JPH0532776B2 - - Google Patents

Info

Publication number
JPH0532776B2
JPH0532776B2 JP2320914A JP32091490A JPH0532776B2 JP H0532776 B2 JPH0532776 B2 JP H0532776B2 JP 2320914 A JP2320914 A JP 2320914A JP 32091490 A JP32091490 A JP 32091490A JP H0532776 B2 JPH0532776 B2 JP H0532776B2
Authority
JP
Japan
Prior art keywords
shared
cache
block
cache memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2320914A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04191946A (ja
Inventor
Masaki Sato
Akira Yamamoto
Teruhiko Oohara
Koichi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP2320914A priority Critical patent/JPH04191946A/ja
Publication of JPH04191946A publication Critical patent/JPH04191946A/ja
Publication of JPH0532776B2 publication Critical patent/JPH0532776B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP2320914A 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式 Granted JPH04191946A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2320914A JPH04191946A (ja) 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2320914A JPH04191946A (ja) 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式

Publications (2)

Publication Number Publication Date
JPH04191946A JPH04191946A (ja) 1992-07-10
JPH0532776B2 true JPH0532776B2 (OSRAM) 1993-05-17

Family

ID=18126682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2320914A Granted JPH04191946A (ja) 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式

Country Status (1)

Country Link
JP (1) JPH04191946A (OSRAM)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2707774B1 (fr) * 1993-07-15 1995-08-18 Bull Sa Procédé de gestion cohérente des échanges entre des niveaux d'une hiérarchie de mémoires à au moins trois niveaux.
FR2707776B1 (fr) 1993-07-15 1995-08-18 Bull Sa Procédé de gestion de mémoires d'un système informatique, système informatique mémoire et support d'enregistrement mettant en Óoeuvre le procédé.
US5604882A (en) * 1993-08-27 1997-02-18 International Business Machines Corporation System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system
JPH11508375A (ja) * 1995-06-26 1999-07-21 ラプラント、パトリック、アール． 流体圧による引っ張り及び同調システム
US5923898A (en) * 1997-05-14 1999-07-13 International Business Machines Corporation System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matched
EP2157507B1 (en) 2007-06-12 2013-05-01 Panasonic Corporation Multiprocessor control device, multiprocessor control method, and multiprocessor control circuit
JP5019222B2 (ja) * 2007-11-13 2012-09-05 エヌイーシーコンピュータテクノ株式会社 マルチプロセッサシステム

Also Published As

Publication number Publication date
JPH04191946A (ja) 1992-07-10

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term