JPH05327680A - Synchronization changeover system - Google Patents

Abstract

PURPOSE:To attain the synchronization changeover by adjusting automatically and optimizingly a relative delay time difference in the unit of multi-frames between active and standby signals. CONSTITUTION:Relative delay time adjustment between active and standby signals in the unit of multi-frames is divided into delay time adjustment in a frame and delay time adjustment in the unit of frames by using an active frame pulse 5 and an active multi-frame pulse 6 obtained by establishing multi- frame synchronization and frame synchronization with respect to an active signal string 2, and a standby frame pulse 6 and a standby multi-frame pulse 8 obtained by establishing multi-frame synchronization and frame synchronization with respect to a standby signal string 4, the timewise lead and lag between the active string and the standby string are discriminated, and while the relative delay time difference between the active and standby signals is set to 0, the signal is used for an input to a synchronization changeover 111 to implement uninterruptible switching between the active and standby signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous switching system, and more particularly to transmitting a signal sequence having a multi-frame structure to working and protection lines and automatically and optimally adjusting a relative delay time difference caused by a difference in transmission paths. The present invention relates to a synchronous switching method for switching.

[0002]

2. Description of the Related Art A conventional synchronous switching system will be described with reference to FIG. This figure is a conventional block diagram. Reference numeral 101 is a frame synchronization circuit, which inputs a working clock 1 and a working signal train 2 on the working line side, establishes frame synchronization and outputs a working frame pulse 5. On the protection line side, the protection clock 3 and the protection signal train 4 are input to establish frame synchronization and output a protection frame pulse 6. Reference numeral 102 denotes a multi-frame synchronization circuit.
The active signal train 2 and the active frame pulse 5 are input, multiframe synchronization is established, and the active multiframe pulse 7 is output. On the protection line side, the protection clock 3, the protection signal train 4, and the protection frame pulse 6 are input, multi-frame synchronization is established, and the protection multi-frame pulse 8 is output.

On the other hand, reference numeral 112 is a counting circuit, and on the working line side, the working multiframe pulse 7 is used as a start signal by the working clock 1 and the spare multiframe pulse 8 is used.
Are input as stop signals, the relative delay time difference between the working / standby is counted based on the working multi-frame pulse 7, and the working counting result 29 is output. On the protection line side, the protection multiframe pulse 8 is used as a start signal by the protection clock 3 and the current multiframe pulse 7 is used.
Are input as stop signals, the relative delay time difference between the working and the spare is counted with the preliminary multi-frame pulse 8 as a reference, and the preliminary counting result 30 is output.

Reference numeral 113 is a comparison circuit, which compares the current counting result 29 and the preliminary counting result 30 on the working line side and outputs the working comparison result 31. On the protection line side, the preliminary count result 30 and the current count result 29 are compared, and the preliminary comparison result 32
Is output. Reference numeral 114 denotes a delay circuit, which delays the current signal sequence 2 and the current frame pulse 5 by using the current clock 1 based on the current comparison result 31 and the current count result 29 on the side of the current line. Output the column 13, active first frame pulse 14. On the backup line side, the backup clock 3 is used to delay the backup signal train 4 and the backup frame pulse 6 based on the backup comparison result 32 and the backup count result 30, and the backup first signal train 16 and the backup first train One frame pulse 17 is output.

The frame synchronization circuit 101, the multi-frame synchronization circuit 102, the counting circuit 112, and the comparison circuit 11
3. The delay circuit 114 constitutes the working line section 109. Similarly, the frame synchronization circuit 101, the multi-frame synchronization circuit 102, the counting circuit 112, the comparison circuit 113, and the delay circuit 114 constitute the protection line unit 110. Reference numeral 111 denotes a synchronization switching circuit, which is a working clock 1 on the working line side, a first frame pulse 14, a first signal train 13, a spare clock 3 on the protection line side, a first frame pulse 17, and a first signal. The column 16 is input, and the non-instantaneous synchronous switching between the working and protection is performed and the clock 27 and the signal sequence 28 are output.

[0006]

In the above-described conventional synchronous switching system, the relative delay time difference between the working and the standby, which is a maximum of 1 multiframe length (bit), is counted, and a variable delay circuit of a maximum 1 multiframe length is provided. It was prepared, and the delay between the working and the spare was adjusted, and the non-instantaneous synchronous switching between the working and the spare was performed. In this way, since the relative delay time difference between the working line and the protection line is counted and adjusted in units of multiframes, it is necessary to count one multiframe length as a counting circuit, and the working multiframes with long cycles are mutually used. Since it is necessary to compare the pulse with the preliminary multi-frame pulse, there is a problem that the efficiency is poor and the adjustment time is longer. An object of the present invention is to provide a synchronous switching system capable of automatically adjusting the relative delay time difference and performing synchronous switching.

[0007]

The present invention comprises a working line section, a protection line section, and a synchronization switching circuit. The working line section inputs a working signal sequence and a working clock, establishes frame synchronization and outputs a working frame pulse, and a working signal sequence, a working clock and a working frame pulse, and multi-frame synchronization. A multi-frame synchronizing circuit that establishes and outputs a working multi-frame pulse, and counts the relative delay time difference between the working frame pulse and the standby frame pulse by means of a working clock, based on the working frame pulse, and outputs the first working count result. One counting circuit, a first comparing circuit for comparing the current first counting result and the preliminary first counting result, and outputting the current first comparing result, the current first comparing result and the current first comparing result. Based on the counting result, the working clock is used to delay the working signal sequence, working frame pulse, and working multi-frame pulse within one frame. A first delay circuit for outputting a first signal train, a first frame pulse and a first multi-frame pulse, and a working first multi-frame pulse and a spare first by a working clock and a first frame pulse. A second counting circuit that counts the relative delay time difference of the multi-frame pulse based on the first working multi-frame pulse and outputs the second working count result, the second working count result and the second backup count result And a second comparison circuit that outputs a second comparison result for current use, and a second clock circuit for current second comparison result and second count result for current use to use the first clock and the first signal sequence and the first frame. A second delay circuit that gives a delay of one frame unit to the pulse and outputs a second signal train and a second frame pulse is included.

Further, the spare line section inputs a spare signal train and a spare clock, establishes frame synchronization and outputs a spare frame pulse, and a spare signal train, a spare clock and a spare frame pulse. , A multi-frame synchronization circuit that establishes multi-frame synchronization and outputs a preliminary multi-frame pulse, and the relative delay time difference between the preliminary frame pulse and the working frame pulse by the preliminary clock is counted based on the preliminary frame pulse, and the preliminary first count is made. A first counting circuit for outputting the result, a first comparing circuit for comparing the preliminary first counting result and the working first counting result, and outputting a preliminary first comparison result, and a preliminary first comparing result And a preliminary 1st frame for the preliminary signal train, the preliminary frame pulse and the preliminary multi-frame pulse using the preliminary clock according to the first counting result. Given a delay of less than, the first of the signal sequence,
A first delay circuit for outputting the first frame pulse and the first multi-frame pulse, and a relative delay time difference between the preliminary first multi-frame pulse and the working first multi-frame pulse by the preliminary clock and the first frame pulse. The second counting circuit that counts the preliminary first multi-frame pulse as a reference and outputs the preliminary second counting result, compares the preliminary second counting result with the working second counting result, and A second comparison circuit for outputting the comparison result of 1) and a preliminary clock based on the preliminary second comparison result and the preliminary second count result, and a frame unit for the first signal train and the first frame pulse. And a second delay circuit for outputting the second signal train and the second frame pulse. Further, the synchronization switching circuit inputs the working clock, the working second frame pulse, the working second signal train, and the spare clock, the spare second frame pulse, and the spare second signal train to input between the working and the spare. Outputs a clock and a signal train by switching to non-instantaneous synchronization.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
Reference numeral 101 is a frame synchronization circuit, which inputs a working clock 1 and a working signal train 2 on the working line side, establishes frame synchronization and outputs a working frame pulse 5. On the protection line side, the protection clock 3 and the protection signal train 4 are input to establish frame synchronization and output a protection frame pulse 6. 102
Is a multi-frame synchronizing circuit, which inputs a working clock 1, a working signal train 2 and a working frame pulse 5 on the working line side, establishes multi-frame synchronization and outputs a working multi-frame pulse 7. On the protection line side, the protection clock 3, the protection signal train 4 and the protection frame pulse 6 are input to establish multi-frame synchronization and output a protection multi-frame pulse 8.

Reference numeral 103 denotes a first counting circuit, which inputs the working frame pulse 5 as a start signal and the spare frame pulse 6 as a stop signal by the working clock 1 on the working line side, and uses the working frame pulse 5 as a reference. The relative delay time difference within one frame is counted, and the current first counting result 9 is output. On the protection line side, the protection clock 3 inputs the protection frame pulse 6 as a start signal and the working frame pulse 5 as a stop signal, and counts the relative delay time difference within one frame with reference to the protection frame pulse 6. The preliminary first counting result 10 is output. Reference numeral 104 denotes a first comparing circuit, which compares the first working counting result 9 and the preliminary first counting result 10 on the working line side and outputs the first working comparing result 11.
The backup line side compares the backup first count result 10 with the working first count result 9 and outputs the backup first comparison result 12.

Numeral 105 is a first delay circuit, and on the working line side, a working signal sequence 2, a working frame pulse 5, and a working frame signal 5 using a working clock 1 according to a working first comparison result 11 and a working first count result 9. A delay of 1 frame or less is given to the active multi-frame pulse 7, and the active first signal train 1
3. Output the first working frame pulse 14 and the first working multi-frame pulse 15. Further, on the protection line side, according to the protection first comparison result 12 and the protection first counting result 10, using the protection clock 3, the protection signal sequence 4, the protection frame pulse 6, and the protection multi-frame pulse 8 are within one frame. , The spare first signal train 16,
The preliminary first frame pulse 17 and the first multi-frame pulse 18 are output.

Reference numeral 106 denotes a second counting circuit, which is a working clock 1 and a working first frame pulse 1 on the working line side.
4, the active first multi-frame pulse 15 is used as a start signal, and the spare first multi-frame pulse 18 is used as a stop signal, and the relative delay time difference in frame units is calculated with reference to the active first multi-frame pulse 15. It counts and outputs the current second counting result 19. On the protection line side, the protection clock 3 is used to input the protection first frame pulse 17 as a start signal and the working first frame pulse 15 as a stop signal. Relative delay time difference is counted and the preliminary second counting result 20 is output.

Numeral 107 is a second comparison circuit, and on the working line side, the working second counting result 19 and the spare second counting result 2
0 is compared, and the current second comparison result 21 is output. or,
The backup line side compares the backup second counting result 20 with the working second counting result 19 and outputs the backup second comparing result 22. Reference numeral 108 denotes a second delay circuit, and on the working line side, the working first signal sequence 13 and the working first frame 13 are used by using the working clock 1 according to the working second comparison result 21 and the working second counting result 19. The pulse 15 is delayed by one frame unit, and the second working frame pulse 23 and the second working signal sequence 24 are output. Further, on the protection line side, according to the protection second comparison result 22 and the protection second counting result 20, one frame unit is used for the protection first signal sequence and the protection first frame pulse 17 using the protection clock 3. A delay is given to output the preliminary second frame pulse 25 and the second working signal sequence 26.

The frame synchronizing circuit 101, the multi-frame synchronizing circuit 102, the first counting circuit 103, the first comparing circuit 104, the first delay circuit 105, the second counting circuit 106, and the second comparing circuit. The working line unit 109 is composed of 107 and the second delay circuit 108. Similarly, the frame synchronization circuit 101, the multi-frame synchronization circuit 102, the first counting circuit 103, the first comparison circuit 104, the first delay circuit 105, the second counting circuit 106, the second comparison circuit 107, and the second comparison circuit 107. The second delay circuit 108 constitutes the protection line unit 110. Reference numeral 111 denotes a synchronous switching circuit, which is a working clock 1 on the working line side, a second frame pulse 23, a second signal train 24, a spare clock 3 on the protection line side, a second frame pulse 25, and a second signal. Input the row 26, and switch the working / standby without instantaneous interruption synchronously and clock 27 and signal row 28.
Is output.

Next, the operation of the configuration shown in FIG. 1 will be described with reference to the timing charts of FIGS. Figure 2
The timing chart when the preliminary frame pulse is delayed from the current frame pulse. FIG. 3 is a timing chart when the current frame pulse is delayed from the preliminary frame pulse. FIG. 4 is a timing chart in the case where the preliminary multi-frame pulse is delayed from the working multi-frame pulse, which is the state after the output of the first delay circuit. FIG. 5 is a timing chart when the active multi-frame pulse is delayed from the preliminary multi-frame pulse, and shows the state after the output of the first delay circuit.

First, the delay adjustment within a frame will be described. On the transmitting side, the same signal is transmitted as the current signal sequence 2 and the backup signal sequence 4. Working signal sequence 2 is working line section 109.
Frame synchronization circuit 101 establishes frame synchronization, and multiframe synchronization circuit 102 establishes multiframe synchronization. On the other hand, in the spare signal train 4, frame synchronization is established in the frame synchronization circuit 101 of the protection line unit 110, and multiframe synchronization is established in the multiframe synchronization circuit 102. The relative delay time difference between the active frame pulse 5 and the backup frame pulse 6 is
The working side is counted with the working frame pulse 5 as a reference, and the protection side is counted with the protection frame pulse 7 as a reference. The working first counting result 9 (= x bits), the backup first counting result 10
(= Y bits) is output.

Now, as shown in FIG. 2, from the current frame pulse 5 (FIG. 2A) to the preliminary frame pulse 6 (FIG. 2).
When (b)) is delayed, comparing the counting results, x <
It becomes y. This indicates that when the delay amount is given by the first delay circuit on the working side, the delay amount given is smaller. First comparison circuit 1 of working line section 109
04 determines that the own line (= working line) is ahead in time and outputs the first working comparison result 11. or,
The first comparison circuit 104 of the protection line unit 110 determines that the own line (= protection line) is behind in time, and outputs the protection first comparison result 12.

The first delay circuit 105 of the working line section 109
Is a current signal sequence 2, a current multi-frame pulse 7, and a current frame pulse 5 (see FIG. 2A), based on the current first count result 9 (x = bit) and the first current comparison result 11 (= advance). ) Is delayed by x bits and is output as a current first signal sequence 13, a current first multi-frame pulse 15 and a current first frame pulse 14 (FIG. 2 (c)). On the other hand, the first delay circuit 10 of the protection line unit 110
5 is a delay of “0” bits with respect to the preliminary signal sequence 4, the preliminary multi-frame pulse 8 and the preliminary frame pulse 6 (FIG. 2B) due to the preliminary first comparison result 12 (= delay), that is, The signals are output as the preliminary first signal train 16, the preliminary first multi-frame pulse 18, and the preliminary first frame pulse 17 (= preliminary frame pulse 6) without delay.

When the working line side is delayed as shown in FIG. 3, x> y is obtained as the counting result, so the working first comparison result 9 (= delay) and the spare first comparison result 10
(= Advance) As a result, the first delay circuit 105 of the working line unit 109 gives the delay amount as “0”, that is,
Without delay, the first delay circuit 105 of the protection line unit 110
Gives a delay amount of y bits. When the relative delay time difference between the frames of the working line and the protection line = 0 (= x = y), no delay is given to either of the first delay circuits.

Next, the delay adjustment for each frame will be described. The relative delay time difference between the working first multi-frame pulse 15 and the backup first multi-frame pulse 18 is based on the working first multi-frame pulse 15 on the working side and the backup first multi-frame pulse 18 on the protection side. Are counted and output as the current second counting result 19 (= X frame) and the preliminary second counting result 20 (= Y frame). Now, as shown in FIG. 4, when the preliminary first multi-frame pulse 18 (FIG. 4 (d)) is delayed from the working first multi-frame pulse 15 (FIG. 4 (b)), the counting results are compared. Then X <Y. This is
This indicates that the first spare signal train 16 (= spare signal train 4) on the spare side is behind the first working signal train 13 (= working signal train 2) on the working side. At this point in time, the delay adjustment within the frame has already been completed, so the current first frame pulse 14 (FIG. 4 (a)) = preliminary first frame pulse 17 (FIG. 4 (c)). ..

The second comparison circuit 107 of the working line section 109
Judges that its own line (= working line) is ahead in time, and outputs the second working comparison result 21. In addition, the second comparison circuit 107 of the protection line unit 110 determines that the own line (= protection line) is behind in time, and outputs the second protection comparison result 22. The second delay circuit 108 of the working line unit 109 uses the working second counting result 19 (= X frames) and the working second comparison result 21 (= advance) to determine the working first signal sequence 13 and working first signal. Frame pulse of 14
A delay of X frames is given to (Fig. 4 (b)), and the signal is output as the second signal train 24 for current use and the second frame pulse 23 for current use (Fig. 4 (e)). On the other hand, the second delay circuit 108 of the protection line unit 110 causes the protection second comparison result 22 (=
Delay), the spare first signal train 16 and the spare first frame pulse 17 (FIG. 4 (d)) are delayed by "0" frames, that is, the spare second signal train 26 without delay.
The preliminary second frame pulse 25 (= preliminary first frame pulse 17) is output.

When the working line side is delayed as shown in FIG. 5, the counting result is X> Y. Therefore, the working second comparison result 21 (= delay) and the backup second comparison result 22.
(= Advance) As a result, the second delay circuit 108 of the working line unit 109 gives the delay amount as “0”, that is,
The second delay circuit 108 of the protection line unit 110 without delay
Gives the amount of delay for Y frames. Further, when the relative delay time difference between the frames of the working line and the protection line = 0 (= X = Y), no delay is given to either of the second delay circuits. At the input of the line switching circuit 111, since the relative delay time difference between the working line and the protection line is "0", it is possible to switch between the working and protection lines without interruption.

In the above embodiment, the case of FIGS. 2 and 4 has been described, but the same effect can be obtained in the case of the combination of FIGS. 3 and 5 or the combination of FIGS. Needless to say. Further, the fluctuation of the delay amount due to the frequency fluctuation can be dealt with by providing a protection circuit in the delay circuit to protect the counting result and a delay fluctuation absorbing circuit in the synchronization switching circuit. ..

[0024]

As described above, according to the present invention, a circuit for counting the relative delay time of each frame within the frame is provided for each of the working / spare, and means for determining which of the working / spare is delayed is provided. Regarding the circuit, it suffices to provide two counting circuits for the frame length and N frames, and the delay amount can be easily set optimally and all can be set automatically. There is an effect that the method can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Figure 2]

5 is a timing chart for explaining the operation of the configuration of FIG.

FIG. 6 is a block diagram of a conventional synchronization switching method.

[Description of Reference Signs] 101 frame synchronization circuit 102 multi-frame synchronization circuit 103 first counting circuit 104 first comparison circuit 105 first delay circuit 106 second counting circuit 107 second comparison circuit 108 second delay circuit 109 working line unit 110 protection line unit 111 synchronous switching circuit

Claims (1)

[Claims] 1. A N-frame (N: integer of 2 or more) signal train forming one multi-frame is transmitted to a working line and a protection line, and a relative delay time difference caused by a difference in a transmission path is adjusted so that there is no interruption. In the synchronous switching method in which the working line is switched to the protection line, the working line section inputs a working signal train and a working clock, establishes frame synchronization, and outputs a working frame pulse, and a working signal train and working frame. A multi-frame synchronizing circuit that inputs a clock and a working frame pulse, establishes multi-frame synchronization and outputs a working multi-frame pulse, and a relative delay time difference between the working frame pulse and the backup frame pulse based on the working clock based on the working frame pulse. A first counting circuit that counts and outputs a first working count result, a first working count result and a spare first counting result And a first comparison circuit that outputs a first working comparison result, and a working signal sequence, working frame pulse, and working multiframe using a working clock based on the first working comparison result and the first working count result. Delay the pulse within 1 frame,
A first delay circuit for outputting the first frame pulse and the first multi-frame pulse, and a relative delay time difference between the working first multi-frame pulse and the spare first multi-frame pulse according to the working clock and the first frame pulse. The second counting circuit which counts the current first multi-frame pulse as a reference and outputs the current second counting result, and compares the current second counting result and the preliminary second counting result, The second comparison circuit that outputs the comparison result of 1) and the current second clock and the current second count result are used, and the first clock is used for each one frame unit for the first signal sequence and the first frame pulse. And a second delay circuit for outputting the second signal train and the second frame pulse, while the spare line section inputs the spare signal train and the spare clock to establish the frame synchronization and to perform the preliminary synchronization. A frame synchronization circuit that outputs a frame pulse, a multi-frame synchronization circuit that inputs a preliminary signal train, a preliminary clock, and a preliminary frame pulse, establishes multi-frame synchronization and outputs a preliminary multi-frame pulse, and a preliminary frame pulse by a preliminary clock And the relative delay time difference between the working frame pulse and the spare frame pulse as a reference, and compares the spare first count result and the working first count result with the first counting circuit that outputs the spare first count result. , A first comparison circuit for outputting a preliminary first comparison result, and a preliminary signal sequence, a preliminary frame pulse and a preliminary multi-frame pulse using a preliminary clock according to the preliminary first comparison result and the preliminary first counting result. The first signal train, the first frame pulse, and the first multi-frame pulse. The first delay circuit to do, the relative delay time difference between the preliminary first multi-frame pulse and the working first multi-frame pulse by the preliminary clock and the first frame pulse is counted based on the preliminary first multi-frame pulse, A second counting circuit for outputting the preliminary second counting result, a second comparing circuit for comparing the preliminary second counting result and the working second counting result, and outputting a preliminary second comparison result, and the preliminary Based on the second comparison result and the preliminary second counting result, the preliminary clock is used to delay the first signal sequence and the first frame pulse by one frame unit, and the second signal sequence and the second signal sequence are delayed. Includes a second delay circuit that outputs a frame pulse, and inputs a working clock, a working second frame pulse, a working second signal train, and a spare clock, a spare second frame pulse, and a spare second signal train. , Working / A synchronous switching system characterized by having a synchronous switching circuit for performing a non-instantaneous synchronous switching between spares and outputting a clock and a signal train.