JP2507978B2 - Line switching device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line switching apparatus for switching between a working line and a protection line on the receiving side of a digital communication system having a working line and a protection line without bit error and without interruption.

[0002]

2. Description of the Related Art As is well known, in a digital communication system, regardless of whether it is wired or wireless, it has a 1: 1 working line and a protection line depending on the size, and a plurality of working lines. There is a case where there is one protection line, and in either case the protection line is switched to the protection line at the time of maintenance inspection, and when the working line is restored, the protection line is switched to the working line again. Although the line can be maintained, the line switching device that performs such switching is required to have a function that can be performed without causing a bit error in the transmitted data signal sequence.

There are various line switching devices of this type, and one of them is shown in FIG. 3, for example. This line switching device adjusts the delay difference due to the difference between the transmission lines of the working line and the protection line to a certain amount within the non-instantaneous-interruption synchronous switching range, and then uses a memory circuit or a serial-parallel conversion circuit to set a bit in the data signal string. It is designed so that the lines can be synchronously switched without error. The outline will be described below.

In FIG. 3, the working line delay circuit 2 is provided with a shift register capable of delaying the input data signal sequence by N bits (N is a natural number) at the maximum, and the working line delay circuit 2 controls the data signal sequence 101 transmitted through the working line. N by signal 111
(N is an integer satisfying 0 ≦ n ≦ N) Bit delay.

Similarly, the protection line delay circuit 4 is provided with a shift register capable of delaying the input data signal sequence by at most M (N is a natural number) bits, and the data signal sequence 201 transmitted through the protection line is fed to the protection control signal. 121 by j (j: 0
≤ j ≤ M) bit delay.

The non-instantaneous-interruption synchronization switching circuit 5 is provided with a memory circuit or a serial / parallel conversion circuit, and the phase difference between the output data signal sequence 401 of the working line delay circuit 2 and the output data signal sequence 601 of the protection line delay circuit 4 is reduced. When within ± L (L is a natural number) bits, the output data signal sequence 4 of the active line delay circuit 2 is generated without any bit error by the active / standby selection signal 141 without any interruption.
01 and the output data signal sequence 601 of the protection line delay circuit 4 are switched to output the data signal sequence 701. It should be noted that the range that can be switched without bit error without any interruption is the above-mentioned no-interruption synchronous switching range, which is a range of ± L bits,
This is determined by the configuration of the memory circuit or the serial / parallel conversion circuit.

Next, the operation will be specifically described with reference to FIG. To simplify the description, the maximum delayable amount N of the working line delay circuit 2 and the maximum delayable amount M of the protection line delay circuit 4 are both 20 bits, and L is 4 bits. The delay difference due to the difference in transmission route between the working line and the protection line is 15 bits. For example, as shown in FIGS. 4A and 4B, the data signal sequence 101 transmitted on the working line is the protection line. 15 more than the transmitted data signal sequence 201
It is assumed that it is received with a bit delay. In other words, this is the case when returning from the protection line to the working line.

The delay difference between the working line and the protection line is detected by comparing the frame pulses outside the drawing, and the working control signal 111 and the protection control signal 121 are generated based on this, but in the above example, the data signal sequence 101 is Since it is delayed, the set delay amount n by the working control signal 111 of the working line delay circuit 2 becomes n = 0 bits, and the output data signal string 401 of the working line delay circuit 2 becomes the same as that in FIG. 4 (A). .

On the other hand, as for the delay amount j set by the protection control signal 121 of the protection line delay circuit 4, the first bit of the reception data signal sequence 201 (FIG. 4B) of the protection line is the reception data signal sequence 101 (of the working line). Since it is an amount necessary to set within a range of 4 bits before and after the first bit of FIG. 4 (A) (non-instantaneous sync switching range), 15-4 = 11 bits (FIG. 4).
(C)) and above, and 15 + 4 = 19 bits (see FIG. 4).
(D)) It is set to a predetermined value within the following range.

In the non-instantaneous-interruption synchronization switching circuit 5, the data between the data signal sequence 401 of the working line (FIG. 4A) and the data signal sequence 601 of the protection line (FIG. 4C and the same (D)) is stored. Signal sequence), for example, if a memory circuit is provided, these are delayed by a predetermined bit, and a working / spare selection signal 141 is given from outside the figure at an appropriate timing when the leading bit positions are aligned. From the working line to the working line without any bit error and without interruption, and outputs the data signal sequence 701 of the working line.

[0011]

As described above, after adjusting the delay difference due to the difference in the transmission path between the working line and the protection line, the line is transmitted to the data signal train without bit error by using the memory circuit or the serial / parallel conversion circuit. In the line switching device capable of switching, the delay difference is adjusted so as to be within the non-interrupted synchronous switching range, but, for example, the transmission route of the protection line is changed during the operation of the working line, If the data signal sequence transmitted on the protection line is delayed beyond the range of the hitless synchronous switching, the phase difference between the data signal string of the working line and the protection line can be switched without any interruption just by adjusting the delay amount of the protection line delay circuit. In some cases, it becomes impossible to adjust within the range.

In such a case, the delay amount of the data signal sequence transmitted on the working line must be changed.
In the conventional device, since the working line is in operation, an error occurs in the data signal sequence in the working line delay circuit when the delay amount is changed, and it becomes impossible to switch to the protection line without interruption. There is.

An object of the present invention is to change the delay amount by changing the transmission route of either the working or protection line,
Even when the delay difference between both lines exceeds the range without synchronous switching without interruption, the amount of delay can be adjusted without causing errors in the data signal sequence, and synchronous switching of lines can be performed without interruption. It is to provide a line switching device.

[0014]

In order to achieve the above object, a line switching apparatus according to the present invention has the following configuration. That is, the line switching device of the present invention adjusts the delay difference due to the difference between the transmission paths of the working line and the protection line to a certain amount within the non-instantaneous-interruption synchronous switching range, and then uses the memory circuit or the serial-parallel conversion circuit to perform data transfer. A line switching device for performing line synchronous switching without bit error in a signal sequence;
The data signal strings of one of the working line and the protection line are
Alternate delay control with different or same delay amount
Adjusts their phase difference to a fixed amount within the range without instantaneous interruption switching
Error in either delayed data signal sequence.
First means for switching and outputting without causing noise;
The data signal string of the other line of the protection line and the protection line is
Phase difference with the output data signal train of 1 means no interruption sync switching
Delay control is performed so that the amount is within a certain range, either one
Switching the data signal sequence of the same without causing bit error
It is characterized in that the Ru provided with; a second means for outputting. Specifically, the first means is the working line and the protection line.
The data signal sequence transmitted by one of the lines is branched into two.
And a branch circuit; each data branched into two by the branch circuit
Delay signal sequence by first and second control signals respectively
A first delay circuit and a second delay circuit;
A parallel conversion circuit is provided, and the outputs of the first and second delay circuits are provided.
The first selection when the phase difference between the force data signal sequences is within a certain amount.
One output data signal sequence to the other output depending on the selection signal
Cuts without interruption to the data signal sequence without any bit errors.
Equipped with a first non-instantaneous sync switching circuit for switching and outputting;
Get The second means is to use the other of the working line and the protection line.
The data signal string transmitted by the line is used as the third control signal.
Therefore, a third delay circuit for delaying; a memory circuit or
The first non-instantaneous-interruption synchronization switching circuit including a serial-parallel conversion circuit
Output data signal sequence and output data of the third delay circuit
When the phase difference of the signal train is within a certain amount, the second selection signal
From one output data signal sequence to the other output data signal
Switching to a column without any bit error and outputting without interruption
A second non-instantaneous-interruption synchronization switching circuit that operates.

[0015]

Next, the operation of the line switching device of the present invention constructed as described above will be described. In the present invention, the alternate delay control of the two delay circuits in one line is performed so that the phase difference between the output data signal trains is set to a fixed amount within the non-interruptive sync switching range of the first non-interruptive sync switching circuit. Repeat while adjusting
The phase difference between the output data signal sequence of the first hitless sync switching circuit and the output data of the delay circuit of the other line is set to a fixed amount within the hitless sync switching range of the second hitless sync switching circuit. I am able to do it. As described above, the hitless synchronization switching range depends on the configuration of the memory circuit or the serial-parallel conversion circuit included in the hitless synchronization switching circuit.

One line is a working line or a protection line in a system having a working line and a protection line at 1: 1 but is a working line in a system having n: 1.

Therefore, even if the delay amount is changed by changing the transmission route of either the working line or the protection line, and the delay difference between the two lines exceeds the non-instantaneous sync switching range, the data signal The amount of delay can be adjusted without causing errors in the queue, and line synchronous switching can be performed without interruption.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a line switching device according to one embodiment of the present invention. In FIG. 1, the line switching device of the present embodiment considers a system having a working line and a protection line at n: 1,
Of the two data signal sequences given to the (second) non-interruptible synchronization switching circuit 5, the backup data signal sequence is formed by the backup line delay circuit 4 as the third delay circuit as in the conventional case, but the active data signal The column is divided into a branch circuit 1, two working line delay circuits (2-1, 2-2) as first and second delay circuits, and a working no-interruption synchronization switching circuit 3 as a first no-interruption synchronization switching circuit. It is formed by and.

In FIG. 1, a branch circuit 1 branches a data signal sequence 101 transmitted through a working line into two directions. One branch output data signal sequence 301 is input to the working line delay circuit 2-1 and the other branch output data signal sequence 30
2 is input to the working line delay circuit 2-2.

The working line delay circuits 2-1 and 2-2 each include a shift register capable of delaying the input data signal sequence by at most N (N is a natural number) bits. The working line delay circuit 2-1 outputs the first branch output data signal sequence 301 to the first branch output data signal sequence 301.
N (n: 0) according to the active control signal 111 which is the control signal of
≤ n ≤ N) delay. This corresponds to the working line delay circuit 2 in FIG. In addition, the working line delay circuit 2-2 uses the other branch output data signal sequence 302 by the working control signal 112 which is the second control signal.
(M: an integer such that 0 ≦ m ≦ N) Bit delay.

The active non-instantaneous-interruption switching circuit 3 is provided with a memory circuit or a serial / parallel conversion circuit similarly to the non-instantaneous-interruption synchronous switching circuit 5, and the output data signal string 401 of the active line delay circuit 2-1.
And the phase difference between the output data signal sequence 402 of the working line delay circuit 2-2 is within ± K (K is a natural number) bits, the first
Of the data signal by switching between the output data signal sequence 401 of the working line delay circuit 2-1 and the output data signal sequence 402 of the working line delay circuit 2-2 without any bit error by the working selection signal 131, which is a selection signal of The column 501 is output.

On the other hand, the protection line delay circuit 4 is provided with a shift register capable of delaying the input data signal sequence by at most M (M is a natural number) bits as described above, and the data signal sequence 201 transmitted through the protection line is transmitted. The preliminary control signal 121, which is the third control signal, delays j bits (j: 0≤j≤M).

The no-interruption synchronization switching circuit 5 includes a memory circuit or a serial-parallel conversion circuit, and outputs an output data signal sequence 501 of the active no-interruption synchronization switching circuit 3 and an output data signal sequence 601 of the protection line delay circuit 4. When the phase difference is within ± L (L is a natural number) bits, the current selection / preliminary selection signal 1 which is the second selection signal
41 outputs the data signal sequence 701 by switching between the output data signal sequence 501 of the active non-interruption synchronization switching circuit 3 and the output data signal sequence 601 of the protection line delay circuit 4 without interruption and without bit error.

Next, referring to FIG. 2, when the operation is carried out on the working line, a change occurs in the transmission route due to maintenance or the like on the protection line, so that the data signal is changed on the working line which is the working line. The operation of adjusting the delay amount without causing an error in the columns will be described. Even in the opposite case, the same operation is performed because the delay difference between both lines is only the difference between the lead phase and the lag phase.

In order to simplify the explanation, both the maximum delayable amount N of the working line delay circuits (2-1, 2-2) and the maximum delayable amount M of the protection line delay circuit 4 are set to 20 bits, and the working non-instantaneous Both K, which defines the non-instantaneous-interruption synchronization switching range of the non-instantaneous-interruption switching circuit 3, and L, which defines the non-instantaneous-interruption synchronous switching range of the non-instantaneous-interruption switching circuit 5, are 4 bits.

As shown in FIGS. 2A and 2B, it is assumed that the data signal sequence 201 transmitted on the protection line is received 15 bits later than the data signal sequence 101 transmitted on the working line. To do. Therefore, the delay setting amount j by the standby control signal 121 of the standby line delay circuit 4 becomes j = 0, and the input data signal sequence 601 to the non-instantaneous-interruption synchronization switching circuit 5 is shown in FIG.
It is the same as (B). This is because the phase difference between the output data signal string 501 of the current hitless sync switching circuit 3 and the data signal string 201 transmitted on the protection line is calculated as the hitless sync switching range of the hitless sync switching circuit 5. Although it is required to be within (± L = ± 4 bits), it is realized as follows.

The operating data signal train of the working line is shown in FIG.
(A), which is output from the working line delay circuit 2-1, so that the working selection signal 131 selects the data signal sequence 401 in the working hitless synchronous switching circuit 3. Therefore, first, the working line delay circuit 2-
2 is controlled to delay the branch output data signal sequence 302 by m = 4 bits, and the output data signal sequence is as shown in FIG.

That is, the input data signal sequence 401 (FIG. 2 (A)) and the input data signal sequence 402 (FIG. 2) to the active hitless sync switching circuit 3 are used.
After the phase difference of (C) is set within the range of K = 4 bits that defines the hitless sync switching range of the active hitless sync switching circuit 3, the data signal sequence 402 is set by the working selection signal 131.
Is selected, the output data signal sequence 501 of the active non-instantaneous-interruption switching circuit 3 changes from the data signal sequence 401 (FIG. 2A) to the same 402 (FIG. 2C) without a bit error. You can switch it off .

Next, the working line delay circuit 2-1 converts the input data signal sequence 101 (FIG. 2A) into the working control signal 111.
Then, the output data signal sequence 401 is delayed by n = 8 bits as shown in FIG. Then, the data signal sequence 4
02 (FIG. 2 (C)) is within the range of K = 4 bits which defines the non-instantaneous-interruption synchronous switching range of the active non-instantaneous-interruption synchronous switching circuit 3, so that the data signal string is selected by the active selection signal 131. Four
If 01 is selected, the output data signal sequence 501 of the active non-instantaneous-interruption switching circuit 3 becomes the data signal sequence 402 (see FIG. 2).
(C)) to the same 401 (FIG. 2D) without any bit error and without interruption .

As described above, the delay amount settings of the working line delay circuits 2-1 and 2-2 are alternately changed within the hitless sync switching range of the working hitless sync switching circuit 3, and finally, In the example of FIG. 2, the output data signal string 402 of the working line delay circuit 2-2 is delayed as shown in FIG. 2 (E), and the input data of the working non-instantaneous-interruption synchronous switching circuit 3 is delayed by the working selection signal 131. The signal trains 401 and 402 are switched to an output data signal train 501 without any bit error and without interruption, as shown in FIG.
The data signal sequence shown in (F) is obtained.

The phase difference between the data signal train 501 and the data signal train 601 of the protection line shown in FIG. 2 (F) is within the hitless sync switching range of the hitless sync switching circuit 5 (FIG. 2B). Therefore, it is possible to switch to the protection line thereafter without interruption without causing a bit error.

[0032]

As described above, in the line switching apparatus of the present invention, the alternate delay control of the two delay circuits in one line is performed by setting the phase difference between the output data signal sequences to be the first.
A certain amount of repeated while adjusting in the hitless sync switching range hitless sync switching circuit, the output data of the output data signal sequence and a delay circuit of the other line of the first hitless sync switching circuit Since the phase difference can be set to a fixed amount within the non-instantaneous-interruption synchronous switching range of the second non-instantaneous-interruption synchronous switching circuit, it is possible to change the transmission route of either the working line or the standby line by changing the transmission route. Even if the delay amount is changed and the delay difference between both lines exceeds the non-interruptive synchronization switching range, the delay amount can be adjusted without causing an error in the data signal sequence, and the line can be synchronized without interruption. There is an effect that can be switched.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a line switching device according to an embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the present invention.

FIG. 3 is a configuration block diagram of a conventional line switching device.

FIG. 4 is a time chart for explaining the operation of the conventional device.

[Explanation of symbols]

 1 Branch circuit 2-1 Working line delay circuit 2-2 Working line delay circuit 3 Working non-instantaneous interruption synchronization switching circuit 4 Backup line delay circuit 5 Non-instantaneous interruption synchronization switching circuit

Claims (5)

(57) [Claims] 1. A bit error in a data signal sequence using a memory circuit or a serial / parallel conversion circuit after adjusting a delay difference due to a difference between transmission paths of a working line and a protection line to a certain amount within a non-instantaneous-interruption synchronous switching range. And a line switching device for synchronously switching the lines; the line switching device has different or the same data signal strings for one of the working line and the protection line.
Alternate delay control with one delay amount
Is adjusted to a fixed amount within the non-instantaneous sync switching range.
Causes bit error in one of the delayed data signal sequences
First means for switching output without switching; Working line and backup circuit
The data signal train of the other line of the line is transferred to the output signal of the first means.
A certain amount of phase difference with the data signal sequence within the range without instantaneous interruption synchronization switching
Delay control so that
Second output for switching output without causing bit error
Protection switch, characterized in that Ru provided with; stage and. 2. The first means is one of a working line and a protection line.
A branch that splits the data signal sequence transmitted over the line
A circuit; each data signal string branched into two by the branch circuit
Are delayed by the first and second control signals, respectively.
A first delay circuit and a second delay circuit; a memory circuit or a serial-parallel converter
An output circuit of the first and second delay circuits.
First selection signal when the phase difference between the signal trains is within a certain amount
From one output data signal sequence to the other output data
Switching to non-interruption without causing bit errors in the signal sequence
And a first non-interruptive synchronization switching circuit for outputting
The line switching device according to claim 1, wherein: 3. The second means is the other of the working line and the protection line.
The third control signal is the data signal string transmitted by the line
A third delay circuit for delaying by; a memory circuit or
The first non-instantaneous-interruption synchronization switching circuit including a serial-parallel conversion circuit
Output data signal sequence and output data of the third delay circuit
When the phase difference of the signal train is within a certain amount, the second selection signal
From one output data signal sequence to the other output data signal
Switching to a column without any bit error and outputting without interruption
A second non-instantaneous-interruption synchronous switching circuit for
The line switching device according to claim 1, which is characterized in that. 4. One of the lines is a working line and a protection line.
1: 1 system has either working or protection line
The method according to claim 1, characterized in that Line switching equipment
Place. 5. One of the lines is a working line and a protection line.
It is a working line in a system with n: 1;
The line switching device according to claim 1, which is a characteristic.