JPH05327497A - A/d converter - Google Patents

Abstract

PURPOSE:To prevent the influence of the fluctuation of the power source voltage on the conversion data by providing a reference voltage forming circuit to be applied to the low potential side terminal of the ladder resistance and a bias voltage forming circuit to be applied to the output of an input amplifier. CONSTITUTION:The A/D converter is provided with a reference voltage forming circuit 15 containing a Zener diode 2D driven by the power source voltage Vcc and the current limiter resistance Ra, forming the prescribed reference voltage Vref by in seveis adding the voltage drop of the current limiter resistance Ra and the voltage obtained by dividing the voltage drop of the Zener diode 2D, and driving one low-potential terminal 11 of a ladder resistance 6 by the reference voltage Vref through an amplifier 16. Further, it is provided with a bias voltage forming circuit 17 having amplifiers 18 and 19 shifting the zero line of the analog a/c signal Vin to be converted to the prescribed voltage level by taking the central potential voltage Vm in from a terminal 14 of the ladder resistance 6 to be amplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to a high speed A / D converter for converting an analog image signal into a digital signal.

[0002]

2. Description of the Related Art A parallel comparison type A / D converter generally called a flash converter is used for high-speed digital conversion of analog image signals and the like, and an A / D converter using this type of element is used. An example of is shown in FIG. The parallel comparison type A / D converter includes, for example, a ladder resistor 6, a comparator 7 and an encoder 8 as indicated by reference numeral 5. This ladder resistor 6 is for forming the comparison threshold voltage of the comparator 7. For example, the power supply voltage + Vcc of the device is applied to one terminal 10 of the ladder resistor 6, and the other terminal 11 is connected via the resistor Rs. Connected to the ground side.

Assuming that the A / D converter 5 is, for example, an element for 8 bits, the ladder resistor 6 is 8 to the power of 2 or R1 to R256 as shown in the figure.
It is composed of a group of resistors, and is connected from the power supply voltage Vcc to the terminal 10,
A current flows to the ground side through the ladder resistor 6, the terminal 11 and the resistor Rs. Assuming that the voltage generated in the resistor Rs by this current is the reference voltage Vref, the ladder resistor 6 is connected to the power source voltage Vref.
The voltage of the difference between cc and the reference voltage Vref is divided by, for example, 256 resistors R1 to R256 to form 255 threshold voltages V1, ..., V255.

In this case, if the resistance connected to the low potential side terminal 11 of the ladder resistance 6 is R1 and the resistance connected to the power supply voltage Vcc side terminal 10 is R256, the value of each resistance element is, for example, R1 = Although R2 = ... = R256 = R [Ω] is set, the resistors R1 and R256 at both ends may be set to R1 = R256 = R / 2 [Ω]. In any case, however, each threshold voltage is sequentially increased from V1 to V255 by a voltage difference corresponding to 1LSB, that is, (Vcc-Vref) / 255. When the power supply voltage Vcc is constant, the magnitude of the voltage corresponding to 1LSB is determined by the magnitude of the reference voltage Vref generated in the resistor Rs, so that the value of the resistor Rs is generally adjustable.

The comparator 7 is composed of, for example, 255 comparator groups A1 to A255, and a threshold voltage is applied from the ladder resistor 6 to one input terminal of each comparator. An analog input signal Vin is commonly applied to the other input terminal of each comparator via the terminal 9 of the A / D converter 5. Here, for example, the comparator A1 to which the threshold voltage V1 is applied
Is the lowest comparator, and the comparator A255 to which the threshold voltage V255 is added is the highest comparator, each comparator simultaneously compares the input signal with the respective threshold voltage, and 1 (on) or 0 (off). Emits the comparison output of.

The encoder 8 is, for example, a combination of gate elements (not shown), and has the above-mentioned 255 comparators A1.
-The comparison output of 0 or 1 issued from A255 is received in parallel, converted into 8-bit binary signal data, and sent out from the output terminal 12.

In FIG. 3, when the converted AC analog signal Vin is applied to the input terminal 1 of the device, the signal is applied to the signal input terminal 9 of the A / D converter 5 via the amplifiers 2, 3 and 4. Here, the amplifier 2 is, for example, an inverting amplifier including a range switch (not shown), and performs range switching so that the magnitude of the input signal Vin is within the allowable input voltage range (Vref-Vcc) of the A / D converter 5. To do. It is preferable that the zero line of the inverted output voltage of the amplifier 2 be in the vicinity of the center of the allowable input voltage range. Therefore, for example, a DC bias voltage -Vb for level shifting is applied. The amplifiers 3 and 4 are, for example, a gain 1 inverting amplifier and a gain 1 non-inverting amplifier.

Next, an outline of the operation will be described with reference to FIG. When a relatively low level converted AC voltage signal Vin as shown in FIG. 4B is applied to the input terminal 1 of the device, the amplifier 2 switches to an appropriate range and performs inverting amplification. A bias voltage -Vb for zero line shift is applied to the output, and the output becomes as shown in Fig. 4B. The amplifier 3 inverts and amplifies this voltage signal with a gain of 1 as shown in FIG. 8C, and the amplifier 4 non-inverts and amplifies the output of the amplifier 3 with a gain of 1 as shown in FIG.

In FIG. 4D, the power supply voltage Vcc,
Reference voltage Vref, comparators A1, A2, ..., A2
53, A254, A255 threshold voltages V1, V2
, V254, V255 and the voltage signal Vin have a level relationship as shown in the figure, for example, the output of the comparator when continuously compared at a predetermined timing is as shown in FIGS. .. In this case, the encoder 8 outputs the comparison output of each comparator at a certain temporary point T.
The time required to convert to 8-bit binary signal data differs depending on the element.
When s is set, the voltage signal Vin can be A / D converted at high speed. The display unit 13 temporarily stores binary signal data sent from the encoder 12 in, for example, a memory, and displays the signal waveform on a CRT or on a recording paper.

[0010]

The above-mentioned conventional device is relatively simple in construction, and is suitable for visually observing the waveform of an input signal. However, for example, when the power supply voltage changes, the threshold voltage of each comparator changes, so that the digital conversion data may have different values even with input signals of the same level. Therefore, it is not always applicable to electronic measuring instruments that measure the absolute level of the input signal.

As an example, in FIG. 5 which is obtained by extracting the ladder resistance of FIG. 3, the reference voltage Vref is obtained by dividing the power supply voltage Vcc by the resistance Rs and the ladder resistance groups R1 to R256. Therefore, Vref = Vcc × Rs / (Rs + R1 + R2 + ...
+ R256). Here, for simplification of description, for example, if R1 = R2 = ... = R256 = R [Ω], then Vref = Vcc × Rs / (Rs + R × 256) (1) Assuming that the reference voltage Vref and the threshold voltage V1 and the voltage difference between adjacent threshold voltages are Vδ, Vδ = (Vcc-Vref) / 256 (2) Equation (1) is added to the above equation. When substituting, Vδ = Vcc {1-Rs / (Rs + R × 256)} / 256 (3)

Next, the power supply voltage Vcc changes to Vcc '.
When the reference voltage at the time of is Vref ′ and the voltage difference between the adjacent threshold voltages is Vδ ′, Vref ′ = Vcc ′ × Rs / (Rs + R × 256) ...... ( 4) Vδ ′ = (Vcc′−Vref ′) / 256 = Vcc ′ {1-Rs / (Rs + R × 256)} / 256 (5) When Formula (4) is divided by Formula (1), Vref ′ / Vref = Vcc '/ Vcc From the above formula, Vref' = Vref (Vcc '/ Vcc) Let VV be the variation of the power supply voltage, and Vcc' = Vcc ± ΔV, Vref '= Vref (Vcc ± ΔV ) / Vcc = Vref (1 ± ΔV / Vcc) (6) Further, when the equation (5) is divided by the equation (3), Vδ ′ / Vδ = Vcc ′ / Vcc. Vδ ′ = Vδ (1 ± ΔV / Vcc) (7) is obtained in the same manner as in the case of deriving the equation (6). According to the equations (6) and (7), when the power supply voltage changes, both the reference voltage and the threshold voltage difference change at the same rate as the rate of change.

By the way, assuming that the power supply voltage Vcc is 5 [V] and the reference voltage Vref is 3 [V] in the conventional device, the voltage Vδ of the difference between the threshold voltages is calculated from the equation (2). Vδ = (5-3) /256=0.00781 [V]. In this case, for example, the magnitude of the 200th lowest threshold voltage V200 is V200 = Vref + Vδ × 200 = 3 + 0.00781 × 200 = 4.562 [V]. Therefore, if the input signal voltage Vin is 4.5620 <Vin ≦ 4.5620 + 0.00781, that is, 4.5620 <Vin ≦ 4.5698 (8), from Vcc-Vδ to Vcc, that is, 4 In an A / D converter that converts an input voltage from .9922 [V] to 5 [V] into a FF as a full-scale voltage, the signal Vin is a binary corresponding to a threshold voltage of V200 of 4.562 [V]. Data "1
1001000 ".

Assuming that the power supply voltage Vcc changes by 2% to Vcc ', the reference voltage Vref' is calculated from the equation (6) as follows: Vref '= (1 ± 0.02) × 3 [V] The difference voltage Vδ ′ is Vδ ′ = (1 ± 0.02) × 0.00781 [V] from the equation (7). For simplification of description, for example, when the power supply voltage fluctuates to the positive side by 2%, Vref ′ = 3.06 [V] Vδ ′ = 0.00797 [V]. Since the voltage difference from the reference voltage changes in this way, the threshold voltage V200 before the power supply voltage changes does not correspond to the input signal voltage Vin. Therefore, the threshold voltage corresponding to Vin is V
Assuming that (n), V (n) <Vin ≦ V (n + 1) (9). In the above formula, V (n) = Vref ′ + Vδ ′ × n = 3.06 + 0.00797 × n [V] V (n + 1) = Vref ′ + Vδ ′ × (n + 1) = 3.06 + 0.00797 × (n + 1) [V ].

In this case, since the value of Vin has a range as shown in equation (8), if the median value is Vin = 4.5659 [V], then 3.06 + 0. 0079 × n <4.5659 ≦ 3.06 + 0.00797 × (n + 1) (10). From 3.06 + 0.00797 × n <4.5659 in formula (10), n <188.9. Further, from the formula (10), 4.5659 ≦ 3.06 + 0.00797 × (n + 1), n ≧ 187.9. Therefore, n = 188 is obtained as the value of n satisfying 187.9 ≦ n <188.9. That is, when the power supply voltage 5 [V] changes by, for example, + 2%, the threshold voltage corresponding to the input signal voltage 4.5659 [V] changes from V200 to V188. Therefore, the voltage of the input signal Vin is converted into binary data “10111100” corresponding to the threshold voltage of V188.

As described above, when the power supply voltage fluctuates, the input signals of the same level are converted into binary data of different values, which is not preferable because it causes a measurement error for the measuring instrument. The present invention has been made in consideration of the above circumstances, and an object thereof is to realize a high-speed A that prevents digital conversion data of an input signal from being affected even if the power supply voltage fluctuates.
The object is to provide an A / D converter.

[0017]

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1, which illustrates an embodiment of the invention, amplifiers 2, 3, 4, and A
The / D converter 5, the display unit 13 and the like are composed of substantially the same units as the previous conventional device, and are therefore provided with the same reference numerals. In this embodiment, in order to solve the above problems, the following means are further provided. That is, for example, the Zener diode ZD that operates at the power supply voltage + Vcc and its current limiting resistor Ra, and the voltage dividing resistor R that divides a part of the voltage drop of the Zener diode ZD and extracts it.
b, Rc, and the serial voltage of the extracted divided voltage and the voltage drop generated in the current limiting resistor Ra, the amplifier 16
In addition to the above, a reference voltage forming circuit 15 for forming the reference voltage Vref and applying it to the low potential side terminal 11 of the ladder resistor 6 is provided.

For example, the voltage Vm at the central potential terminal 14 of the ladder resistor 6 is applied to the amplifier 18, and the same amplifier 18 and the next-stage amplifier 19 form a bias voltage −Vb for zero line shift of the input signal Vin to input the amplifier 2.
Bias voltage forming circuit 17 applied to the output side of.

[0019]

In the reference voltage forming circuit 15 of the means for solving the above problems, the voltage drop across the Zener diode ZD hardly changes even if the power supply voltage Vcc changes and can be regarded as constant. Therefore, when the power supply voltage fluctuates by ± ΔV, the voltage drop of the current limiting resistor Ra changes by ± ΔV. Therefore, the voltage drop of the current limiting resistor Ra,
A part of the voltage drop across the Zener diode ZD is divided in series by a voltage divided by a resistor Rb to form a reference voltage Vref, and a low-potential-side terminal of the ladder resistor 6 via an amplifier 16. When the voltage is applied to No. 11, even if the power supply voltage Vcc applied to the high potential side terminal 10 changes by ± ΔV, the voltage between both terminals 10-11 does not change and is maintained at a predetermined constant voltage. As a result, the threshold voltage V1, V2, ...
δ does not change, so the threshold voltage seen from terminal 11 does not change.

Next, in the bias voltage forming means 17 of the above problem solving means, for example, the potential voltage + Vm is taken in from the central potential terminal 14 of the ladder resistor 6, and the bias voltage −Vb for zero line shift is inputted by the amplifiers 18 and 19. Is formed and added to the output side of the amplifier 2. As a result, the absolute value Vb of the bias voltage −Vb becomes equal to the power supply voltage Vc.
Even if c changes, it becomes equal to the level of the central potential voltage Vm of the ladder resistor 6, and the zero line of the input signal Vin is A / D.
It is always held at the center voltage level of the allowable input voltage range of converter 5.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION In FIG. 1 described above, a portion having the same structure as the conventional apparatus will be briefly described. When the converted analog AC signal Vin is applied to the amplifier 2 via the input terminal 1 of the device, the amplifier 2 selects an appropriate range in accordance with the signal level, inverts and amplifies the input signal Vin to amplify the amplifier 3.
Add to. In this embodiment, in order to shift the zero line of the inverted output signal Vin of the amplifier 2 to the negative side, for example, the bias voltage -Vb is applied from the bias voltage forming circuit 17 to the output side of the amplifier 2. ..
The amplifier 3 inverts and amplifies the output Vin of the amplifier 2 whose zero line is shifted to the negative side -Vb with a gain of 1, for example. As a result, the output Vin of the amplifier 3 becomes a signal having + Vb on the positive side as the zero line. The amplifier 4 non-inverts the output of the amplifier 3 with a gain of 1, for example, and the A / D converter 5
Signal input terminal 9 of.

In the A / D converter 5, the signal Vin applied to the signal input terminal 9 is applied in parallel to the comparator groups A1 to A255 of the comparator 7, and the threshold value given from the ladder resistor 6 to each of the above comparators. The voltages are compared with the voltages V1, ..., V255, respectively. In this embodiment, the power source voltage + V of the device is applied to, for example, one high potential side terminal 10 of the ladder resistor 6.
cc is applied, and the reference voltage + Vref is applied from the reference voltage forming circuit 15 to the other low potential side terminal 11.

The reference voltage forming circuit 15 includes, for example, the Zener diode ZD and its current limiting resistor Ra, and the resistors Rb and Rc for dividing the voltage drop across the Zener diode ZD, as described in the means for solving the problems. Same resistance R
An amplifier 16 that forms a reference voltage Vref by adding the voltage drop of the current limiting resistor Ra in series to the voltage divided by b.

Here, in FIG. 2A, which is an excerpt of the reference voltage forming circuit 15 of FIG.
When the voltage drops of the Zener diode ZD and the current limiting resistor Ra when Vcc is added are Vz and Va, respectively, Vcc = Vz + Va (11) In the formula (11), the voltage drop Vz of the Zener diode ZD is the power supply voltage Vz as described in the section for explaining the operation.
It is a constant voltage that is not affected by fluctuations in cc, and the voltage drop Va of the resistor Ra is a voltage that changes according to fluctuations in the power supply voltage Vcc.

Now, the voltage drop Vz of the Zener diode ZD is divided by, for example, the resistors Rb and Rc, the resistor Rb is further adjusted, and the desired reference voltage Vref is obtained by the divided voltage Vba and the voltage drop Va of the resistor Ra. Then, Vref = Vba + Va (12) Substituting equation (11) into Va in equation (12) gives Vref = Vba + Vcc-Vz (13). In the formula (13), for example, when the reference voltage when the power supply voltage Vcc fluctuates ± ΔV is Vref ′, Vref ′ = Vba + VCC ± ΔV−Vz From the above formula and the formula (13), Vref ′ = Vref ± ΔV ... (14) is obtained. That is, when the power supply voltage Vcc fluctuates ± ΔV, the reference voltage Vref fluctuates at the same voltage.

Therefore, when this reference voltage Vref is applied to the low potential side terminal 11 of the ladder resistor 6 via the non-inverting amplifier 16 having a gain of 1, for example, the power source applied to the high potential side terminal 10 of the ladder resistor 6 is applied. When the voltage Vcc changes by + ΔV, the reference voltage Vref also changes by + ΔV, and when the Vcc changes by -ΔV, Vref also changes by -ΔV. That is, no matter how the power supply voltage Vcc changes, the voltage Vcc-Vref between both terminals of the ladder resistor 6 is kept constant. This state is shown in FIG. Therefore, each threshold voltage V1 to V formed in the ladder resistor 6 is
255 is not affected by the fluctuation of the power supply voltage.

As described in the means for solving the above problems, the bias voltage forming circuit 17 inverts the output of the amplifier 18 with a gain of 1 and the amplifier 18 which non-inverts the center potential voltage Vm of the ladder resistor 6 with a gain of 1, for example. It is composed of an amplifier 19. Here, the central potential voltage V of the ladder resistor 6
The magnitude of m is Vm = (Vcc-Vref) / 2 (15). The input voltage of the amplifier 18 is Vm + Vref = (Vcc-Vref) / 2 + Vref because the amplifier 18 receives the voltage Vm with respect to the ground. Since the bias voltage -Vb output by the amplifier 19 is the inversion voltage of the above equation, -Vb =-(Vm + Vref) and the polarity becomes negative. However, the output side of the inverting amplifier 3 is further inverted to have a positive polarity. That is, Vb = Vm + Vref (16) Here, for example, if the power supply voltage Vcc fluctuates by ± ΔV, the reference voltage Vref also fluctuates by ± ΔV as described above, so Vcc → Vcc ± ΔV Vref → Vref ± Letting Vm ′ be the central potential voltage when ΔV is set and Vb ′ be the bias voltage, Vm ′ = {(Vcc ± ΔV) − (Vref ± ΔV)} / 2 = (Vcc−Vref) / 2 Become. From the above equation and equation (15), it can be seen that Vm ′ = Vm and the central potential voltage Vm does not change.

Regarding the bias voltage Vb ′, Vb ′ = Vm ′ + (Vref ± ΔV) = Vm + (Vref ± ΔV) From the above equation and the equation (16), Vb ′ = Vb ± ΔV, and the bias voltage Vb ´ (zero line level) is △
It can be seen that it varies by V. These states are also shown in FIG. 2 (B). Since the signal waveforms i to i of the respective parts of FIG. 4 in the conventional device can be obtained in the embodiment of the present invention, corresponding parts are designated by the same reference numerals.

[0029]

As described in detail above, in the present invention, for example, the Zener diode ZD that operates at the power supply voltage Vcc of the device and the current limiting resistor Ra are included, and the voltage drop Va of the current limiting resistor Ra and the Zener are the same. Diode ZD
The voltage Vba obtained by dividing the voltage drop of 1 is serially added to form a predetermined reference voltage Vref, and one low potential side terminal 11 of the ladder resistor 6 is driven by the reference voltage Vref via the amplifier 16. The reference voltage forming circuit 15 is provided.

Further, for example, the terminal 1 of the ladder resistor 6 described above.
The bias voltage forming circuit 17 is provided with amplifiers 18 and 19 for taking in and amplifying the central potential voltage Vm of the ladder resistor 6 from 4 and shifting the zero line of the converted analog AC signal Vin to a predetermined voltage level. ..

Therefore, according to the present invention, the threshold voltage for level comparison given from the ladder resistor 6 to the comparator 7 is changed by the power supply voltage Vcc applied to the other high potential side terminal 10 of the ladder resistor 6. However, it does not change under the influence of it. In addition, the AC input signal Vin
Is held at the center potential voltage of the ladder resistor 6, that is, the center voltage level of the allowable input voltage range of the A / D converter 5, and even if the power supply voltage Vcc fluctuates, it is not affected by it. There is no.

Therefore, for example, if the waveform of an image signal is recorded on a recording paper and its level is measured, accurate measurement data can be obtained, and a high-speed and high-accuracy A / D suitable for electronic measuring instruments can be obtained.
A conversion device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an A / D conversion device according to the present invention.

FIG. 2 is an operation explanatory view of the problem solving means applied to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional device.

FIG. 4 is a signal diagram for explaining the operation of the conventional device.

FIG. 5 is a ladder resistance configuration diagram for explaining a problem in a conventional device.

[Explanation of symbols]

 5 A / D converter 6 Ladder resistance 7 Comparator 15 Reference voltage forming circuit 16 Amplifier 17 Bias voltage forming circuit 18 Amplifier 19 Amplifier A1-A255 Amplifier group R1-R256 Ladder resistance Ra Zener current setting resistance Rb Voltage dividing resistance Rc Voltage dividing resistance V1-V255 Threshold voltage Va Zener current setting resistor voltage drop Vb Bias voltage Vba Divided voltage Vcc Power supply voltage Vin AC input signal Vm Ladder resistor central potential voltage Vref Reference voltage Vz Zener diode voltage drop

Claims (1)

[Claims] 1. A ladder resistor (6) for generating various threshold voltages in a resistor group provided between a power supply voltage (Vcc) of a device and a predetermined reference voltage (Vref), and the ladder resistor. An amplifier group that compares the threshold voltage with the threshold voltage generated by the resistor (6) as one input and the AC analog input signal (Vin) as the other input in common, and compares the levels with the threshold voltage. A parallel comparison type A / D converter (5) including a comparator (7) provided therein is provided, and a positive or negative constant DC voltage (V) is applied to the input signal (Vin).
b) is added to shift the zero line of the same signal within the allowable analog input voltage range of the A / D converter (5), and the shifted input signal is digitally converted by the same A / D converter. In, a Zener diode (ZD) and a Zener current setting resistor (Ra) that are provided in series between the power supply voltage (Vcc) and ground and operate, and a voltage drop (Vz) across the Zener diode (ZD). Resistance to divide the voltage (Rb, Rc)
And the divided voltage (Vba) by the resistor and the voltage drop (Va) across the Zener current setting resistor (Ra).
A reference voltage forming circuit 15 which has an amplifier (16) whose input is a series voltage of and a reference voltage (Vref) for applying the output of the amplifier to the ladder resistor (6), and the ladder resistor (6) An amplifier (18, 1) that takes in and amplifies the voltage (Vm) at the central potential terminal (14) of the
9), the positive or negative DC output of the amplifier is added as a bias voltage to the input signal (Vin), and the zero line level of the input signal is added to the A / D converter (5).
And a bias voltage forming circuit (17) that shifts to a voltage substantially equal to the center potential voltage of the allowable analog input voltage range in (1).