JP3303839B2 - High precision D / A converter and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-precision D / A conversion circuit and a control method thereof, and more particularly to a high-precision D / A conversion capable of correcting an offset voltage of an operational amplifier constituting an output buffer circuit with high accuracy. The present invention relates to a circuit and a control method thereof.

[0002]

2. Description of the Related Art FIG. 7 shows a resistor string type resolution 8.
FIG. 3 is a block diagram showing a configuration of a conventional D / A conversion circuit for bits. As shown in the drawing, in the 8-bit reference voltage generation block 101, 2 ⁸ is provided between the lower reference potential source ref1 and the higher reference potential source ref2.
(= 256) resistors R1, R2,..., R256 are connected in series. The output voltages V (0) and V (0) are respectively applied to the lower reference potential point and the connection point of each resistor.
(1), V (2),..., V (254), V (255) are provided. D /
The A output buffer block 102 includes an operational amplifier 102c having a non-inverting input terminal (+) connected to the input terminal 102a, an output terminal connected to the analog signal output terminal 102b, and an output terminal connected to the inverted input terminal (-). ing.

The switch circuit 103 selects an output terminal in the reference voltage generation block 101 according to the digital code data, and selects a D / A output buffer block 1
02 input terminal 102a.

In such a D / A conversion circuit, since an offset exists in the output buffer block 102, a conversion error occurs. FIG. 8 is an equivalent circuit diagram of a measurement circuit for a sample of the operational amplifier in the D / A output buffer block shown in FIG. 9 and 10 show that, in this measurement circuit, 1.5V and -1.5V are used as the power supply voltage (lower reference potential source: ref1 = -1.5V, higher reference potential source: ref2 = 1.5V). ), Input terminal -2.0V ~
Sample 1 when 2.0V input voltage VICM was applied
5 shows output (VOUT) characteristics and measurement results of offset voltage VOS (VOS = VOUT−VICM) for Sample 2.

FIGS. 9A and 1B schematically show input / output characteristics.
0 (a) shows no significant difference between Sample 1 and Sample 2, but shows details of the offset voltage.
10 (b) and FIG. 10 (b), while the offset voltage of Sample 1 is within ± 0.5 mV,
In sample 2, it exceeds ± 2 mV. Since the offset is not corrected in the conventional example shown in FIG. 7, the offset voltage directly causes an error in the D / A output buffer block 102, and the D / A conversion circuit using the latter sample becomes defective. . Thus, this kind of D /
The A-conversion circuit is usually provided as a multi-channel D / A conversion circuit, and if a conversion error is out of specifications even for one channel, the entire semiconductor chip becomes defective.
In the conventional example, it was difficult to manufacture with high yield.

As a solution to this problem, Japanese Patent Application Laid-Open No. 63-67828 proposes to compensate for an offset voltage of an output buffer amplifier. FIG.
1 is a block diagram of a D / A conversion circuit proposed in the publication. In the figure, 201 is a digital information signal input circuit, 202 is a digital correction signal generation circuit comprising a latch and counter circuit 203 and a clock signal generator 204, 205 is a full adder, 206 is an MSB input circuit and an inverter 207a is provided. D / A converter 207 attached
D / A converter 209 including a deglitch and amplifying circuit 208, a comparator 209 for detecting an offset voltage,
Reference numeral 10 denotes a switch.

In the D / A conversion circuit shown in FIG. 11, to correct the offset voltage, the signal input to the input circuit 201 is set to 0, the power is turned on, and the latch and counter circuit 203 is reset. In this state, when the latch and counter circuit 203 starts counting the clock from the clock signal generator 204, the D / A converter 206 outputs an analog component corresponding to the correction signal (count value) of the latch and counter circuit 203. And D / A conversion means 20
The sum with the offset voltage component of No. 6 is output and input to the comparator 209. Latch and counter circuit 203
At the beginning, when a negative signal is input to the comparator 209, the output of the comparator 209 becomes L level. When the switch 210 is turned off and the latch and counter circuit 203 continues counting, the correction signal increases, and the input of the comparator changes from negative to positive. As a result, the output of the comparator 209 becomes H level, and the latch value of the latch and the counter circuit 203 at this time is latched. As a result, a correction signal is obtained, and the D / A conversion is performed by adding the correction signal of the latch and counter circuit 203 to the digital signal input from the input circuit 201.

In the conventional example shown in FIG. 11, the correction signal is obtained when the input digital signal is 0. In general, the offset voltage is as shown in FIGS. 9 (b) and 10 (b). Because of the input voltage dependency, it is difficult to perform appropriate correction on the input signals of all codes using the correction signal obtained under the condition of the input digital signal 0.

In the conventional example shown in FIG. 11, since a correction signal is obtained in bit units, the LSB (least
Even if there was an offset below the analog value corresponding to the significant bit, it could not be corrected.

[0010]

SUMMARY OF THE INVENTION The object of the present invention is to remedy the disadvantages of the prior art which has been described above, and in particular to a new and novel method which can finely and accurately compensate for the offset of the output buffer circuit over all digital code data. A high-precision D / A converter and a control method thereof are provided.

Another object of the present invention is to provide a novel high-precision D / A converter which eliminates the offset of the output buffer circuit even when the offset of the output buffer circuit extends over a wide range of 1 LSB or more, thereby improving the yield, and a control method therefor. Is provided.

[0012]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, a first aspect of the high-precision D / A converter according to the present invention is an output voltage generation block having a plurality of analog voltage output terminals capable of outputting an analog voltage according to digital code data; An amplifier that has two input terminals and generates an analog correction voltage by inputting the output voltage of two selected consecutive analog voltage output terminals of the output voltage generation block to the two input terminals; The output voltage correction block provided with a gain variable means for varying the gain of the amplifier, and either the output voltage of the output voltage generation block or the output voltage of the output voltage correction block is selectively input, A buffer block that buffers and amplifies the input voltage and outputs an analog output signal; A successive approximation block for detecting the presence or absence of an offset in the buffer block by inputting the output voltage of the buffer block and the output voltage of the buffer block; and Selecting an analog voltage output terminal of the output voltage generation block to be input to the correction block, inputting the output voltage to the output voltage correction block, inputting the output of the output voltage correction block to the buffer block, and And switch control means for controlling switching of the gain variable means of the output voltage correction block.
In an aspect, the output voltage correction block includes an operational amplifier,
A first resistor connected to an inverting input terminal of the operational amplifier; and a second resistor connected to a non-inverting input terminal of the operational amplifier.
, A plurality of third resistors having the same resistance connected in series between the inverting input terminal and the output terminal of the operational amplifier, and the switch control configured to short each of the plurality of third resistors. And a plurality of switch means controlled by the means,
In a third aspect, the output voltage correction block includes an operational amplifier, a first resistor connected to an inverting input terminal of the operational amplifier, a second resistor connected to a non-inverting input terminal of the operational amplifier, A plurality of series circuits in which a third resistor connected between the inverting input terminal and the output terminal of the operational amplifier, a fourth resistor and switch means controlled by the switch control means are provided in series, and A circuit is connected in parallel to the first resistor.

A first aspect of the method of controlling a high-precision D / A converter according to the present invention is an output voltage generator having a plurality of analog voltage output terminals capable of outputting analog voltages in accordance with digital code data. And an amplifier that has two input terminals and generates an analog correction voltage by inputting the output voltages of two selected consecutive analog voltage output terminals of the output voltage generation block to the two input terminals. In this amplifier, an output voltage correction block provided with a gain variable means for varying the gain of the amplifier, and either the output voltage of the output voltage generation block or the output voltage of the output voltage correction block are selectively provided. A buffer block for buffering and amplifying the input voltage and outputting an analog output signal; and an output voltage generation block. A successive approximation block for detecting the presence or absence of an offset of the buffer block by inputting the analog output voltage of the buffer block and the output voltage of the buffer block; and Selecting an analog voltage output terminal of the output voltage generation block to be input to the voltage correction block, inputting the output voltage to the output voltage correction block, and inputting the output of the output voltage correction block to the buffer block, And a switch control means for switching and controlling the gain variable means of the output voltage correction block, wherein the analog voltage according to digital code data is input to the buffer block. At least including an offset at the output terminal of the buffer block A first step of obtaining a analog voltage; and an analog voltage including an offset obtained in the first step and an analog voltage not including an offset based on the digital code data. A second step of detecting, and a third step of, when the offset is detected, generating a voltage obtained by changing a predetermined voltage from an analog voltage based on the digital code data. Inputting the voltage generated in the third step to the buffer block until the successive approximation block no longer detects the offset.
And a fourth step of controlling the switch control means to further change the voltage generated by the voltage of the third step. When the successive approximation block stops detecting the offset substantially, The output voltage of the buffer block is an analog voltage obtained by D / A conversion. In a second aspect, the detection of the presence or absence of the offset in the second step is performed by the successive approximation block In the third aspect, the voltage generated in the third step varies the gain of the amplifier of the output voltage correction block. It is characterized by being obtained by

[0015]

FIG. 1 illustrates an embodiment of the present invention.
N (N is a positive integer) bit D / A conversion for clarification
It is a block diagram of a circuit. As shown in FIG.
The output voltage generation block is included in the reference voltage generation block 1.
1a and an output voltage correction block 1b.
The output voltage generation block 1a applies a reference potential difference to a resistance strike.
(2)^N +1) Divide it by 1
The output terminal T (−) is connected to each of the division points and the reference potential points at both ends.
1), T0, T1,..., T (2^N -2), T ((2
^N -1), T (2^N ) Is provided for each output terminal
From V (-1: 0), V (0: 0), V (1:
0),..., V (2^N -2: 0), V (2^N -1:
0), V (2^N : 0) are obtained. Of these, N bits
The analog voltage according to the code data is applied to the output terminals at both ends.
Excluding 2^N Output terminals.

As shown in FIG. 2, the output voltage correction block 1b includes an operational amplifier Amp2, a first resistor Ri2 connected to an inverting input terminal (-) of the operational amplifier, and
A second resistor Ri1 connected to the non-inverting input terminal (+) of the operational amplifier; and a plurality of third resistors Rf1 having the same resistance connected in series between the inverting input terminal (-) and the output terminal of the operational amplifier. Rfγ and a plurality of switch means SWf configured to short each of the plurality of third resistors.
1 to SWfγ, and the output obtained at the output terminal VROUT is input to the D / A output buffer block 2.

The D / A output buffer block 2 having a buffer circuit therein has an input terminal 2a and an analog signal output terminal 2b from which an output signal of the D / A conversion circuit is obtained.

The successive approximation block 3 having two input terminals 3aa and 3ab and one output terminal 3b has a function of comparing signals input to the two input terminals 3aa and 3ab, and the comparison result is as follows. The output signal DV is output from the output terminal 3b.

5a selects one output terminal from the output terminals of the output voltage generation block 1a in accordance with the input digital code data, and outputs D through a switch 6a.
The first switch mechanism 5b connected to the input terminal 2a of the / A output buffer block 2 selects one output terminal from the output terminals of the output voltage generation block 1a according to the input digital code data, and switches the output terminal. The second switch mechanism 5c connected to the input terminal 3aa of the successive approximation block 3 through the output voltage generation block 1
a of two adjacent output terminals selected from the output terminals of the output voltage correction block 1b.
The third switch mechanism 5d connected to the output voltage correction block 1b controls the switch of the output voltage correction block 1b to output the output of the output voltage correction block 1b via the switch 6a.
A fourth switch mechanism 6b, 6c connected to the input terminal 2a of the A output buffer block 2 is a switch that is turned on and off as necessary.

4 controls the third switch mechanism 5c based on the comparison result output from the successive approximation block 3 to change two of the output terminals of the output voltage generation block 1a to the output voltage correction block 1b. , And controls the switch of the output voltage correction block 1b by controlling the fourth switch mechanism 5d, and outputs the output of the output voltage correction block via the switch 6a to the D / A output buffer block 2. Switch control means connected to the input terminal 2a. The switch control means 4 further controls switching of the switch 6a and on / off of the switches 6b and 6c.

Next, the operation of the D / A conversion circuit of the present invention shown in FIG. 1 will be described.

(A) Input of digital code data First, the first switch 6a is set to the first switch mechanism 5a.
And turn on the second and third switches 6b and 6c. When digital code data is input as an input signal in this state, one of the output terminals of the output voltage generation block 1a according to the digital code data is selected by the first and second switch mechanisms 5a and 5b, and the output terminal is selected. The output signal V (α: 0) is transmitted to the input terminals 2a and 3aa (where α = 0, 1, 2,..., 2 ^N −1).

(B) Initial setting The D / A output buffer block 2 amplifies the input signal voltage V (α: 0) in a buffer circuit in the block and outputs an analog signal output terminal as a signal including an offset voltage. 2b, and this output signal is compared with the signal voltage V (α: 0) input from the input terminal 3aa in the successive approximation block 3.

At this time, when the offset VOS in the D / A output buffer block is negative, the output signal DV of the successive approximation block 3 is at a high level, and when the offset VOS is positive, the output DV of the successive approximation block 3 is at a low level. Becomes

(C) -1 Successive comparison (1): [DV
Is high level] The switch control means 4 switches the first switch 6a to the output voltage correction block 1b side (the second and third switches 6b and 6c remain as they are), and controls the third switch mechanism 5c. Of the output voltage of the output voltage generation block 1a.
(Α: 0) is input terminal 1b of output voltage correction block 1b.
a, and V (α-1: 0) to the input terminal 1bb. Next, the switch control means 4 controls the fourth switch mechanism 5d to control the switches SWf1, SWf2,..., SWfγ of the output voltage correction block 1b connected to the input terminal 2a of the D / A output buffer block 2. OFF sequentially
The voltage input to the input terminal 2a of the D / A output buffer block 2 is gradually changed. In the process, when the signal input to the input terminal 2a just exceeds the offset of the D / A output buffer block 2, the successive approximation block 3
Changes from the high level to the low level. When detecting that the DV is inverted, the switch control means 4 stops the switch control operation by the fourth switch means 5d, fixes the input voltage input to the input terminal 2a, and completes a series of correction operations. That is, the output signal output from the analog signal output terminal 2b immediately after the DV is inverted is determined as the correction output signal related to the input digital code data. Next, if necessary, the first to third switches 6a to 6c are all turned off to prepare for the input of the next digital code.

(C) -2 Successive comparison (part 2): [DV
Is low level]. The switch control means 4 switches the first switch 6a to the output voltage correction block 1b side (the second and third switches 6b and 6c remain as they are), and controls the third switch mechanism 5c. Of the output voltage of the output voltage generation block 1a.
(Α: 0) is input to the input terminal 1ba, and V (α + 1:
0) is input to the input terminal 1bb of the output voltage correction block 1b. Next, the switch control means 4 controls the fourth switch mechanism 5d to control the switches SWf1, SWf2,..., SWfγ of the output voltage correction block 1b connected to the input terminal 2a of the D / A output buffer block 2. Sequential OF
F, the voltage input to the input terminal 2a of the D / A output buffer block 2 is gradually changed. In the process, when the signal inputted to the input terminal 2a just exceeds the offset of the D / A output buffer block 2, the output voltage DV of the successive approximation block 3 changes from a low level to a high level. When detecting that the DV has been inverted, the switch control means 4 stops the switch control operation by the fourth switch means 5d, fixes the input voltage input to the input terminal 2a, and completes a series of correction operations. That is, the output signal output from the analog signal output terminal 2b immediately after the DV is inverted is selected as the correction output signal for the input digital code data. Next, if necessary, all the first to third switches 6a to 6c are turned off,
Prepare for input of next digital code data.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a high-precision D / A converter according to the present invention.

(First Specific Example) FIGS. 1 and 2 show a first specific example of a high-precision D / A converter and a control method thereof according to the present invention. An output voltage generating block 11a having a plurality of analog voltage output terminals capable of outputting analog voltages in accordance with digital code data, and two input terminals VI1 and VI2. An amplifier Amp2 that generates an analog correction voltage by inputting the output voltages of two selected analog voltage output terminals of the output voltage generation block 11a, the amplifier A
An output voltage correction block 1 provided with gain variable means SWf1 to SWfγ for varying the gain of the amplifier
1b, and either the output voltage of the output voltage generation block 11a or the output voltage of the output voltage correction block 11b is selectively input, and a buffer that buffers and amplifies the input voltage to output an analog output signal Block 1
2, a successive approximation block 13 for detecting the presence or absence of an offset in the buffer block 12 by inputting the analog output voltage of the output voltage generation block 11a and the output voltage of the buffer block 12, and the successive approximation block 13 The analog voltage output terminal of the output voltage generation block 11a to be input to the output voltage correction block 11b is selected with reference to the presence or absence of the offset output from the output voltage correction block 11b, and this output voltage is input to the output voltage correction block 11b. , This output voltage correction block 11b
Of the output voltage correction block 11b.
Switch control means 4 for switching control of Wf1 to SWfγ
And a high-precision D / A converter composed of the following. Further, the output voltage correction block 11b includes an operational amplifier Amp2
A first resistor Ri2 connected to the inverting input terminal (-) of the operational amplifier; a second resistor Ri1 connected to the non-inverting input terminal (+) of the operational amplifier; and the inverting input terminal (-). And a plurality of third resistors Rf1 to Rf1 connected in series between the output terminal VROUT of the operational amplifier and having the same resistance value.
Rfγ and the switch control means 4 for short-circuiting the plurality of third resistors Rf1 to Rfγ.
A high-precision D / A converter characterized by being constituted by a plurality of switch means SWf1 to SWfγ controlled by.

Hereinafter, the first specific example will be described in more detail.

The switch mechanism and its control means disposed between the blocks are technical means well known to those skilled in the art, and therefore, their illustration and detailed description thereof will be omitted in the following description.

FIG. 2 is a block diagram of a resistor string type D / A conversion circuit. As shown in the figure, the reference voltage generation block 11 includes an output voltage generation block 11a that generates an 8-bit code voltage, and an output voltage correction block 11b. The output voltage generation block 11a stores a reference potential difference between the lower reference potential source ref1 and the higher reference potential source ref2 by two.
It is divided by a factor of 257 by a series resistor connection composed of 57 (= 2 ⁸ +1) resistors, and the voltages V (−1: 0) and V are output from the respective division points and the output terminals of the reference potential points at both ends.
(0: 0), V (1: 0),..., V (α: 0), V (α
+1: 0),..., V (255: 0), V (256: 0)
Is obtained. However, an analog voltage according to 8-bit code data is obtained from 2 ⁸ (= 256) output terminals excluding output terminals at both ends of these voltages.

The output voltage correction block 11b has an operational amplifier Amp2, a non-inverting input terminal (+ side) of the operational amplifier Amp2 is connected to an input terminal VI1 via a resistor Ri1, and an inverting input terminal (-) is connected to an inverting input terminal (-). It is connected to the input terminal VI2 via the resistor Ri2.

Further, the output voltage correction block 11 b
, Rfγ are connected in series, and switches SWf1, SWf2,..., SWfγ that can be switched to short-circuit connection are connected in parallel to the respective resistors.

One end of the series-connected resistor group is connected to the inverting input terminal (-) of the operational amplifier Amp2, and the other end is connected to the output terminal VROUT of the operational amplifier Amp2.

The input terminals VI1 and VI2 of the output voltage correction block 11b are respectively switched to switch the output terminals V (α: 0) and V (α-1: 0) (V-1) of the 8-bit code output voltage generation block 11a. Or V (α +
1: 0)).

Therefore, the output voltage correction block 11b
By switching the internal switches SWf1, SWf2,..., SWfγ, (γ + 1) kinds of inverted amplified voltages V (α: 0), V (α: 1),.
γ).

These output correction voltages are supplied to the D / A output buffer block 12 during the successive approximation of the successive approximation block 13.
Is supplied as an input bias.

The D / A output buffer block 12 has an operational amplifier 12c and is an analog output block based on a voltage follower system.

The D / A output buffer block 12 is provided with an operational amplifier 12c having an input terminal 12a connected to a non-inverting input terminal (+) and an output terminal provided with an analog signal output terminal 12b. The terminal is connected to the inverting input terminal (-) and negative feedback is applied. The input terminal 12a is connected to the output voltage generation block 11 in the initial setting in accordance with the input digital code data.
a 8-bit code output voltage V (0: 0), V (1:
, V (254: 0), V (255: 0), and then the output voltage of the output voltage correction block 11b is sequentially applied in the successive approximation stage.

In the successive approximation block 13, the non-inverting input terminal (+) is connected to the constant potential source V1, and the inverting input terminal (-) is connected to one end of the capacitor C and the constant potential source V1 via the switch SW2. A comparator 13c having an output terminal of the operational amplifier 13c connected to the output terminal 13b is provided. The voltage of the constant potential source V1 is selected to be a value sufficient for the comparator 13c to operate normally over the entire input voltage range. The comparator 13c has an offset canceller, and an offset canceller having an offset of 0 or extremely small is used. The other end of the capacitor C is connected to the changeover switch SW1, and the input terminal 13 is connected through the changeover switch SW1.
a or the analog signal output terminal 12b of the D / A output buffer block 12. Changeover switch SW
1 is input to the input terminal 13a at the time of the initial setting, and is then switched to the output terminal 12b of the D / A output buffer block 12 in the successive approximation stage.

Next, the operation of the first specific example shown in FIG. 2 will be described. First, the operation at the time of initial setting when inputting a digital code will be described. Turn on the changeover switch SW1 to the input terminal 13a side,
Turn on the switch SW2. During this time, the offset adjustment of the comparator 13c in the successive approximation block 13 is completed. By inputting a digital code, the input terminals 12a, 1
The corresponding code output voltage V (α: 0) is input to the output voltage generating block 11a (where α = 0 to 2).
55). As a result, the capacitor C is charged up to the capacitor voltage VC of V1−V (α: 0) with the voltage of the constant potential source V1 as V1. This is the initial setting stage.

At this time, a voltage obtained by adding the offset voltage VOS of the D / A output buffer block to the code output voltage V (α: 0) is output to the analog signal output terminal 12b as the analog output voltage AOUT. That is, AOUT = V (α: 0) + VOS The following successive approximation fine adjustment operation is performed to remove VOS which is the error voltage here. The switch SW2 is turned off, and the changeover switch SW1
To the output terminal 12b side.

When the switch SW2 is turned off, there is no change in the potential at both terminals of the capacitor C. Here, when the changeover switch SW1 is switched to the output terminal 12b side, a voltage obtained by subtracting the voltage [V (α: 0)] input from the AOUT to the input terminal 13a is transmitted to the electrode of the capacitor on the comparator side. . Therefore, the voltage input to the inverting input terminal of the comparator is as follows: V1 + AOUT−V (α: 0) = V1 + V (α: 0) + VOS−V (α: 0) = V1 + VOS Therefore, in the comparator 13c, D / A
The sign of the offset VOS of the output buffer block 12 is determined. As the output signal DV of the comparator, when VOS is negative, DV is at a high level, and when VOS is positive, DV is at a low level. Hereinafter, the successive approximation operation for the above two cases will be described. -1 When the output DV of the comparator 13c is at the high level, both input terminals VI of the output voltage correction block 11b
V (α: 0) and V (α-1: 0) for VI1 and VI2, respectively.
Enter -1 Switches SWf1, SWf2,..., SW until the output DV of the comparator 13c is inverted to a low level.
fγ is sequentially turned off, and the voltage applied to the input terminal DIN of the D / A output buffer block 12 is V (α:
0) → V (α: 1) →... → V (α: n) (n is OF
F, the total number of SWf1 to SWfγ, V (α: 0) <V
(Α: 1) <... <V (α: n)).
(F) -2 When the output DV of the comparator 13c is at a low level, both input terminals VI of the output voltage correction block 11b
V (α: 0) and V (α + 1: 0) for VI1 and VI2, respectively.
Enter -2 Switches SWf1, SWf2,..., S until output DV of comparator 13c is inverted to High level.
Wfγ is sequentially turned off, and the voltage applied to the input terminal DIN of the D / A output buffer block 12 is V
(Α: 0) → V (α: 1) →... → V (α: n) (n
Is the total number of SWf1 to SWfγ turned off, V (α:
0)> V (α: 1)>...> V (α: n)). (F) Input DI of output buffer block at the end of switching
The voltage applied to N is held as an optimized 8-bit reference voltage until the next digital input operation. Also, for stable supply of external analog output voltage AOUT, SW
1 is switched to the 13a side.

As described above, the output buffer block 1
Digital / analog conversion without error factors due to the offset voltage of 2.

Next, an 8-bit D / A converter will be described with reference to specific numerical examples.

Considering an 8-bit code output by a 3V reference power supply, in the 8-bit code output voltage generating block 11, the minimum bit change amount: 1 LSB is (1 LSB) = 3.0 (V) ÷ (2 ⁸ +1) ≒ 11 .6
7 (mV).

The lowest code output voltage V (0: 0) of the 8-bit code output voltage is 11.67 (mV), and the highest code output voltage V (255: 0) is 2988.33.
(MV).

Further, in the output voltage correction block 11b, Ri2 = 100 kΩ, Rf1 = Rf2 =... = Rfγ
Assuming that ≡Rf = 5 kΩ and γ = 100, VROUT = −n × Rf ÷ Ri2 × (VI2−VI1) + VI1 = −0.05n × (-1LSB) + V (α: 0) (when VI2 = V (α-1: 0)) or -0.05n × (+ 1LSB) + V (α: 0) (when VI2 = V (α + 1: 0) ) = ± n × (0.05 LSB) + V (α: 0) Therefore, the minimum change of the output voltage correction value is 0.05 × 11.67 (mV) ≒ 0.58 (mV).

As described above, the external analog output voltage AOUT of the D / A converter of the above specific example is calculated based on the code output voltage V (α: 0) corresponding to an arbitrary digital code input by V (α: 0) −0.58 (mV) ≦ AOUT ≦ V (α: 0) +0.58
(MV) with the accuracy (α = 0 to 255).

Further, for any number where n is 0 to 100, V (α: 0) −58.35 (mV) ≦ VROUT ≦ V (α: 0) +
The offset voltage VOS is 58.35 m to take the range of 58.35 (mV).
It is possible to correct up to the magnitude of V.

On the other hand, in the conventional example shown in FIG.
(Α: 0) plus VOS as is AOUT
Is output as For this reason, the sample whose characteristics are shown in FIG. 9B and whose VOS is 0 to 0.5 (mV) is handled as a non-defective product, but whose characteristics are shown in FIG.
Samples with VOS = 0 to 2.0 (mV) were considered defective.

Similarly, in a good sample as shown in FIG. 5, no deterioration in digital / analog conversion characteristics is observed due to the offset voltage VOS = 0 to 2.0 (mV).

However, in the sample as shown in FIG. 6, that is, in the case where the offset voltage VOS> 11.67 (mV), the prior art could not correct and could not obtain an accurate conversion characteristic. According to the present invention, as described above, the characteristic variation of the D / A output buffer block in the manufacturing process is wide (VOS is 1 LSB in the specific example described above).
Even when the above condition is satisfied, high-accuracy D / A conversion becomes possible, so that an improvement in yield is expected.

(Second Specific Example) FIG. 3 is a diagram showing a high-precision D / A converter according to a second specific example of the present invention.
FIG. 3 shows an operational amplifier Amp2 and a first resistor Ri2 connected to an inverting input terminal (-) of the operational amplifier.
(1), a second resistor Ri1 connected to the non-inverting input terminal (+) of the operational amplifier, and the inverting input terminal (−).
, A third resistor Rf connected between the output terminal VROUT of the operational amplifier, a fourth resistor Ri2 (n), and switch means SWi2 (n) controlled by the switch control means 4.
Are provided in series, and a high-precision D / A converter is provided in which a plurality of (γ-1) series circuits are provided and the series circuits are connected in parallel to the first resistor Ri2 (1).

Hereinafter, the second specific example will be further described.

In this specific example, the inverting input resistance element Ri2
(1), Ri2 (2),..., Ri2 (γ)
The variable gain is realized by switching Wi2 (2), SWi2 (3),..., SWi2 (γ).

Then, digital / analog conversion is executed by the same procedure as the operation flow of the first specific example.

However, in the first specific example, the switch SWf
1, SWf2,..., SWfγ are sequentially turned OFF from the ON state
In the example of FIG. 3, the switches SWi2 (2), SWi2 (3),..., SWi2 (γ) are switched.
Are sequentially switched from the OFF state to the ON state.

Further, in this example, it is meaningless to make the inverting input resistance value 0 Ω, so that only Ri2 (1) is always in the connected state. Therefore, the output voltage correction value is γ.

(Third Specific Example) FIG. 4 is a block diagram for explaining a third specific example of the present invention. The third specific example differs from the first specific example shown in FIG. 2 only in the configuration of the successive approximation block 13, and there is no difference in other parts.
As shown in FIG. 4A, in the successive approximation block 13 of the third specific example, an inverter 13d functioning as an inverting amplifier is used instead of the comparator. Here, an inverter having a sufficiently high amplification factor is used as the inverter 13d. The operations of the changeover switches SW1 and SW2 are the same as in the first specific example, and the circuit operation is the same as in the first specific example. That is, when the changeover switch SW1 is turned on to the input terminal 13a side and the switch SW2 is turned on, the capacitor C sets the input voltage DINO = V (α: 0) input to the input terminal 13a. Is charged. Switch S
When W2 is turned off and the changeover switch SW1 is turned on to the D / A output buffer block 12, the electrode of the capacitor C on the inverter side (input terminal of the inverter) is
AOUT-V (α: 0) voltage is applied, and the output terminal 13b
, As an output signal DV, a low level when AOUT> V (α: 0), and a high level when AOUT <V (α: 0).
A high-level signal is output.

According to the third embodiment, the comparator 1 in the successive approximation block is different from the first embodiment.
Since a power supply of the bias voltage V1 for normal operation of the 3d is not required, there is an advantage that the circuit configuration can be simplified and the number of external input terminals can be reduced.

FIG. 4B is a block diagram for explaining a modification of the third specific example. The difference from FIG. 4A is that the inverter 13d in the successive approximation
The point is that it is connected in multiple stages from three stages. FIG.
In FIG. 4A, since there is only one inverter, if the amplification degree is not sufficient, there is a possibility that the successive approximation detection for the change in the fine adjustment output voltage may not be performed.
This inconvenience is avoided by connecting the inverters in multiple stages.

Note that the number of connected inverters can be any number including even-numbered inverters. However, when the inverters are connected to the even-numbered stages, High and Low of the output signal DV of the successive approximation block are opposite to those described above.

As described above, according to the method of controlling the high-precision D / A converter of the present invention, the analog voltage according to the digital code data is input to the buffer block, and the analog voltage including the offset is output to the output terminal of the buffer block. From the analog voltage including the offset obtained in the first step and the analog voltage not including the offset based on the digital code data,
A second step in which the successive approximation block detects the presence or absence of the offset; and when the offset is detected, the output voltage correction block changes the analog voltage based on the digital code data by a predetermined voltage. A third step of generating the output voltage, and inputting the voltage generated in the third step to the buffer block, and the switch control unit performs the following steps until the successive approximation block does not substantially detect the offset: And a fourth step of controlling the voltage generated by the voltage of the third step so as to further change. When the successive approximation block no longer detects the offset, the output voltage of the buffer block is reduced. It is configured to be a D / A converted analog voltage.

[0065]

As described above, the high-precision D / A converter and the control method thereof according to the present invention can finely and accurately compensate for the offset of the output buffer circuit over all digital code data. Moreover, even if the offset of the output buffer circuit extends over a wide range of 1 LSB or more, the offset can be eliminated, so that the yield can be drastically improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a high precision D / A converter according to the present invention.

FIG. 2 is a block diagram illustrating a first specific example of a high-precision D / A converter according to the present invention.

FIG. 3 is a circuit diagram of a second specific example of the present invention.

FIG. 4 is a circuit diagram of a third specific example of the present invention.

FIG. 5 is a graph showing an example of a sample having a small offset of an operational amplifier.

FIG. 6 is a graph showing an example of a sample having a large offset of an operational amplifier.

FIG. 7 is a block diagram of a conventional D / A converter.

FIG. 8 is an equivalent circuit diagram of a measuring circuit for measuring the offset of the operational amplifier.

FIG. 9 is a graph showing an example of the measurement result of the offset of the operational amplifier, and is a graph showing a state where the offset is small.

FIG. 10 is a graph showing an example of the measurement result of the offset of the operational amplifier, and is a graph showing a state where the offset is large.

FIG. 11 is a block diagram of another conventional D / A converter.

[Explanation of symbols]

 1, 11 Reference voltage generation block 11a Output voltage generation block 11b Output voltage correction block 2, 12 Buffer block 3, 13 Successive approximation block 4 Switch control means SWf1 to SWfγ switch

Claims (6)

(57) [Claims] An output voltage generation block having a plurality of analog voltage output terminals capable of outputting an analog voltage in accordance with digital code data, and two input terminals, wherein the two input terminals generate the output voltage. An amplifier for generating an analog correction voltage by inputting the output voltage of two selected analog voltage output terminals of the block in succession, the amplifier being provided with a variable gain means for varying the gain of the amplifier. An output voltage correction block, and either the output voltage of the output voltage generation block or the output voltage of the output voltage correction block is selectively input, buffers and amplifies the input voltage to output an analog output signal A buffer block; an analog output voltage of the output voltage generation block; and an output voltage of the buffer block. A successive approximation block that detects the presence or absence of an offset of the buffer block by being input, and the presence or absence of an offset that the successive approximation block outputs, with reference to the output voltage generation block that is input to the output voltage correction block. Select the analog voltage output terminal,
Switch control means for inputting the output voltage to the output voltage correction block, inputting the output of the output voltage correction block to the buffer block, and switching and controlling the variable gain means of the output voltage correction block. A high-precision D / A converter characterized by comprising. 2. The output voltage correction block includes an operational amplifier and a first input terminal connected to an inverting input terminal of the operational amplifier.
A second resistor connected to the non-inverting input terminal of the operational amplifier; a plurality of third resistors having the same resistance connected in series between the inverting input terminal and the output terminal of the operational amplifier; 2. The high-precision D / A converter according to claim 1, comprising a plurality of switch means controlled by said switch control means, each of which short-circuits a plurality of third resistors. 3. The output voltage correction block includes an operational amplifier and a first input terminal connected to an inverting input terminal of the operational amplifier.
, A second resistor connected to the non-inverting input terminal of the operational amplifier, a third resistor connected between the inverting input terminal and the output terminal of the operational amplifier, a fourth resistor, and the switch control means. 2. A high-precision D / A converter according to claim 1, wherein a plurality of series circuits are connected in series with the switch means controlled by the control circuit, and the series circuits are connected in parallel to the first resistor. . 4. An output voltage generating block having a plurality of analog voltage output terminals capable of outputting an analog voltage in accordance with digital code data, comprising: two input terminals; An amplifier for generating an analog correction voltage by inputting the output voltage of two selected analog voltage output terminals of the block in succession, the amplifier being provided with a variable gain means for varying the gain of the amplifier. An output voltage correction block, and either the output voltage of the output voltage generation block or the output voltage of the output voltage correction block is selectively input, buffers and amplifies the input voltage to output an analog output signal A buffer block; an analog output voltage of the output voltage generation block; and an output voltage of the buffer block. A successive approximation block that detects the presence or absence of an offset of the buffer block by being input, and the presence or absence of an offset that the successive approximation block outputs, with reference to the output voltage generation block that is input to the output voltage correction block. Select the analog voltage output terminal,
Switch control means for inputting the output voltage to the output voltage correction block, inputting the output of the output voltage correction block to the buffer block, and switching and controlling the variable gain means of the output voltage correction block. A method of controlling a high-precision D / A converter, comprising: inputting an analog voltage according to digital code data to the buffer block, and obtaining an analog voltage including an offset at an output terminal of the buffer block. A second step in which the successive approximation block detects the presence or absence of the offset from an analog voltage including an offset obtained in the first step and an analog voltage not including an offset based on the digital code data; When an offset is detected, the output voltage correction block A third step of generating a voltage obtained by changing the analog voltage based on the digital code data by a predetermined voltage; and inputting the voltage generated in the third step to the buffer block. And a fourth step of controlling the switch control means to further change the voltage generated by the voltage of the third step until the offset is substantially not detected. A high-precision digital-to-analog converter wherein the output voltage of the buffer block is a D / A-converted analog voltage when the offset is substantially not detected.
/ A converter control method. 5. The high-precision D / D converter according to claim 4, wherein the presence or absence of the offset in the second step is detected by a change in the sign of the output signal of the successive approximation block.
Control method of A converter. 6. The high precision D according to claim 5, wherein the voltage generated in the third step is obtained by changing a gain of an amplifier of the output voltage correction block.
/ A converter control method.