JP3102820B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to a high-speed A / D converter for converting an analog image signal into a digital signal.

[0002]

2. Description of the Related Art A parallel comparison type A / D converter, which is generally called a flash converter, is used to convert an analog image signal or the like at a high speed into a digital form. Is shown in FIG. As shown by reference numeral 5, the parallel comparison type A / D converter includes, for example, a ladder resistor 6, a comparator 7, and an encoder 8. The ladder resistor 6 is for forming a comparison threshold voltage of the comparator 7. For example, one terminal 10 is supplied with the power supply voltage + Vcc of the device, and the other terminal 11 is connected via a resistor Rs. Connected to the ground side.

Assuming that the A / D converter 5 is, for example, an element for 8 bits, the ladder resistor 6 has 2 @ 8 powers of R1-R256, that is, 256 bits, as shown in FIG.
And a group of resistors.
A current flows to the ground through the ladder resistor 6, the terminal 11, and the resistor Rs. Assuming that a voltage generated in the resistor Rs by this current is a reference voltage Vref, the ladder resistor 6 is connected to the power supply voltage Vref.
The voltage difference between cc and the reference voltage Vref is divided by, for example, 256 resistors R1 to R256 to form 255 threshold voltages V1,..., V255.

In this case, assuming that the resistance connected to the terminal 11 on the low potential side of the ladder resistor 6 is R1 and the resistance connected to the terminal 10 on the power supply voltage Vcc side is R256, the value of each resistance element is, for example, R1 = R2 =... = R256 = R [Ω], but the resistors R1 and R256 at both ends may be R1 = R256 = R / 2 [Ω]. However, in any case, each threshold voltage is sequentially increased from V1 to V255 by a voltage difference corresponding to 1 LSB, that is, (Vcc-Vref) / 255. If the power supply voltage Vcc is constant, the magnitude of the voltage corresponding to 1 LSB is determined by the magnitude of the reference voltage Vref generated in the resistor Rs, so that the value of the resistor Rs is generally adjustable.

The comparator 7 comprises, for example, 255 comparator groups A1 to A255, and a threshold voltage is applied to one input terminal of each comparator from the ladder resistor 6. An analog input signal Vin is commonly applied to the other input terminal of each comparator via the terminal 9 of the A / D converter 5. Here, for example, a comparator A1 to which a threshold voltage V1 is added
Is the lowest comparator, and the comparator A 255 to which the threshold voltage V255 is added is the highest comparator. Each comparator simultaneously compares the input signal with the respective threshold voltage, and 1 (ON) or 0 (OFF) The comparison output of is issued.

The encoder 8 is composed of, for example, a combination of gate elements (not shown).
-The comparison output of 0 or 1 issued from A255 is received in parallel, converted into 8-bit binary signal data, and transmitted from the output terminal 12.

In FIG. 3, when the converted AC analog signal Vin is applied to the input terminal 1 of the device, the signal is applied to the signal input terminal 9 of the A / D converter 5 via the amplifiers 2, 3, and 4. Here, the amplifier 2 is, for example, an inverting amplifier having a range switch (not shown), and switches the range so that the magnitude of the input signal Vin falls within the allowable input voltage range (Vref-Vcc) of the A / D converter 5. Do. It is preferable that the zero line of the inverted output voltage of the amplifier 2 is near the center of the allowable input voltage range, so that, for example, a DC bias voltage -Vb for level shift is applied. The amplifiers 3 and 4 are, for example, an inverting amplifier with a gain of 1 and a non-inverting amplifier with a gain of 1.

Next, an outline of the operation will be described with reference to FIG. When a relatively low-level converted AC voltage signal Vin, for example, as shown in FIG. 4A, is applied to the input terminal 1 of the device, the amplifier 2 switches to an appropriate range and inverts and amplifies. A bias voltage -Vb for zero line shift is applied to the output, and the output becomes as shown in FIG. The amplifier 3 inverts and amplifies this voltage signal with a gain of 1 as shown in FIG. 3C, and the amplifier 4 non-inverts and amplifies the output of the amplifier 3 with a gain of 1 as shown in FIG.

In FIG. 4, the power supply voltage Vcc,
Reference voltage Vref, comparators A1, A2,..., A2
53, A254, A255 threshold voltages V1, V2,
.., V254, V255, and the voltage signal Vin, for example, as shown in the figure, the output when the comparator performs continuous comparison at a predetermined timing is as shown in FIG. . In this case, the comparison output of each comparator at a certain time point T is
Although the time required for converting to 8-bit binary signal data differs depending on the element, for example, the conversion time is set to 50n.
Assuming that s, the voltage signal Vin can be A / D converted at high speed. The display unit 13 temporarily stores the binary signal data transmitted from the encoder 12 in, for example, a memory, and displays the signal waveform on a CRT or records it on a recording paper.

[0010]

The above-mentioned conventional apparatus has a relatively simple structure, and is suitable for visually monitoring the waveform of an input signal and the like. However, for example, when the power supply voltage fluctuates, the threshold voltage of each comparator changes, so that even if the input signal has the same level, the digital conversion data may have a different value. Therefore, the present invention is not always applicable to electronic measuring instruments for measuring the absolute level of an input signal.

For example, in FIG. 5 which is an excerpt of the ladder resistor of FIG. 3, the reference voltage Vref is obtained by dividing the power supply voltage Vcc by the resistor Rs and the ladder resistor groups R1 to R256, so that Vref = Vcc × Rs / (Rs + R1 + R2 + ...
+ R256). Here, for the sake of simplicity, if, for example, R1 = R2 =... = R256 = R [Ω], then Vref = Vcc × Rs / (Rs + R × 256) (1) Assuming that the voltage between the reference voltage Vref and the threshold voltage V1 and the difference between the adjacent threshold voltages is Vδ, Vδ = (Vcc−Vref) / 256 (2) Is substituted, Vδ = Vcc {1−Rs / (Rs + R × 256)} / 256 (3)

Next, the power supply voltage Vcc fluctuates to Vcc '
Let Vref 'be the reference voltage and Vδ' be the difference voltage between the adjacent threshold voltages, Vref '= Vcc'.times.Rs / (Rs + R.times.256) in the same manner as described above. 4) Vδ ′ = (Vcc′−Vref ′) / 256 = Vcc ′ {1−Rs / (Rs + R × 256)} / 256 (5) When Expression (4) is divided by Expression (1), Vref ′ / Vref = Vcc '/ Vcc From the above equation, Vref' = Vref (Vcc '/ Vcc) When the variation of the power supply voltage is △ V, and Vcc' = Vcc ± △ V, Vref '= Vref (Vcc ± △ V ) / Vcc = Vref (1 ± △ V / Vcc) (6) When Expression (5) is divided by Expression (3), Vδ ′ / Vδ = Vcc ′ / Vcc. Vδ ′ = Vδ (1 ± △ V / Vcc) (7) is obtained in the same manner as when the equation (6) is derived. According to equations (6) and (7), when the power supply voltage changes, both the reference voltage and the threshold voltage change at the same rate as the change rate.

By the way, assuming that the power supply voltage Vcc is 5 [V] and the reference voltage Vref is 3 [V], the voltage Vδ of the threshold voltage difference is given by the following equation (2). Vδ = (5-3) /256=0.00781 [V]. In this case, for example, the magnitude of the 200th threshold voltage V200 from the bottom is V200 = Vref + Vδ × 200 = 3 + 0.00781 × 200 = 4.562 [V]. Therefore, if the input signal voltage Vin is in the range of 4.5620 <Vin ≦ 4.5620 + 0.00781, that is, 4.5620 <Vin ≦ 4.5698 (8), from Vcc−Vδ to Vcc, that is, 4 In an A / D converter that converts an input voltage from 0.9922 [V] to 5 [V] to a FF as a full scale voltage, the signal Vin is converted to a binary corresponding to a threshold voltage of V562 of 4.562 [V]. Data "1
1001000 ".

Here, assuming that the power supply voltage Vcc changes by, for example, 2% to Vcc ', the reference voltage Vref' is calculated from the equation (6) as follows: Vref '= (1 ± 0.02) × 3 [V] From the equation (7), the difference voltage Vδ ′ is Vδ ′ = (1 ± 0.02) × 0.00781 [V]. Now, for the sake of simplicity, for example, when the power supply voltage fluctuates by 2% to the positive side, Vref '= 3.06 [V] Vδ' = 0.00797 [V]. Since the difference voltage from the reference voltage changes in this manner, the threshold voltage V200 before the power supply voltage changes does not correspond to the input signal voltage Vin. Therefore, after the power supply voltage fluctuates, the threshold voltage corresponding to the above Vin is changed to V
Assuming that (n), V (n) <Vin ≦ V (n + 1) (9) In the above equation, V (n) = Vref ′ + Vδ ′ × n = 3.06 + 0.00797 × n [V] V (n + 1) = Vref ′ + Vδ ′ × (n + 1) = 3.06 + 0.00797 × (n + 1) [V] ].

In this case, since the value of Vin has a width as shown in equation (8), if, for example, the median value is taken as Vin = 4.5659 [V], then from equation (9), 3.06 + 0. 00797 × n <4.5659 ≦ 3.06 + 0.00797 × (n + 1) (10) From 3.06 + 0.00797 × n <4.559 in the equation (10), n <188.9. Further, n ≧ 187.9 from 4.5659 ≦ 3.06 + 0.00797 × (n + 1) in the equation (10). Therefore, n = 188 is obtained as the value of n that satisfies 187.9 ≦ n <188.9. That is, when the power supply voltage 5 [V] changes by, for example, + 2%, the threshold voltage corresponding to the input signal voltage 4.5659 [V] changes from V200 to V188. Therefore, the voltage of the input signal Vin is converted into binary data “10111100” corresponding to the threshold voltage of V188.

As described above, when the power supply voltage fluctuates, an input signal at the same level is converted into binary data having a different value, which is not preferable for a measuring instrument because it causes a measurement error. SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a high-speed A that prevents digital conversion data of an input signal from being affected even when a power supply voltage fluctuates.
An object of the present invention is to provide a / D conversion device.

[0017]

Referring to FIG. 1, which illustrates an embodiment of the present invention, amplifiers 2, 3, 4, and A
The / D converter 5, the display unit 13 and the like are constituted by substantially the same units as those of the conventional device, and therefore, are denoted by the same reference numerals. In this embodiment, the following means are provided to solve the above problems. That is, for example, a Zener diode ZD that operates at the power supply voltage + Vcc and its current limiting resistor Ra, and a voltage dividing resistor R that divides and extracts a part of the voltage drop of the Zener diode ZD.
b, Rc, and the series voltage of the extracted divided voltage and the voltage drop generated in the current limiting resistor Ra.
And a reference voltage forming circuit 15 for forming a reference voltage Vref and applying the same to the low potential side terminal 11 of the ladder resistor 6.

For example, the voltage Vm at the center potential terminal 14 of the ladder resistor 6 is applied to the amplifier 18, and the amplifier 18 and the next-stage amplifier 19 form a bias voltage −Vb for zero-line shift of the input signal Vin, and the input amplifier 2
And a bias voltage forming circuit 17 to be applied to the output side.

[0019]

The voltage drop across the Zener diode ZD in the reference voltage forming circuit 15 of the above-mentioned means for solving the problem can be considered to be constant even if the power supply voltage Vcc fluctuates. Therefore, when the power supply voltage changes by, for example, ± ΔV, the voltage drop of the current limiting resistor Ra changes by ± ΔV. Then, the voltage drop of the current limiting resistor Ra,
A reference voltage Vref is formed by adding in series a voltage obtained by dividing a part of the voltage drop between both ends of the Zener diode ZD by the resistor Rb, and a low potential terminal of the ladder resistor 6 via the amplifier 16. In addition, even if the power supply voltage Vcc applied to the high potential side terminal 10 changes by ± ΔV, the voltage between both terminals 10-11 does not change and is maintained at a predetermined constant voltage. Thereby, the threshold voltage V1, V2,...
δ does not change, and thus the threshold voltage viewed from the terminal 11 does not change.

Next, the bias voltage forming means 17 of the means for solving the above problem takes in the potential voltage + Vm from the center potential terminal 14 of the ladder resistor 6, for example, and the amplifiers 18 and 19 apply the bias voltage -Vb Is applied to the output side of the amplifier 2. Thus, the absolute value Vb of the bias voltage −Vb becomes equal to the power supply voltage Vc.
Even if c fluctuates, it becomes equal to the level of the central potential voltage Vm of the ladder resistor 6, and the zero line of the input signal Vin is A / D
It is always kept at the center voltage level of the allowable input voltage range of converter 5.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1 described above, portions which are configured similarly to a conventional apparatus will be briefly described. When the converted analog AC signal Vin is applied to the amplifier 2 via the input terminal 1 of the device, the amplifier 2 selects an appropriate range according to the signal level, inverts and amplifies the input signal Vin, and outputs
Add to In this embodiment, in order to shift the zero line of the inverted output signal Vin of the amplifier 2 to the negative side, for example, a bias voltage -Vb is applied from the bias voltage forming circuit 17 to the output side of the amplifier 2. .
The amplifier 3 inverts and amplifies the output Vin of the amplifier 2 in which the zero line is shifted to -Vb on the negative side with a gain of 1, for example. Thus, the output Vin of the amplifier 3 becomes a signal having + Vb on the positive side as a zero line. The amplifier 4 non-inverts and amplifies the output of the amplifier 3 with a gain of 1, for example, and an A / D converter 5
To the signal input terminal 9.

In the A / D converter 5, the signal Vin applied to the signal input terminal 9 is applied in parallel to comparator groups A1 to A255 of the comparator 7, and the threshold value given to each of the comparators from the ladder resistor 6 is applied. , V255, respectively. In this embodiment, for example, one high potential side terminal 10 of the ladder resistor 6 is connected to the power supply voltage + V of the device.
The reference voltage + Vref is applied from the reference voltage forming circuit 15 to the other low potential side terminal 11.

The reference voltage forming circuit 15 includes, for example, a Zener diode ZD and a current limiting resistor Ra, and resistors Rb and Rc for dividing a voltage drop between both ends of the Zener diode ZD, as described in the means for solving the problem. Same resistance R
The amplifier 16 forms a reference voltage Vref by serially adding the voltage drop of the current limiting resistor Ra to the voltage divided at b.

Here, in FIG. 2A, which is an excerpt of the reference voltage forming circuit 15 of FIG. 1, the power supply voltage V
Assuming that the voltage drops of the Zener diode ZD and the current limiting resistor Ra when Vcc is added are Vz and Va, respectively, Vcc = Vz + Va (11) In equation (11), the voltage drop Vz of the Zener diode ZD is equal to the power supply voltage V
It is a constant voltage that is not affected by the fluctuation of cc, and the voltage drop Va of the resistor Ra is a voltage that changes according to the fluctuation of the power supply voltage Vcc.

Now, the voltage drop Vz of the Zener diode ZD is divided by, for example, resistors Rb and Rc, and the resistor Rb is further adjusted to obtain a desired reference voltage Vref based on the divided voltage Vba and the voltage drop Va of the resistor Ra. Is set, Vref = Vba + Va (12) By substituting equation (11) for Va in equation (12), Vref = Vba + Vcc-Vz (13) In the equation (13), for example, assuming that the reference voltage when the power supply voltage Vcc fluctuates ± △ V is Vref ′, Vref ′ = Vba + VCC ± △ V-Vz From the above equation and the equation (13), Vref ′ = Vref ± △ V (14) is obtained. That is, when the power supply voltage Vcc changes by ± ΔV, the reference voltage Vref also changes at the same voltage.

Therefore, when this reference voltage Vref is applied to the low potential side terminal 11 of the ladder resistor 6 via, for example, the non-inverting amplifier 16 having a gain of 1, the power supply applied to the high potential side terminal 10 of the ladder resistor 6 is changed. When the voltage Vcc changes by + ΔV, the reference voltage Vref also changes by + ΔV, and when the Vcc changes by −ΔV, Vref also changes by −ΔV. That is, the voltage Vcc-Vref between both terminals of the ladder resistor 6 is kept constant regardless of how the power supply voltage Vcc fluctuates. This state is shown in FIG. Therefore, each of the threshold voltages V1 to V
255 is not affected by fluctuations in the power supply voltage.

As described in the above-mentioned means for solving the problem, the bias voltage forming circuit 17 amplifies the central potential voltage Vm of the ladder resistor 6 with a gain of 1, for example, and inverts the output of the amplifier 18 with a gain of 1. It is composed of an amplifier 19. Here, the central potential voltage V of the ladder resistor 6
The magnitude of m is Vm = (Vcc-Vref) / 2 (15). Since the amplifier 18 receives the above-mentioned voltage Vm with respect to the ground, the input voltage of the amplifier 18 becomes Vm + Vref = (Vcc-Vref) / 2 + Vref. Since the bias voltage −Vb output from the amplifier 19 is the inverted voltage of the above equation, −Vb = − (Vm + Vref), and the polarity is negative. However, the output of the inverting amplifier 3 is further inverted to have a positive polarity. Vb = Vm + Vref (16) Here, for example, when the power supply voltage Vcc fluctuates by ± ΔV, the reference voltage Vref also fluctuates by ± ΔV as described above, so that Vcc → Vcc ± ΔV Vref → Vref ± Assuming that the central potential voltage when ΔV is set as Vm ′ and the bias voltage is Vb ′, Vm ′ = {(Vcc ± ΔV) − (Vref ± ΔV)} / 2 = (Vcc−Vref) / 2 Become. From the above equation and equation (15), Vm '= Vm, and it can be seen that the central potential voltage Vm does not change.

Further, as for the bias voltage Vb ′, Vb ′ = Vm ′ + (Vref ± ΔV) = Vm + (Vref ± ΔV) From the above equation and equation (16), Vb ′ = Vb ± ΔV, and the bias voltage Vb is obtained. ´ (the level of the zero line) is △
It can be seen that it fluctuates by V. These states are also shown in FIG. Since the signal waveforms I to I of the respective parts in FIG. 4 in the conventional apparatus can be obtained also in the embodiment of the present invention, corresponding parts are denoted by the same reference numerals.

[0029]

As described above in detail, the present invention includes, for example, a Zener diode ZD which operates at the power supply voltage Vcc of the device and a current limiting resistor Ra, and a voltage drop Va of the current limiting resistor Ra and the Zener diode. Diode ZD
A voltage Vba obtained by dividing the voltage drop is added in series to form a predetermined reference voltage Vref, and one low potential side terminal 11 of the ladder resistor 6 is driven by the reference voltage Vref via the amplifier 16. The reference voltage forming circuit 15 is provided.

Further, for example, the terminal 1 of the ladder resistor 6
4 includes a bias voltage forming circuit 17 provided with amplifiers 18 and 19 for taking in and amplifying the central potential voltage Vm of the ladder resistor 6 and shifting the zero line of the converted analog AC signal Vin to a predetermined voltage level. .

Therefore, according to the present invention, the power supply voltage Vcc applied to the other high-potential side terminal 10 of the ladder resistor 6 varies as the level comparison threshold voltage applied from the ladder resistor 6 to the comparator 7. However, there is no change under the influence. Also, the AC input signal Vin
Is maintained at the center potential voltage of the ladder resistor 6, that is, the center voltage level of the allowable input voltage range of the A / D converter 5, and even if the power supply voltage Vcc fluctuates, the zero line does not shift. There is no.

For this reason, for example, when a waveform of an image signal is recorded on a recording paper and its level is measured, accurate measurement data can be obtained, and a high-speed and high-precision A / D suitable for electronic measuring instruments.
A conversion device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an A / D converter according to the present invention.

FIG. 2 is an explanatory diagram of the operation of the problem solving means applied to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional device.

FIG. 4 is a signal diagram for explaining the operation of the conventional device.

FIG. 5 is a configuration diagram of a ladder resistor for explaining a problem in the conventional device.

[Explanation of symbols]

 Reference Signs List 5 A / D converter 6 Ladder resistance 7 Comparator 15 Reference voltage forming circuit 16 Amplifier 17 Bias voltage forming circuit 18 Amplifier 19 Amplifier A1-A255 Amplifier group R1-R256 Ladder resistance Ra Zener current setting resistance Rb Voltage dividing resistance Rc Voltage dividing resistance V1-V255 Threshold voltage Va Voltage drop of Zener current setting resistor Vb Bias voltage Vba Divided voltage Vcc Power supply voltage Vin AC input signal Vm Central potential voltage of ladder resistor Vref Reference voltage Vz Voltage drop of zener diode

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] 1. A ladder resistor (6) for generating various threshold voltages in a group of resistors provided between a power supply voltage (Vcc) of a device and a predetermined reference voltage (Vref); A group of amplifiers, each of which has the threshold voltage generated by the resistor (6) as one input and an AC analog input signal (Vin) as the other input in common and compares the threshold voltage with the threshold voltage, respectively. And a parallel comparison type A / D converter (5) including a comparator (7) provided with the input signal (Vin).
b) is added to shift the zero line of the signal to within the permissible analog input voltage range of the A / D converter (5), and the A / D converter converts the shifted input signal to digital by the A / D converter. In the above, a Zener diode (ZD) and a Zener current setting resistor (Ra) provided in series between the power supply voltage (Vcc) and ground, and a voltage drop (Vz) between both ends of the Zener diode (ZD) (Rb, Rc) to divide voltage
And a voltage drop (Va) between both ends of the divided voltage (Vba) by the resistor and the Zener current setting resistor (Ra).
A reference voltage forming circuit 15 for applying an output of the amplifier as a reference voltage (Vref) to the ladder resistor (6); and a ladder resistor (6). Amplifier (18, 1) that takes in and amplifies the voltage (Vm) at the central potential terminal (14) of the
9), the positive or negative DC output of the amplifier is added as a bias voltage to the input signal (Vin), and the zero line level of the input signal is converted to the A / D converter (5).
And a bias voltage forming circuit (17) for shifting the voltage to a voltage substantially equal to the central potential voltage of the allowable analog input voltage range in (1).