JPH05324576A - Inter-processor synchronization control system - Google Patents

Abstract

PURPOSE:To reduce an overhead of synchronization control by providing a circuit for generating a synchronizing signal, and a selector for selecting plural pieces of synchronization control registers, in an exchange switch of a coupling network. CONSTITUTION:In a coupling network of a multistage constituted of exchange switches 00-03, 10-13, and 20-23 for coupling plural processors 0-7 and memories 100-107, Ack signal generating circuits (counters) 30-32 for showing a fact that a memory request passes through are provided in the exchange switches of each stage. Also, synchronization control registers 50-52 are distributed and arranges in each stage, and moreover, a register 60 for holding a PE number written in this register, and selectors 40-42 for selecting plural pieces of synchronization control registers are provided. Therefore, synchronization control required for transferring shared data between the processors can be executed at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device comprising a plurality of arithmetic processors, a storage device interleaved with a plurality of modules, an interconnection network connecting the arithmetic processing devices and the storage devices, and arithmetic processor mutual interconnections. The present invention relates to an interprocessor synchronization control method in an information processing device that is configured by a synchronization control register used for synchronization control between processors.

[0002]

2. Description of the Related Art Tightly coupled circuits comprising a plurality of arithmetic processors, memories interleaved in a plurality of modules, an interconnection network connecting the processors to each other, and a synchronization control register used for synchronization control between the processors. FIG. 1 is a block diagram showing a parallel computer having a multiprocessor configuration. In this parallel computer, shared data is transferred between processors via a memory. At this time,
A synchronization control register is used for synchronization control between processors so that shared data can be delivered and received correctly.

Delivery of shared data using the synchronization control register is performed as follows. First, the content of the synchronization control register is cleared (0 value). When the writing processor writes the shared data to be transferred in the memory, the processor sets the flag of the synchronization control register (one value). The reading side processor reads the shared data from the memory after confirming that the synchronization control register has been set. As a result, the order of writing the shared data of the writing processor and the reading of the shared data of the reading processor is guaranteed, and the shared data can be transferred correctly.

At this time, in the writing side processor, it is necessary to guarantee the order of writing the shared data and writing the synchronization control register. That is, it is necessary to write to the synchronization control register after confirming that the writing of the shared data has been completed.
If the flag of the synchronization control register is set before the end of writing the shared data, correct data transfer cannot be performed. There are several possible methods for guaranteeing the order of the shared data writing and the synchronization control register writing.

First, the order guarantee can be easily realized by adopting a connection network satisfying the order guarantee. Here, the connection network that satisfies the order guarantee is a connection network that guarantees the temporal order relation of the memory access requests issued by the processors and accesses the memories in the order. An example of such a connection network is bus connection. In this case, the writing processor may set the flag in the synchronization control register after issuing the shared data write command. That is, since the order of the write command and the read command guaranteed by the synchronization control register is held in the connection network and issued to the memory, correct data transfer is possible.

[0006] However, in a multistage connection network with a buffer, which performs arbitration control by packet switching control, since the order guarantee of memory access is not satisfied, it is necessary to add a circuit for order guarantee control. As an example of this circuit, a signal line for writing shared data and returning completion is provided between the processor and the memory device, and the memory device responds to all memory accesses with an Ack signal indicating the completion of memory access. Return to. After receiving these signals, the writing processor issues a flag setting instruction for the synchronization control register.

[0007]

When the number of processors exceeds several tens, it becomes quite difficult to realize a connection network satisfying the order guarantee. That is, the control becomes complicated, and the effective throughput of the connection network may be reduced. In this case, a packet switching control multistage coupling network is often adopted.

However, when the above-described sequence guarantee control method is used in a multi-stage connection network, the TAT (turn aland time) of the flag setting operation of the synchronization control register becomes long, which causes deterioration of system performance. Become. That is,
The write command signal to the shared memory reaches the storage device,
Until the Ack signal indicating that the memory access is completed is returned, it is impossible to issue the flag setting instruction of the synchronization control register, so that useless waiting occurs.

[0009]

SUMMARY OF THE INVENTION An interprocessor synchronization control system of the invention of the present application for solving the above-mentioned problems is provided in a multistage connection network composed of exchange switches for connecting a plurality of processors and memories. An Ack signal generation circuit that indicates that a memory request has passed is provided in the exchange switch of the stage, the synchronization control registers are arranged in a distributed manner in each stage, and a register for holding the PE number written in this register and a plurality of registers are provided. By providing a selector that selects one of the synchronization control registers, a means is provided which can perform the synchronization control required for transferring shared data between the processors at high speed.

At this time, the present invention can be applied to the multistage connection network regardless of the topology of the network, provided that the following conditions are satisfied. That is, if the processor and the memory module are uniquely determined, only one route in the connection network is determined, and it is sufficient if the connection switch does not cause the memory request packets before and after it to overtake on the path.

If the memory access packet between a plurality of processors uses the same path from a certain stage in the connection network to the memory, the order of the memory access after that stage is guaranteed. Therefore, the flag of the synchronization control register can be set when it is confirmed that all the memory access packets have passed through this stage. Therefore, the synchronization control registers are distributed and arranged in each stage (they physically consist of a plurality of registers, but logically appear as one synchronization control register), and the write side of this register Performs writing separately when it is guaranteed that the memory request packet has passed in each stage, and the reading side selects and reads the synchronization control register to be read from the write processor number and the read processor number. It becomes possible to perform high-speed synchronous control between two processors.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. As an example, a description will be given of a synchronization method in a multiprocessor configuration including eight processors and eight interleaved memory modules, using an Omega network using an exchange switch with a buffer as an interconnection network. Hereinafter, the synchronization control register is referred to as a communication register.

In FIG. 2, eight processors 0, ...
, 107 interleaved with eight modules, and Omega connecting them. The Omega network is composed of three stages, and four 2 × 2 buffered exchange switches are arranged in each stage. Set the first-stage replacement switch to 00, ..., 03,
It is assumed that the middle-stage exchange switches are 10, ..., 13 and the final-stage exchange switches are 20, ..., 23. Since it is an Omega network, the processor and the exchange switch, and also the exchange switch are shuffle-coupled. Each switching switch arbitrates contention of two packets in the switching switch, and when a conflict occurs, a request with a high priority is passed and a request with a low priority is held in a buffer in the switching switch.

Counters 30, 31, 32, selectors 40, 41, 42, communication register sections 50, 5 are provided in each stage.
1, 52 are provided. The counter is connected to four exchange switches each. The input side of the selector is connected to the counter and the communication register bus, and selects the signal from the counter and the signal from the communication register bus.

Corresponding to each communication register, there is a PE number register section 60 for holding the PE number whose value is written in this communication register. Further, there are a decoder section 61 and a communication register selector section 62 for selecting a value read from the communication register.

It is issued as a normal memory access command (memory write command, memory read command) packet and reaches the memory through the memory access path in the Omega network. The memory accesses the memory according to the OPCODE of the packet.

The instructions for operating the communication register are as follows: (1) SCR (writing communication register) The processor uses the communication register bus to rewrite the contents of the communication register indicated by the CR address of each communication register section 50, ..., 52. In addition, PE number register unit 6
Write its own processor number in the PE number register indicated by the CR address of 0. Also, each selector 40, ...
42 has a selection signal for selecting WriteDATA of the communication register bus. (2) CSCR (Write Communication Register with Order Guarantee) The processor sends this command packet to the memory access path. Also, using the communication register bus, P
The processor number is written in the PE number register indicated by the CR address of the E number register unit 60, and a selection signal for selecting a signal from the exchange switch is sent to each selector 40, ..., 42. When the first-stage switching switches 00, ..., 03 receive this CSCR packet, they broadcast the CSCR packet to two output ports. Further, the CSCR packet is also sent to the counter 30. When the counter 30 receives the CSCR packet, it sends it to the selector 40, and the selector 40 sends the main CSCR packet to the communication register unit 50. Communication register unit 50 is CS
The contents of the communication register indicated by the CR address in the CR packet are replaced with the value of the data in the CSCR packet. The two exchange switches 10, ..., 13 in the middle stage are each a CSC.
When receiving R packet, C for 2 output ports
Broadcast the SCR packet. Further, the CSCR packet is also sent to the counter 31. The counter 31 waits until each CSCR packet is received from the two exchange switches. When two CSCR packets are received, they are sent to the selector 41, and the selector 41 sends the present CSCR packet to the communication register unit 51. The communication register unit 51 rewrites the contents of the communication register indicated by the CR address in the CSCR packet with the value of the data in the CSCR packet. The last four exchange switches 20, ..., 23
When each of the CSCR packets is received, the counter 32
To send a CSCR packet. The counter 32 waits until it receives a CSCR packet from each of the four switching switches. When the four CSCR packets are received, they are sent to the selector 42, and the selector 42 sends the present CSCR packet to the communication register unit 52. Communication register section 52
Rewrites the contents of the communication register indicated by the CR address in the CSCR packet with the value of the data in the CSCR packet. (3) LCR (reading communication register) The processor uses the communication register bus to read the contents of the communication register indicated by the CR address of each communication register unit 50, ..., 52. In addition, the PE number register unit 60
The content of the PE number register indicated by the CR address is read. Since there are a plurality of communication register sections, the communication register selector section 62 and the decoder 61 determine which communication register section to select the contents of the communication register section. Decoder section 6
1 compares the PE number read from the PE number register unit 60 with its own processor number and sends the selection number to the communication register selector unit 62. The communication register selector unit 62 selects the data read from the communication register according to the selection number and returns this data to the processor. Here, the selection signals are as follows. The processor number that issued the LCR is (a1, a2, a3). (A1,
a2, a3) are PE number binary representations, and a is a's complement representation. P read from the PE number register section
If the E number is (a1, a2, a3), a selection signal for selecting the communication register unit 50 is transmitted. If the PE number read from the PE number register section is (a1, a2, a3), a selection signal for selecting the communication register section 51 is sent. If the PE number read from the PE number register section is (a1, a2, a3), a selection signal for selecting the communication register section 52 is sent.

In this configuration, the shared data transfer between the two processors is performed as follows. First, the processor on the writing side clears (0 value) the communication register using the SCR instruction. At this time, the three communication register units 5
The value of the CR register having the same CR address of 0, ..., 52 is cleared.

After the writing processor issues a data write command to the memory, the processor writes CSC.
Issue the R instruction. This CSCR instruction is an instruction to set a flag (one value) in the communication register. The processor on the reading side checks this communication register until the flag is set by the LCR instruction, and if it is set, issues a read instruction of shared data.

The processor number on the writing side is (a1, a
2, a3). The processor number of the reading side is (a
1, a2, a3), the memory request packet on the write side and the memory request packet on the read side for the arbitrary memory module pass through the same path after the first-stage exchange switch. Access overtaking does not occur and the order is guaranteed. In this case, according to the CSCR and LCR instruction rules, the communication register select unit 62 selects the data in the communication register unit 50. That is, since the flag is set after the write-side CSCR packet has passed through the first-stage exchange switch, the guarantee of the order is satisfied.

The processor number on the reading side is (a1, a
2, a3), since the memory request packet on the write side and the memory request packet on the read side pass through the same path after the middle-stage exchange switch for any memory module, memory access is performed after the middle-stage switch. Ordering is guaranteed without overtaking. In this case, the communication register / selection unit 62 selects the data in the communication register unit 51. In other words, CS on the writing side
Since the flag is set after the CR packet passes through the two exchange switches in the middle stage, the guarantee of ordering is satisfied.

The processor number on the reading side is (a1, a
2, a3), the memory request packet on the write side and the memory request packet on the read side pass through different paths to the final-stage exchange switch for any memory module. The order is not guaranteed unless the flag of the communication register is set after confirming that the switch has been passed. In this case, the communication register / selection unit 62 selects the data in the communication register unit 52. That is, since the flag is set after the write-side CSCR packet has passed through the four exchange switches in the third stage, the guarantee of the order is satisfied.

FIG. 3 shows a block diagram of the communication register section. The communication register unit includes a plurality of registers 00, ...
It is composed of a communication register file 0 composed of 0n and a communication register control unit 1. WriteDATA10
The 0 signal line is the output of the selectors 40, ..., 42 of FIG. 2, and the ReadDATA 101 signal line is the input of the communication register selector unit 62 of FIG.

If the instruction indicated by OPCCODE 102 is a write instruction, the value of the communication register at the address indicated by CR address 102 is replaced with the value of WriteDATA 100. If the instruction indicated by OPCCODE 102 is a read instruction, the value of the communication register at the address indicated by CR address 102 is changed to ReadDATA101.
To the signal line of.

FIG. 4 is a block diagram of the PE number register section. The PE number register unit comprises a PE number register file 0 composed of a plurality of PE number registers 00, ..., 0n and a PE number register control unit 1. The WritePE number is the communication register bus 20 of FIG.
0 PE number field signal line, ReadPE
The number 101 is an input to the decoder 61 in FIG.

If the instruction indicated by OPCCODE 102 is a write instruction, the value of the PE number register at the address indicated by CR address 102 is set to WritePE number 10.
Replace with a value of 0. If the instruction indicated by OPCCODE 102 is a read instruction, the value of the PE number register at the address indicated by CR address 102 is output to the signal line of ReadPE number 101.

FIG. 5 shows a block diagram of the exchange switch. The exchange switch is composed of an arbiter that arbitrates request packets of input ports # 0 and # 1, and a 2 × 3 exchange switch 1 that performs routing based on a selection signal 50 from the arbiter. In the case of a normal memory request, it functions as a 2 × 2 exchange switch and routes a packet to a desired output port. When a CSCR packet is input, it has a function of broadcasting the packet to two output ports and a port to the selector.

FIG. 6 shows a CR operation command packet. The CR operation packet has OPCCODE field 0
In addition to 0, 10 and CR addresses 02, 12, it is composed of its own PE number field that contains the PE number that issued the CR command. (In case of CR writing, data field 03 is also included)

[0029]

As described above, the flag of the synchronization control register is set by the processor on the writing side after the Ack signal indicating the completion of writing from the memory is received from the storage device. In the synchronous control method of (1), in some processor relations, the memory request packet becomes possible at the time when it passes through a certain stage of the connection network, that is, before reaching the memory, so the overhead of the synchronous control can be considerably reduced. ..

Especially in the future, it is predicted that it is indispensable to connect a large number of processors in a multistage connection in order to improve the performance. At this time, the number of stages of the multistage connection is increased, and in the method of returning the Ask signal from the memory, It is possible that the overhead becomes large and becomes a bottleneck in performance improvement.
In such a case, this method is particularly effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing a parallel computer having a general tightly coupled multiprocessor configuration.

FIG. 2 is a block diagram showing an embodiment of the present invention,
In particular, a configuration diagram illustrating in detail a multiprocessor configuration using an omega network as a connection network.

FIG. 3 is a configuration diagram illustrating a communication register unit in detail.

FIG. 4 is a configuration diagram illustrating a PE number register unit in detail.

FIG. 5 is a configuration diagram illustrating a replacement switch in detail.

FIG. 6 is a configuration diagram illustrating SCR, CSCR, and LCR packets in detail.

[Explanation of symbols]

1, 0, ..., N processors 20 Mutual connection network 30 Synchronous control register device 101, ..., 10n Memory module 201 Communication register bus In FIG. 2, 0, ..., 7 processors 00, ..., 23 With buffer 2 × 2 exchange switch 30, ..., 32 counter 40, ..., 42 selector 50, ..., 52 communication register unit 60 PE number register unit 61 decoder 62 communication register selector unit 100, ..., 107 memory module 200 communication register bus In FIG. 0 communication register file 1 communication register control unit 00, ..., 0n communication register 100 WriteDATA signal line 101 ReadDATA signal line 102 OPCCODE, CR address signal line In FIG. 4, 0 PE number register file 1 PE number register Control part 00, ..., 0n PE number register 100 WritePE signal line 101 ReadPE signal line 102 OPCCODE, CR address signal line In FIG. 5, 0 arbiter 1 2 × 3 switch 00, 01 address, OPOCODE input port 10, 11 OPCODE output port 20, 21 Data input port 30, 31 Data output port 40 Address, OPOCODE output port (counter) 41 Data output port (counter) 50 Selection signal In FIG. 6, 00, 10 OPCODE field 01, 11 Own PE number field 02 , 12 CR address field 03 Write data field

Claims (1)

[Claims] 1. An arithmetic processing device comprising a plurality of arithmetic processors, a storage device interleaved with a plurality of modules, a multi-stage interconnection network interconnecting the arithmetic processing device and the storage device, and the arithmetic operation. In an information processing device including a synchronous control register used for synchronous control between processors, a circuit for generating a synchronous signal in an exchange switch of a junction network, and a synchronous control register distributed and arranged in each stage of a coupling network And a register that holds the processor number that has written to the register and a selector that selects a plurality of synchronization control registers, thereby achieving high-speed synchronization control in shared data transfer between a plurality of processors. An interprocessor synchronization control method characterized by performing.