JPH05324568A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To simplify an information transfer procedure between processors in a multi-processor system, to improve information transfer efficiency, and to reduce a load of both processors. CONSTITUTION:This system is constituted by providing between processors 100 a common storage means 200 in which the transfer origin processor writes information 201 to be transferred and an information write informing signal 202 for informing a fact that this information is written, and due to a fact that the information write informing signal is written, the transfer destination processor detects a fact that the information addressed to its own processor is written and reads it, thereafter, writes information for showing a fact that the information is received, information for showing whether the information is in a receivable state or not thereafter, and the information write informing signal for informing a fact that the information is written, in the transfer origin processor, and a classification of information is determined by a bit position in a storage area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication system in a multiprocessor system for transferring various kinds of information between a plurality of processors.

As the functions of information processing systems have diversified, multiprocessor systems in which the functions are distributed and shared among a plurality of processors have been put into practical use. In this type of multiprocessor system, it is necessary to exchange necessary information between the processors.

[0003]

2. Description of the Related Art FIG. 8 is a diagram showing an example of a conventional multiprocessor system, and FIG. 9 is a diagram showing an example of an inter-processor communication process (initial setting) in FIG.
FIG. 9 is a diagram showing an example of an inter-processor communication process (information transfer) in FIG. 8.

In FIG. 8, the main processor (MCP) 1
Two sets of a control field register (CFR) 3 and a data area (DA) 4 are provided between the slave processor and the sub processor (SCP) 2. The individual control field registers (CFR) are (CFR ₁ ) 3 ₁ and (C
FR ₂ ) 3 ₂ and the individual data areas (DA) are called (DA ₁ ) 4 ₁ and (DA ₂ ) 4 ₂ .

Control field register (CFR ₁ ) 3 ₁
The data area (DA ₁ ) 4 ₁ is the main processor (M 1
It is used to transfer various types of information from the CP) 1 to the slave processor (SCP) 2 and uses the control field register (CFR).
₂ ) 3 ₂ and data area (DA ₂ ) 4 ₂ are used to transfer various information from the slave processor (SCP) 2 to the main processor (MCP) 1.

In FIG. 8 and FIG. 9, when the slave processor (SCP) 2 is powered on, the master processor (M
CP) 1 to status register use permission notification signal st
Wait for _{1 to} be transferred.

On the other hand, the main processor (MCP) 1 gives a permission to use a status register (not shown) to the slave processor (SCP) 2 before starting transfer of various information with the slave processor (SCP) 2. the register usage permission notification signal st _1, the control field register via the bus 5 ₁ (CFR ₁₎ 3 ₁ after writing in, controls the interrupt signals i ₁ through the bus 5 ₁ field register (CFR ₁₎ 3 Write to ₁ .

The slave processor (SCP) 2 receives the interrupt signal i written in the control field register (CFR ₁ ) 3 _1.
When _one reads through the bus 5 _2, the main processor (MC
P) 1 is determined to writing the required information into the control field register (CFR ₁₎ 3 _1, a control field register (CFR ₁₎ 3 status register grant notification signal st ₁ written in ₁ bus 5 reading through _2, a main processor (MCP) status register grant response signal st ₂ showing an authorization to use the status register, not shown gave that the acknowledgment, the control field register via the bus 5 ₂ After writing to (CFR ₂ ) 3 ₂ , the interrupt signal i ₂ is written to the control field register (CFR ₂ ) 3 ₂ via the bus 5 _{2 so} that communication with the main processor (MCP) 1 will be continued thereafter. It is possible.

The main processor (MCP) 1 receives the interrupt signal i written in the control field register (CFR ₂ ) 3 _2.
And ₂ read via the bus 5 _1, the slave processor (SC
P) 2 is a control field register (CFR ₂₎ 3 ₂ To determine the writing the required information, the control field register (CFR ₂₎ 3 ₂ Status register use permission response signal st ₂ written in the bus 5 After reading via ₁ , the communication with the slave processor (SCP) 2 is started thereafter.

In FIG. 8 and FIG. 10, when the main processor (MCP) 1 transfers the required information DT to the slave processor (SCP) 2, the control field register (CFR ₁ ) is transferred via the bus 5 _1. Write request signal w to 3 ₁
After writing q, the interrupt signal i ₁ is written to the control field register (CFR ₁ ) 3 ₁ via the bus 5 ₁ .

The slave processor (SCP) 2 receives the interrupt signal i written in the control field register (CFR ₁ ) 3 _1.
When _one reads through the bus 5 _2, the main processor (MC
P) 1 is judged to writing the required information into the control field register (CFR ₁₎ 3 _1, the write request signal wq being written to a control field register (CFR ₁₎ 3 ₁ bus 5 ₂ Main Processor (MCP) 1 when read through
Confirm that the ready to receive information transferred from the control field register via the bus 5 ₂ (CF
R ₂₎ 3 ₂ after writing the write Allowed response signal wa, bus 5
Write the interrupt signal i ₂ into the control field register (CFR ₂ ) 3 ₂ via ₂ .

The main processor (MCP) 1 receives the interrupt signal i written in the control field register (CFR ₂ ) 3 _2.
And ₂ read via the bus 5 _1, the slave processor (SC
P) 2 is a control field register (CFR ₂₎ 3 ₂ To determine the writing the required information, the control field register (CFR ₂₎ 3 ₂ writable response signal written in the wa
When the read via the bus 5 _1, the slave processor (SCP)
2 is ready to receive information.

Thereafter, the main processor (MCP) 1 is connected to the bus 5
₁Data area (DA₁) 4 ₁According processor
After writing the information DT to be transferred to the (SCP) 2, the bus
5₁Data area (DA₁₁) 4₁₁Write completion notification to
Write signal we, and then bus 5 ₁Control via
Register (CFR₁) 3₁Interrupt signal i₁Write

The slave processor (SCP) 2 is a control processor.
Register (CFR₁) 3₁Interrupt signal i written in
₁The bus 5₂Read through the main processor (MC
P) 1 is the control field register (CFR₁) 3₁In
It is determined that the necessary information has been written, and the control field register
(CFR₁) 3₁Writing end notification signal w written in
bus 5₂Read through the main processor (MC
P) 1 transfers information to the slave processor (SCP) 2
Data area (DA₁) 4₁It is judged that writing to the
Data area (DA₁) 4₁The information DT written in
Space 5₂After reading through, bus 5₂Control through
Field Register (CFR₂) 3₂Reading end notification signal r
write e, and then bus 5₂Control field cash register via
Star (CFR ₂) 3₂Interrupt signal i₂Write

The main processor (MCP) 1 receives the interrupt signal i written in the control field register (CFR ₂ ) 3 _2.
And ₂ read via the bus 5 _1, the slave processor (SC
P) 2 determines that the control field register (CFR ₂ ) 3 ₂ has written the required information, and the read end notification signal r written in the control field register (CFR ₁ ) 3 ₂
When the e read via the bus 5 _1, the slave processor (SC
P) 2 confirms that it has received the information, and the bus 5 ₁
After writing the end notification reception response signal ra read the control field register (CFR ₁₎ 3 ₁ via a write interrupt signal i ₁ to the control field register (CFR ₁₎ 3 ₁ through the bus 5 ₁ ..

As described above, the required information DT is completely transferred from the main processor (MCP) 1 to the slave processor (SCP) 2. In the above process, the slave processor (SCP) 2, which has received the write request signal wq, for some reason, receives the information DT.
If the response information indicating that writing is impossible is returned instead of the write enable response signal wa in the same procedure as described above, the main processor (MCP) 1 writes from the slave processor (SCP) 2. Until the response message wa is returned,
Transmission of write request signal wq is repeated in the same procedure as described above.

[0017]

[Problems to be Solved by the Invention]
In the conventional multiprocessor system,
Is the main processor (MCP) 1 is the slave processor (SC
P) When transferring the required information DT to 2, first write request
The signal wq and the write enable response signal wa are transferred to the slave process
That the SCP (SCP) 2 can receive the information DT.
Information DT is transferred, and then information DT is transferred.
Read end notification signal re and read
In order to transfer the reception end notification reception response signal ra to each other,
Interrupt signal i each time ₁Or i₂Complex procedure, such as transferring
Is required, the main processor (MCP) 1 and
The information transfer efficiency between the slave processors (SCP) 2 also decreases,
In addition, the main processor (MCP) 1 and the slave processor (S
The control of the CP) 2 becomes complicated, and each main processor (MC
P) 1 and slave processor (SCP) 2 load also increases
There was a problem.

An object of the present invention is to simplify the information transfer procedure between processors as much as possible, improve the information transfer efficiency, and reduce the load on both processors.

[0019]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, reference numeral 100 denotes a plurality of processors that form a multiprocessor system, and information 2
01 is transferred.

200 is a processor 100 according to the present invention.
It is a common storage means provided between them.

[0021]

The common storage means 200 is the processor 1 of the transfer source.
00 writes information 201 to be transferred to the transfer destination processor 100 and an information write notification signal 202 notifying that the information 201 has been written, and the transfer destination processor 1
00 detects that the information 201 addressed to the own processor 100 has been written by writing the information write notification signal 202, and after reading the information 201, the information 201 is sent to the processor 100 of the transfer source. The information 201 indicating that the reading has been completed, the information 201 indicating whether or not the information 201 can be received thereafter, and the information writing notification signal 202 notifying that the information 201 has been written are written.

In the common storage means 200, the processor 100 of the transfer source writes the information 201 consisting of 1 bit in a predetermined area in the storage area, so that the information 201 of a predetermined type is transferred to the processor of the transfer destination. Transfer to 100 is considered.

Therefore, each processor recognizes in advance whether or not the information transfer destination processor is ready to receive the information to be transferred, and it is not necessary to confirm each time the information is transferred. The information transfer procedure between processors is greatly simplified, resulting in improved information transfer efficiency and reduced processor load.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a multiprocessor system according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of an inter-processor communication process (initial setting, information transfer) in FIG. 2, and FIG. 4 is a diagram in FIG. FIG. 5 is a diagram showing an example of an inter-processor communication process (information transfer stop), FIG. 5 is a diagram showing an example of an inter-processor communication process (reception unconfirmed) in FIG. 2, and FIG. 6 is an inter-processor communication process in FIG. FIG. 7 is a diagram showing an example of write-protection cancellation not confirmed), and FIG. 7 is a diagram showing an example of inter-processor communication process (monitoring during non-communication) in FIG. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, a main processor (MCP) 1 and a slave processor (SCP) 2 are shown as the processor 100 in FIG. 1, and a common memory 10 is provided as the common storage means 200 in FIG.

In the common memory 10, the status area (S
A) 6 (individual status areas (SA) 6 ₁ and 6
₂ ), and so on) and interrupt flag area (FA) 7
, And a data area (DA) 8 are provided for two sets each.

The status area (SA) 6 ₁ has a status area (S) having a storage capacity of 1 bit.
A ₁₁ ) 6 ₁₁ , (SA ₁₂ ) 6 ₁₂ and (SA ₁₃ ) 6 ₁₃ are provided, and the status area (SA ₁₁ ) 6 ₁₁ is used for the transfer of the read request signal rq ₁ consisting of 1 bit and the status area (S
A ₁₂ ) 6 ₁₂ is used for the transfer of the 1-bit read end signal re ₁ , and the status area (SA ₁₃ ) 6 ₁₃ is used for the transfer of the 1-bit write disable signal ib ₁ .

The status area (SA) 6 ₂ similarly even,
Status areas (SA ₂₁ ) 6 ₂₁ , (SA ₂₂ ) 6 ₂₂ and (SA ₂₃ ) 6 ₂₃ are provided. In FIGS. 3 to 7, for example, setting the storage content (1 bit) of the status area (SA) 6 ₁₁ to logical “1” is referred to as writing the read request signal rq ₁ , and the status area (S
A) Setting the memory content (1 bit) of 6 ₁₁ to logical "0" is referred to as erasing the read request signal rq ₁ , and Δrq
Expressed as ₁ .

Read request signal rq ₂ and read end signal re ₁
The same applies to re ₂ , and write disable signals ib ₁ and ib ₂ . First, initialization and information transfer between the main processor (MCP) 1 and the slave processor (SCP) 2 will be described with reference to FIGS. 2 and 3.

2 and 3, the main processor (MCP) 1 and the slave processor (SCP) 2 are turned on and the main processor (MCP) 1 and slave processor (SCP) 2 receive various information. Prior to starting the transfer, the status area (SA ₁₁ ) 6 _{11 is} sent via the bus 5 _1.
The read request signal rq ₁ (logical “1”) is written to the data area (DA ₁ ) 8 ₁ and the initial setting request information ISQ ₁ for requesting the initial setting to the processor (SCP) 2 via the bus 5 _1. After writing, the interrupt flag f ₁ (logical “1”) is written to the interrupt flag area (FA ₁ ) 7 ₁ via the bus 5 ₁ and the read wait timer T ₁ (500 milliseconds)
Start the response wait timer T ₂ (variable).

The slave processor (SCP) 2 has an interrupt flag.
Area (FA₁) 7₁Interrupt flag f written in₁(logic
Take "1") to bus 5₂Read through the main processor
(MCP) 1 is the status area (SA₁) 6₁, (SA
₂) 6₂Or data area (DA₁) 8₁Write to
Bus 5₂Status area (SA
₁₁) 6₁₁Read request signal rq₁Read (logical "1")
And then bus 5₂Data area (DA₁) 8₁
To initial setting request information ISQ₁After reading the
Area (SA₁₁) 6₁₁Read request signal r written in
q₁The bus 5₂Delete via (logic “0”) (Δrq
₁), Bus 5 again₂Status area (SA₁₂)
6₁₂Read request written by the main processor (MCP) 1.
Signal rq ₁And initial setting request information ISQ₁Read the end
A read end signal re indicating that it has crossed₁(Logical "1")
After writing, bus 5₂Interrupt flag area (F
A₂) 7₂Interrupt flag f₂If you write (logical "1")
Both implement the initial setting process in the slave processor (SCP) 2.
To go.

On the other hand, the main processor (MCP) 1 has the interrupt flag f written in the interrupt flag area (FA ₂ ) 7 _2.
2 (logic "1"), when read through the bus 5 _1, slave processor (SCP) 2 status area (SA ₁₎
6 ₁ , (SA ₂ ) 6 ₂ or data area (DA ₂ ) 8 ₂
It is determined that the write request has been written to the status area (SA ₁₁ ) 6 ₁₁ via the bus 5 ₁ and the read request signal Δrq has been deleted.
_{When 1} (logic “0”) is read and then the read end signal re ₁ is read from the status area (SA ₁₂ ) 6 ₁₂ via the bus 5 ₁ , the slave processor (SCP) 2 causes the master processor (MCP) 1 It is determined that the initial setting request information ISQ ₁ transferred from is read, and the read waiting timer T ₁ is stopped.

On the other hand the slave processor (SCP) 2 completes the initial setting process based on the initial setting request information ISQ ₁ received, the status area (SA ₂₁₎ through the bus 5 ₂
Writing 6 ₂₁ to the read request signal rq ₂ (logic "1"), also notifies the completion of the initial setting based on the data area (DA ₂₎ 8 ₂ Initial setup request information ISQ ₁ to via the bus 5 ₂ after writing the initialization completion notification information ISE _2, interrupt flag area (FA ₂₎ via the bus 5 ₂ 7 with writing interrupt flag f ₂ (logic "1") _2, read wait timer T Start ₁ (500 milliseconds).

The main processor (MCP) 1 has an interrupt flag.
Area (FA₂) 7₂Interrupt flag f written in₂(logic
Take "1") to bus 5₁Read through the slave processor
(SCP) 2 is the status area (SA₂) 6₂, (SA
₁) 6₁Or data area (DA₂) 8₂Write to
Bus 5₁Status area (SA
_{twenty one}) 6_{twenty one}Read request signal rq₂Read (logical "1")
And then bus 5₁Data area (DA₂) 8₂
Initialization completion notification information ISE₂After reading the
Tas area (SA_{twenty one}) 6_{twenty one}Read request signal written in
rq₂The bus 5 ₁Erase via (logic “0”) (Δr
q₂), Bus 5 again₁Status area (S
A_{twenty two}) 6_{twenty two}Read by the secondary processor (SCP) 2
Take request signal rq₂And initialization completion notification information ISE₂To
Read end signal re indicating that the reading is completed₂(logic
After writing "1"), bus 5₁Interrupt flag area via
Area (FA ₁) 7₁Interrupt flag f₁Write (logical “1”)
And wait for response T₂To stop.

On the other hand, the slave processor (SCP) 2 has the interrupt flag f written in the interrupt flag area (FA ₁ ) 7 _1.
1 (logic "1"), when read through the bus 5 _2, the main processor (MCP) 1 status area (SA ₁₎
6 ₁ , (SA ₂ ) 6 ₂ or data area (DA ₁ ) 8 ₁
It is determined that the write request has been written to the status area (SA ₂₁ ) 6 ₂₁ via the bus 5 ₂ and the read request signal Δrq has been deleted.
₂ reads (logical "0"), followed by the reading completion signal re ₂ read from the status area (SA ₂₂₎ 6 ₂₂ via a bus 5 _2, the main processor (MCP) 1 is, slave processor (SCP) 2 Initialization completion notification information ISE ₂ transferred from
Has been read, and the read waiting timer T ₁ is stopped.

As described above, the information DT can be transferred between the main processor (MCP) 1 and the slave processor (SCP) 2. In the transfer process of the information DT, the main processor (MCP) 1 uses the information DT ₁ instead of the initial setting request information ISQ _{1 in} the data area (DA) 8 in the above-mentioned initial setting process.
_This is executed in the process shown in FIG. 3 by writing ₁ to the slave processor (SCP) 2 and writing the information DT ₂ into the data area (DA ₂ ) 8 ₂ instead of the initialization completion notification information ISE ₂ . Therefore, the description is omitted.

Next, stop of information transfer between the main processor (MCP) 1 and the slave processor (SCP) 2 will be described with reference to FIGS. 2 and 4. 2 and 4, the master processor (MCP) 1 desiring to transfer the information DT _{1 to} the slave processor (SCP) 2 sends a read request signal to the status area (SA ₁₁ ) 6 ₁₁ by the process shown in FIG. rq
Write ₁ (logical "1") and write data area (DA ₁ )
After writing the information DT _{1 in} 8 ₁ , the interrupt flag area (FA
₁ ) The interrupt flag f ₁ (logical “1”) is written in 7 ₁ , and the read waiting timer T ₁ (500 milliseconds) and the response waiting timer T ₂ (variable) are started.

The slave processor (SCP) 2 has an interrupt flag.
Area (FA₁) 7₁Interrupt flag f written in₁(logic
If you read “1”, the status area (SA₁₁) 6₁₁Or
Read request signal rq₁Read (logic "1"), then
Data area (DA₁) 8₁Information from DT₁Read the figure
Information DT in the receive buffer not shown₁As a result of writing
Information DT soon₁The writable empty area is
Status area
(SA₁₁) 6₁₁Read request signal rq written in₁To
Erase (logical “0”) (Δrq₁), Status area
Area (SA₁₂) 6₁₂Read end signal re₁(Logical "1")
And write the status area (SA₁₃) 6
₁₃Information for the main processor (MCP) 1
T₁Write prohibition signal ib for prohibiting transfer of data₁(logic
After writing "1"), the interrupt flag area (FA ₂) 7₂
Interrupt flag f₂Write (logical "1").

On the other hand, the main processor (MCP) 1 has the interrupt flag f written in the interrupt flag area (FA ₂ ) 7 _{2.
When 2} (logical “1”) is read, the status area (S
When the erased read request signal Δrq ₁ (logical “0”) is read from A ₁₁ ) 6 ₁₁ and the read end signal re ₁ is read from the status area (SA ₁₂ ) 6 ₁₂ , the slave processor (SC
P) 2 determines that it has finished reading the information DT ₁ transferred from the main processor (MCP) 1, and waits for a read timer T ₁
However, when the write disable signal ib ₁ is read from the status area (SA ₁₃ ) 6 ₁₃ further, the slave processor (SC
P) 2 determines that the subsequent reception of the information DT ₁ is prohibited, sets a write disable flag (not shown), and activates a write disable release wait timer T ₃ (for example, 3.5 seconds). ..

Thereafter, even if the main processor (MCP) 1 desires to transfer the information DT _{1 to} the slave processor (SCP) 2, while the write disable flag is set,
Read request signal rq ₁ , information DT ₁ and interrupt flag f ₁
Is not executed.

On the other hand, the slave processor (SCP) 2 executes a predetermined process for the received information DT ₁ , and processes the information DT ₂ indicating the completion of execution, which is not shown in FIG. 4 but the same process as that shown in FIG. As a result of sending back to the main processor (MCP) 1 at, as a result of recognizing that an empty area in which the information DT ₁ to be subsequently received can be written is generated in the reception buffer, the written data is written in the status area (SA ₁₃ ) 6 _13. Impossible signal ib ₁
(Logical "1") was deleted (i.e. deletion already write disable signal .delta.Ib ₁ (logic "0") after writing a), interrupt flag area (FA ₂₎ 7 ₂ to the interrupt flag f ₂ Write (logical "1").

When the main processor (MCP) 1 reads the interrupt flag f ₂ (logical "1") written in the interrupt flag area (FA ₂ ) 7 _2, it reads from the status area (SA ₁₃ ) 6 ₁₃ The erased write disable signal Δib ₂ (logical “0”) is read, it is determined that the slave processor (SCP) 2 has released the prohibition of reception of the information DT ₁ , the write disable flag is released, and the write disable flag is written. Disable disable wait timer T ₃ (eg 3.5
Seconds).

[0043] Thereafter the main processor (MCP) 1, when the transfer desired information DT ₁ for slave processor (SCP) 2 occurs, transferring process information DT ₁ to the slave processor (SCP) 2 in shown in FIG.

Next, the unconfirmed reception of the slave processor (SCP) 2 in the main processor (MCP) 1 will be described with reference to FIGS. 2 and 5. 2 and 5, the main processor (MCP) 1 desiring to transfer the information DT _{1 to} the slave processor (SCP) 2 sends a read request signal to the status area (SA ₁₁ ) 6 ₁₁ by the process shown in FIG. rq
Write ₁ (logical "1") and write data area (DA ₁ )
After writing the information DT _{1 in} 8 ₁ , the interrupt flag area (FA
₁ ) The interrupt flag f ₁ (logical “1”) is written in 7 ₁ , and the read waiting timer T ₁ (500 milliseconds) and the response waiting timer T ₂ (variable) are started.

According to the process shown in FIG. 3, when the slave processor (SCP) 2 reads the interrupt flag f ₁ (logic "1") written in the interrupt flag area (FA ₁ ) 7 _1. , Read request signal rq from status area (SA ₁₁ ) 6 _11
1 (logical “1”) is read, then data area (D
A ₁₎ 8 ₁ After reading the information DT ₁ from the status area (SA ₁₁₎ 6 ₁₁ to read being written request signal rq ₁
Is erased (logical “0”) (Δrq ₁ ), and the read end signal re ₁ (logical “1”) is written in the status area (SA ₁₂ ) 6 ₁₂ , and then the interrupt flag area (FA ₂ ) 7 ₂
It is supposed that the interrupt flag f ₂ (logical “1”) is written in and the main processor (MCP) 1 reads the interrupt flag f ₂ written in the interrupt flag area (FA) 7 ₁ . For this reason, if the main processor (MCP) 1 cannot read the interrupt flag f ₂ before the read wait timer T ₁ detects the elapse of 500 milliseconds, the main processor (MCP) 1 will It is judged that an abnormality has occurred in SCP) 2,
After initializing all the storage areas of the common memory 10, initialization is performed between the main processor (MCP) 1 and the slave processors (SCP) 2 based on the process shown in FIG.

Next, unconfirmed write disable cancellation of the slave processor (SCP) 2 in the main processor (MCP) 1 will be described with reference to FIGS. 2 and 6. 2 and 6, the master processor (MCP) 1 desiring to transfer the information DT _{1 to} the slave processor (SCP) 2 sends a read request signal to the status area (SA ₁₁ ) 6 ₁₁ by the process shown in FIG. Write rq ₁ (logical “1”) and write data area (D
A ₁₎ 8 ₁ After writing the information DT _1, the interrupt flag area (FA ₁₎ 7 ₁ with writing interrupt flag f ₁ (logic "1"), read wait timer T ₁ (500 millimeter Seconds) and a response waiting timer T ₂ (variable).

When the slave processor (SCP) 2 reads the interrupt flag f ₁ (logical "1") written in the interrupt flag area (FA ₁ ) 7 _1, it reads from the status area (SA ₁₁ ) 6 ₁₁ read request signal rq reads ₁ (logical "1"), followed by reading the information DT ₁ from the data area (DA ₁₎ 8 _1, the result of writing the information DT ₁ to unexpected shown receiving buffer, longer or information DT _When recognizing that there is no empty area in which ₁ can be written in the reception buffer, the read request signal rq ₁ written in the status area (SA ₁₁ ) 6 ₁₁ is erased (logic as in FIG. 4). “0”) (Δr
q _1), also end signal re ₁ (logic "1" read in the status area (SA) 6 ₁₂₎ with writing, further status area (SA ₁₃₎ 6 ₁₃ unwritable signal ib ₁ (logic "1" ), And then the interrupt flag area (FA ₂ ) 7 ₂
Write the interrupt flag f ₂ (logic “1”) to

When the main processor (MCP) 1 reads the interrupt flag f ₂ (logical "1") written in the interrupt flag area (FA ₂ ) 7 _2, it reads from the status area (SA ₁₁ ) 6 ₁₁ The erased read request signal Δrq ₁ (logical “0”) is read, and the read end signal r is read from the status area (SA ₁₂ ) 6 _12.
Reading e _1, but stops the read wait timer T _1,
Further, from the status area (SA ₁₃ ) 6 _{13 the} write disable signal i
When b ₁ is read, a write disable flag (not shown) is set and the write disable release wait timer T ₃ (for example, 3.5
Second) to start.

After that, even if the main processor (MCP) 1 requests the slave processor (SCP) 2 to transfer the information DT ₁ , while the write disable flag is set,
Read request signal rq ₁ , information DT ₁ and interrupt flag f ₁
Is not executed.

In such a state, for some reason, the main processor (MCP) 1 reads the erasure of the write disable signal ib ₁ until the write disable release wait timer T ₃ detects the elapse of 3.5 seconds. If not taken, the main processor (MCP) 1 determines that an abnormality has occurred in the slave processor (SCP) 2,
After initializing all the storage areas of the common memory 10, initialization is performed between the main processor (MCP) 1 and the slave processors (SCP) 2 based on the process shown in FIG.

The main processor (MCP) 1 is the information D.
When the response waiting timer T ₂ started when T ₁ is transferred to the slave processor (SCP) 2 times out,
Transfer of information DT ₁ and DT ₂ is done by the main processor (MC
P) 1 and the slave processor (SCP) 2 are closed, the same as when the read wait timer T ₁ times out, after initializing all storage areas of the common memory 10, the main processor ( MCP) 1 and slave processor (SC
While executing the initial setting between P) 2, if the forwarding information DT ₁ and DT ₂ is not closed between the main processor (MCP) 1 and the slave processor (SCP) 2, similarly to the conventional The request is retransmitted or the request is abandoned as necessary.

Next, monitoring in the absence of communication in which there is no information to be transferred between the main processor (MCP) 1 and the slave processor (SCP) 2 will be described with reference to FIGS. 2 and 7.

2 and 7, the main processor
(MCP) 1 transfers to slave processor (SCP) 2
Information to be DT₁Main processor in the absence of
(MCP) 1 regular timer (not shown) times out
Then, the main processor (MCP) 1 displays the status area.
(SA₁₁) 6₁₁Read request signal rq₁(Logical "1")
Writing and data area (DA₁) 8₁According processor
(SCP) 2 status monitoring for requesting monitoring of operating status
Request information HC₁After writing, the interrupt flag area (F
A₁) 7₁Interrupt flag f₁If you write (logical "1")
Both read waiting timer T ₁(500 milliseconds) and wait for a response
Chi timer T₂(Variable) and start.

When the slave processor (SCP) 2 reads the interrupt flag f ₁ (logical "1") written in the interrupt flag area (FA ₁ ) 7 _1, it reads from the status area (SA ₁₁ ) 6 ₁₁ read the read request signal rq ₁ (logic "1"), followed by the data area (DA ₁₎ 8 ₁ from the state monitoring request information HC ₁
After reading, the read request signal rq ₁ written in the status area (SA ₁₁ ) 6 ₁₁ is erased (logic “0”).
(Δrq ₁ ) and after writing the read end signal re ₁ (logical “1”) in the status area (SA) 6 ₁₂ , the interrupt flag f ₂ (logical “1”) is written in the interrupt flag area (FA ₂ ) 7 _2. 1 ”)
And the monitoring process of the operating state in the slave processor (SCP) 2 is executed.

On the other hand, the main processor (MCP) 1 has the interrupt flag f written in the interrupt flag area (FA ₂ ) 7 _{2.
When 2} (logical “1”) is read, the status area (S
The erased read request signal Δrq ₁ (logical “0”) is read from A ₁₁ ) 6 ₁₁ and then the status area (SA ₁₂ ) 6
_{When the} reading end signal re ₁ is read from ₁₂ , the reading waiting timer T ₁ is stopped.

On the other hand, when the slave processor (SCP) 2 completes the monitoring processing of the operating state based on the received status monitoring request information HC ₁ , the read request signal rq ₂ (logic "1") is displayed in the status area (SA ₂₁ ) 6 _21. ) writes, also after writing the monitoring mode notification information HA ₂ report data area (DA) 8 ₂ operating state monitoring result based on the state monitoring request information HC _1, the interrupt flag area (FA ₂₎ 7 ₂ Interrupt flag f ₂
Write (logical "1").

When the main processor (MCP) 1 reads the interrupt flag f ₂ (logical "1") written in the interrupt flag area (FA ₂ ) 7 _2, it reads from the status area (SA ₂₁ ) 6 _21. read request signal rq reads ₂ (logical "1"), followed by the data area (DA ₂₎ 8 ₂ from the monitoring mode notification information HA ₂
And confirms that the operating state of the slave processor (SCP) 2 is normal, the status area (SA ₂₁ ) 6
_The read request signal rq ₂ written in ₂₁ is erased (logical “0”) (Δrq ₂ ) and the status area (SA ₂₂ )
After writing the read end signal re ₂ (logic “1”) to 6 ₂₂ , the interrupt flag f is written in the interrupt flag area (FA ₁ ) 7 _1.
Write ₁ (logical “1”) and wait for response wait timer T ₂
Is stopped and the periodic timer is started. As is clear from the above description, according to the present embodiment, the main processor (MCP) 1 stores the initial setting request information ISQ ₁ or information DT ₁ to be transferred to the slave processor (SCP) 2 in the data area (DA) 8 _1. with written into the read request signal rq ₁ status area (SA ₁₁₎ 6 ₁₁ after written to the interrupt flag area the interrupt flag f ₁ (FA) 7 write crowded in accordance processor ₁ (SCP) 2 The slave processor (SCP) 2 erases the read request signal rq ₁ in the status area (SA ₁₁ ) 6 ₁₁ (Δrq ₁ ) and finishes the reading in the status area (SA ₁₂ ) 6 _12. When the signal re ₁ is written, the slave processor (SCP) 2 sends the subsequent information DT ₁
Of the main processor (MC) after writing the write disable signal ib ₁ indicating whether or not to receive in the status area (SA ₁₃ ) 6 ₁₃ and then writing the interrupt flag f ₂ in the interrupt flag area (FA) 7 _2.
P) 1 with the notification of the read result and the slave processor (SC
P) Since it also notifies the receivability status of the information DT ₁ of 2,
When the information DT ₁ is transferred from the main processor (MCP) 1, a procedure for inquiring whether the information DT ₁ of the slave processor (SCP) 2 can be received is not necessary, and the information DT ₁ can be immediately transferred. Compared to the conventional inter-processor communication process shown in FIG. 2, the transfer process of the write request signal wq, the write enable response signal wa, and the read end notification reception response signal ra can be omitted, and the inter-processor communication process is greatly simplified. To be done.

It should be noted that FIGS. 2 to 7 are merely examples of the present invention, and the common storage means 200 is not limited to the common memory 10 shown in the figure, for example, and various modifications are considered. However, the effect of the present invention does not change in any case. It goes without saying that the multiprocessor system which is the object of the present invention is not limited to the one shown in the figure.

[0059]

As described above, according to the present invention, in the multiprocessor system, each processor recognizes in advance whether or not the information transfer destination processor can receive the transferred information. Since it is not necessary to check each time information is transferred, the information transfer procedure between processors is greatly simplified, resulting in improved information transfer efficiency and reduced processor load.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a multiprocessor system according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of an inter-processor communication process (initial setting, information transfer) in FIG.

4 is a diagram showing an example of an inter-processor communication process (information transfer stop) in FIG.

FIG. 5 is a diagram showing an example of an inter-processor communication process (reception unconfirmed) in FIG.

FIG. 6 is a diagram showing an example of an inter-processor communication process (write disable cancellation unconfirmed) in FIG. 2;

7 is a diagram showing an example of an inter-processor communication process (monitoring during non-communication) in FIG.

FIG. 8 is a diagram showing an example of a conventional multiprocessor system.

9 is a diagram showing an example of an inter-processor communication process (initial setting) in FIG.

10 is a diagram showing an example of an inter-processor communication process (information transfer) in FIG.

[Explanation of symbols]

 1 Main Processor (MCP) 2 Slave Processor (SCP) 3 Control Field Register (CFR) 4 Data Area (DA) 5 Bus 6 Status Area (SA) 7 Interrupt Flag Area (FA) 8 Data Area (DA) 10 Common Memory 100 processor 200 common storage means 201 information 202 information writing notification signal

Claims (2)

[Claims] 1. A multiprocessor system for transferring information (201) between a plurality of processors (100), wherein a transfer source processor (100) is transferred to a transfer destination processor (100) between the processors (100). The information (201) to be transferred and the information write notification signal (202) notifying that the information (201) has been written, and the processor (100) of the transfer destination writes the information write notification. When the signal (202) is written, it is detected that the information (201) addressed to the own processor (100) is written, the information (201) is read, and then the processor (100) of the transfer source is read. ), Information (201) indicating that the information (201) has been read, information (201) indicating whether or not the information (201) can be received thereafter, and Inter-processor communication method is characterized by providing information information write notification signal notifying that the writing the (201) (202) and the writing common storage means (200). 2. The common storage means (200) is predetermined by the transfer source processor (100) writing 1-bit information (201) in a predetermined area in a storage area. The interprocessor communication system according to claim 1, wherein the type information (201) is transferred to the transfer destination processor (100).