JPH03122734A - External storage control device - Google Patents

Abstract

PURPOSE:To properly execute caching processing and to prevent a hit rate from being dropped by previously adding caching specification information to an access request on the main CPU side or previously setting up an address to be cached. CONSTITUTION:A main CPU 2, a common memory 3 and an external storage control device 4 are connected to a system bus 1, an external storage device (magnetic disk device e.g.) 5 is connected to the device 4, and when the device 4 interpretes and executes an access request generated from the CPU 2, access to the device 5 can be attained through a cache memory 46. The CPU 2 is provided with two kinds of caching modes, i.e. an overall caching mode and a selective caching mode, and these modes are switched by the prescribed keyboard operation or the like. Consequently, the drop of the hit rate can be minimized and rapid data access can be held as the whole system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an external storage control device equipped with a caching function suitable for a computer system equipped with an external storage device such as a magnetic disk.

(Prior Art) Conventionally, in an external storage control device equipped with this type of caching function, when an access request of some kind arrives from the main CPU, caching processing is uniformly performed in response to all the access requests. It had become.

That is, when an access request arrives from the main CPU, it is first determined whether the corresponding data exists in the cache memory.

If the relevant data exists in the cache memory, then it is determined whether the access type is write or read, and if it is a write, the relevant data is immediately written to the cache memory and the write completion is notified to the main CPU, while if it is a read, the data is immediately written to the cache memory and the main CPU is notified of the completion of writing. For example, the corresponding data is read from the cache memory and sent to the main CPU.

On the other hand, if the relevant data does not exist in the cache memory, the relevant data is read from the external storage device and loaded into the cache memory, and then the same access processing to the cache memory as described above is performed.

In addition, if there is no free space in the cache memory at this time,
The oldest data is erased from the cache memory, and the corresponding data read from the external storage device is loaded into the erased location.

(Problem to be Solved by the Invention) However, in such conventional external storage control devices equipped with a caching function, caching processing is not uniformly performed for all access requests coming from the main CPU. Therefore, it is quite effective for computer systems running on single-task operating systems, but for computer systems running on multi-tasking or real-time multi-tasking operating systems, or when large programs are loaded from disk memory and executed. In this case, a large number of data accesses or data accesses to multiple areas occur, and the hit rate (caching ability) decreases.

In other words, in the case of a computer system that operates on a multitasking or real-time multitasking operating system, multiple tasks operate simultaneously and multiple disk access requests occur, so when an attempt is made to access data, the data is stored in the cache memory. Similarly, when a large program is loaded from disk memory and executed, or when a program that continuously accesses Inuyama's data is run, the data may no longer exist in the cache memory. more likely to cease to exist.

This invention was made in view of the above-mentioned problems, and its purpose is to load large programs from disk memory when applied to a computer system running on a multitasking or real-time multitasking operating system. An object of the present invention is to provide an external storage control device that can minimize the decrease in cache ratio even when a program that continuously accesses a large amount of data is executed. .

[Structure of the Invention] (Means for Solving the vR Problem) In order to achieve the above-mentioned object, the present invention is based on the caching designation information attached to the access request, or based on the caching target address set in advance as the caching target address. means for determining the presence or absence of a caching processing request based on a comparison result between an address of the external storage device and an address related to the address request; and a means for responding to the access request when the determination indicates that a caching processing request exists. and means for performing normal caching processing, while directly performing access processing to the external storage device in response to the access request when there is no caching processing request.

(Function) According to such a configuration, caching processing can be appropriately executed by adding caching specification information to an access request in advance on the main CPU side or by setting a caching target address in advance. By doing so, you can avoid a drop in the hit rate.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a computer system to which an external storage control device according to the present invention is applied.

As shown in the figure, this computer system connects a main CPU 2, a shared memory 3, and an external storage control device 4 to a system bus 1, and connects an external storage device (magnetic disk drive) to the external storage control device 4. 5 is connected, and the external storage control device 4 interprets and executes an access request issued from the main CPU 2, thereby making it possible to access the external storage device 5 via the memory 46.

As shown in FIG. 2, in addition to the cache memory 46, the external storage control device 4 is provided with a work memory 47 used for storing intermediate results of calculations, etc., and these are backed up by a battery 44. .

Further, the external storage control device 4 is connected to the system bus 1 via a bus interface circuit 45 and to the external storage device 5 via an external storage control vcδ1 interface circuit 43.

Functions such as caching processing, which will be described later, are performed by the CPU.
41 is realized by interpreting and executing the program memory 42.

Next, the process of implementing caching processing in the computer system having the above configuration will be explained with reference to the flowcharts of FIGS. 3 to 5.

FIG. 3 is a flowchart showing only the portions related to data access according to the present invention out of the processing executed by the main CPU 2.

Note that this flowchart may be implemented as part of the operating system or as part of each application program.

The main CPLJ2 has two types of caching modes, a general caching mode and a selective caching mode, and switching between these modes is performed by a predetermined keyboard operation or the like.

When an access request occurs during the execution of some application program, a caching mode is determined (step 301).

Here, if it is determined that the entire caching mode is set (the entire step 301), a predetermined caching designation flag is set to caching designation (step 305).
.

On the other hand, if it is determined that it is selective caching mode (
Stellar 1301 is selected), and then it is determined whether the data requires caching (step 302).

This determination is performed, for example, by storing in advance a data address that requires high-speed access in a memory, and comparing this with the data address at which the access request has occurred.

Here, if it is determined that the data requires caching (
Step 302: YES), the above-mentioned flag is set to indicate caching;
), if it is determined that the data does not require caching (step 302 NO), the aforementioned flag is set to no caching specification (step 304).

In this way, the access request with the caching designation is subsequently sent to the external storage control device 4 (step 306).

The above operations are repeated every time an access request occurs.

Next, FIG. 4 is a flowchart schematically showing the structure of the system program of the external storage control device 4.

The external storage control device side is always in a reception standby state (steps 401 and 402>).

In this state, when an access request is received from the main CPU 2 (step 402 YES), it is then determined whether caching is specified based on the content of the caching specification flag attached to the access request (steps 403, 404).

If it is determined here that caching is not specified (no step 404), then the type of access is determined (
Step 405), if this is a write, the data is directly written to the external storage device 5 (step 406), and then the write completion is notified to the main CPU 2 (step 407), if the access type is a read The corresponding data is directly read from the external storage device 5 (step 408), and sent to the main CPU 2 (step 409).

On the other hand, if it is determined that caching has been designated (step 404), normal caching processing is performed thereafter.

That is, it is determined whether or not the corresponding data exists in the cache memory 46 (step 410), and if the data exists in the cache memory, it is determined (step 410 YES).
Then, the access type is determined (step 415).
), if this is a write, the corresponding data is immediately written to the main 1 flash memory 46 (step 416), ! While notifying the main CPU 2 of the completion of loading (step 417
), and if it is a read, the corresponding data is read from the cache memory 46 (step 418), and this is performed in the main CPLJ.
(step 419).

On the other hand, if the corresponding data does not exist in the cache memory (step 410 NO), the cache memory 46
If there is no free space in the cache memory, the oldest data is erased from the cache memory by referring to the usage status of the cache memory (Step 412), and then the corresponding data is transferred to the external storage device 5.
Step 413 > to read from and load into the cache memory 46, and update the cache memory usage status (
Step 414).

In this way, once the data access is completed, in this embodiment, the cache hit rate is calculated (step 42), with particular reference to the cache memory utilization status mentioned above.
0) and access statistics processing (step 421).

Calculating the cache hit rate is to calculate the number of times data actually existed in the cache memory 46 among access requests that specified caching.
In addition, in access statistics processing, idle time ratio,
The number of accesses, access time (average, maximum, minimum), average transfer size, etc. for each caching target area are determined by statistics.

Next, the cash hit rate and statistical processing results obtained in this manner are stored in a predetermined area of the shared memory 3, and these stored data are read out by the main CPU 2 as appropriate and used as a reference when changing the caching designation.

That is, if the cash hit rate decreases, it is reviewed whether the cause is unnecessary caching processing, and based on the result of this review, settings are changed to specify no caching for unnecessary caching.

In this way, according to the above-described embodiments, caching processing is not performed immediately simply because an access request is received, but caching processing is performed selectively based on the contents of the caching designation flag attached to the access request. Therefore, by appropriately setting caching specifications on the main CPU side, when applied to a computer system running on a multitasking or real-time multitasking operating system, when a large program is loaded from disk memory and executed, Alternatively, even when a program that continuously accesses the main data is operated, the decrease in the hit rate can be suppressed to the necessary minimum, and high-speed access can be maintained as a whole.

In addition, in the above embodiment, each time the caching process is completed, the cache hit rate is calculated and the access statistics are processed to check the current system status, and this information is saved in the shared memory 3 and can be used on the main CPU side. Therefore, it is possible to easily specify optimal caching using this data as a reference.

In the above embodiment, the presence or absence of the caching process status is determined based on the caching specification information attached to the access request, but for example, as shown in FIG. The address of the device may be registered in the shared memory 3 by an operation from the main CPU 1, and the presence or absence of a caching process request may be determined by comparing the address related to the access request with these registered addresses.

That is, in FIG. 5, the external storage control device reads the caching target area from the shared memory as an initial process (step 500), and then enters a state of waiting for an access request (steps 501 and 502).

Thereafter, when an access request is received, step 5C
10Y E S >, the quenching target address read in step 501 is compared with the address of the access target data (step 503), and here, the access target data is determined to be data in the caching target area. only if (step 503 YES)
, normal caching processing similar to that shown in FIG. 4 is performed.

According to such a configuration, as long as the address of the external storage device to be cached is initially registered in the shared memory 3, there is no need for any special caching designation operation on the main CPU 2 side, and processing on the main CPU 2 side is simplified. Simplification will be achieved.

[Effects of the Invention] As is clear from the above description, according to the present invention, when this type of external storage control device is applied to a computer system operating on a multitasking or real-time multitasking operating system, a large amount of Even when a program is loaded from disk memory and executed, or when a program that continuously accesses Ohata's data runs, the drop in hit rate is kept to a minimum and the entire system maintains high-speed data access. can do.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of a computer system to which an external storage control device according to the present invention is applied, Fig. 2 is a block diagram showing details of the external storage control device, and Fig. 3 is a block diagram showing the details of the external storage control device. FIG. 4 is a flowchart schematically showing the entire control program executed by the external storage control device, and FIG. 5 shows another embodiment for determining whether or not caching is specified. This is a flowchart. 1... System bus 2... Main CPU 3... Shared memory 4... External storage control device 5... External storage device 46... Cache memory

Claims (1)

[Claims] Caching processing is performed based on caching designation information attached to an access request or based on a comparison result between an address of an external storage device set in advance as a caching target address and an address related to the address request. means for determining the presence or absence of a request; and if the determination indicates that there is a caching processing request, normal caching processing is performed in response to the access request, while if it is determined that there is no caching processing request, the access request is An external storage control device comprising: means for directly performing access processing to an external storage device in response to the above.