JPH05324547A - Data transfer system - Google Patents

Abstract

PURPOSE:To specify a data transfer device which should transfer data by discriminating the priority level of data transfer to a processor. CONSTITUTION:A processor 10 is connected to plural data transfer devices 11 by one data bus 16, and each data transfer device 11 is internally provided with a right transfer circuit 12 which transfers the right of access to the processor to the adjacent data transfer device 11, and this circuit 12 is connected to the right transfer circuit in the adjacent data transfer device by a signal line. The data transfer device 11 monitors whether a data buffer 15 has transferrable data or not by a data flag. When receiving the right of access to the processor, the data transfer device transfers data to the processor if the data buffer 15 has data. If the data buffer does not have data, the right is transferred to the right transfer circuit 12 of the adjacent data transfer device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system in which a plurality of data transfer devices transfer data to a single processor, and to a method for specifying a data transfer device to perform transfer by handshaking between the data transfer devices. It is a thing.

[0002]

2. Description of the Related Art In recent years, when a plurality of data transfer devices transfer data to the same processor, a method of adding a tag to transfer data to specify the transfer destination, and specifying the transfer destination by an address bus. Although various methods such as a method have been devised, there is a method in which a processor performs a handshake with a plurality of data transfer devices to determine a data transfer destination. As an example of such control, Japanese Patent Application Laid-Open No. 2-16655
There is publication No. 1. In this conventional example, the master computer checks whether or not any of the plurality of slave computers is in a data transferable state, and then the slave computer having a high transfer priority and the slave computer having a low priority are transferred. The highest priority slave
While performing data transfer with the processor, determine whether any of the slave processors with other priorities is in a data transfer enabled state, and prioritize data transfer with the slave processor with the higher priority. ing.

[0003]

However, in the above configuration, the master computer performs data transfer with a certain slave processor while communicating with another slave processor by handshake to transfer the data. Since the priority must be calculated all the time, control of data transfer by the master computer frequently occurs, and transfer control is complicated.

Further, the number of slave processors is limited by the handshake means of the master computer, and there is a problem in that the number of slave processors cannot be easily increased.

In view of the above problems, the present invention specifies a data transfer device to be handshaked between the data transfer devices and transfers the data between the processor and the plurality of data transfer devices, and the processor is exempt from the control of the data transfer. The present invention provides a data transfer method. Further, the present invention provides a data transfer method capable of flexibly coping with the expansion of the data transfer devices without being aware of the number of the data transfer devices, even though the present invention is the data transfer between the processor and the plurality of data transfer devices. Is provided.

[0006]

In order to solve the above problems, in the data transfer system of the present invention, the first means is as follows.
A processor, a plurality of data transfer devices connected to each other through the same first data bus as the processor and having a right transfer circuit for transferring the right to access the processor, and each of the data transfer devices. Same second
A plurality of data buffers connected by the data bus, the right transfer circuit in the data transfer device is connected to the right transfer circuit of the adjacent data transfer device in a ring shape via a signal line, The plurality of data buffers notify the data transfer device connected via the second data bus of the presence or absence of data via a data flag, and the data transfer device determines that the data to be transferred to the data buffer. Control is performed such that data is transferred to the processor if there is any data, and if there is no data, the right to access the processor is transferred to the adjacent data transfer device.

As a second means, a processor and a plurality of data transfer devices are provided, and the data transfer device internally compares a register, a counter for counting the number of transfer words, and the values of the register and the counter. A comparator, and a right transfer circuit for transferring the right to access the processor to the adjacent data transfer device,
The processor and the plurality of data transfer devices are connected by the same data bus, the right transfer circuit is connected to the right transfer circuit of the adjacent data transfer device in a ring shape via a signal line, The data transfer device performs control such that after transferring a preset number of words to the processor, the right to access the processor is transferred to an adjacent data transfer device.

[0008]

According to the present invention, because of the above-described structure, the data transfer priority is determined by handshaking between the data transfers, so that the processor can reduce the control of the data transfer. Further, since the data transfer system according to the present invention does not depend on the number of data transfer devices, it is possible to flexibly deal with the expansion of the data transfer devices, and the data transfer system using this system is highly expandable.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer system according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram of a data transfer system in a first embodiment of the present invention.

In FIG. 1, the processor 10 is connected to a plurality of data transfer devices 11 via the same data bus (first data bus) 16, and each data transfer device 11 is internally connected to the processor. It has a right transfer circuit 12 for transferring the right of access to an adjacent data transfer device, and the right transfer circuit 12 is connected to the right transfer circuit 12 inside the adjacent data transfer device via a signal line 13.
Further, each data transfer device monitors whether or not data exists in the data buffer 15 by the data flag 14. Further, each data transfer device 11 has the same data bus (second data bus) 1 as the plurality of data buffers 15.
It is connected via 7.

The operation of the data transfer system configured as described above will be described below with reference to FIG.

The data transfer device 11 includes a data buffer 15
Data flag 1 indicating whether or not there is data that can be transferred to
Are monitored by 4. When the data transfer device 11 receives the right to access the processor 10, if there is data in the data buffer 15, the data transfer device 11 transfers the data to the processor 10. When there is no data in the data buffer 15, the right is transferred to the right transfer circuit 12 of the adjacent data transfer device 11.

As described above, according to the present embodiment, the right to access the processor is handshaked by the data transfer apparatuses 11 to transfer the right, and the data transfer apparatus 11 having a high priority transfers the data to the processor 10. be able to. Further, according to the present embodiment, when the request for data transfer is low, the data transfer devices always transfer rights to each other,
Waiting for a data transfer request,
As soon as a data transfer request is made, the data transfer is ready.

In the present embodiment, the handshake between the data transfer devices is performed between the adjacent data transfer devices, but the connection form may be linear or ring-shaped, and the right is transferred in the direction in which the right is received. However, it may be in the opposite direction to the direction in which the right was received.

(Embodiment 2) FIG. 2 is a block diagram of a data transfer system in a second embodiment of the present invention. The present embodiment differs from the first embodiment in that the control for transferring the right is performed after the preset number of words is transferred.

In FIG. 2, the processor 20 is connected to the plurality of data transfer devices 21 via the same data bus 27, and each data transfer device 21 internally has the right to access the processor 20. A right delegation circuit for delegating to the data transfer device 22, a register 23,
A counter 24 for counting the number of transfer words and the register 2
Comparator 25 for comparing the value of counter 3 with the value of 3
The right transfer circuit 22 is connected to the right transfer circuit 22 inside the adjacent data transfer device via the signal line 26.

The operation of the data transfer system configured as described above will be described below with reference to FIG.

First, the register 23 in the data transfer device 21
In advance, the number of transfer words is set. Upon receiving the right, the data transfer device 21 transfers the data to the processor 20 and counts the number of accessed words. The transfer is performed while the value of the counter 24 is smaller than the value of the register 23. When the values of the counter and the register are equal, the comparator 25 operates and the right transfer circuit 22 transfers the right to the adjacent data transfer device.

[0020]

As described above, in the present invention, the data transfer device transfers the data to the processor when there is data to be transferred in the data buffer, and the adjacent data transfer device when there is no data. By delegating the right to access the processor to the processor, the data transfer device having a high priority can always hold the right to access the processor. Further, since the data transfer device to be accessed is specified by the handshake between the data transfer devices, the processor is exempted from the control of the data transfer. In addition, since the data transfer method according to the present invention does not depend on the number of data transfer devices, it is possible to flexibly deal with the addition of data transfer devices and the system expandability is large.

Further, according to the first embodiment, when the data transfer request is low, the data transfer devices always transfer the right and wait for the data transfer request to occur. Can be scanned at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data transfer system according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a data transfer system according to a second embodiment of the present invention.

[Description of Reference Signs] 10 processor 11 data transfer device 12 right delegation circuit 14 data flag 15 data buffer

Claims (2)

[Claims] 1. A processor, a plurality of data transfer devices connected to each other through the same first data bus as the processor and having a right transfer circuit for transferring the right to access the processor, and each of the plurality of data transfer devices. A data transfer device and a plurality of data buffers each connected to the same second data bus, wherein the right transfer circuit in the data transfer device is connected to the right transfer circuit of the adjacent data transfer device via a signal line. Are connected in a ring shape, and the plurality of data buffers notify the data transfer device connected by the second data bus of the presence / absence of data via a data flag. When there is data to be transferred in the data buffer, the data is transferred to the processor, and when there is no data, the data is transferred to the adjacent data transfer device. A data transfer method, wherein the right to access the processor is transferred. 2. A processor and a plurality of data transfer devices, wherein the data transfer device internally has a register, a counter for counting the number of transfer words, a comparator for comparing the values of the register and the counter, and the processor. To the adjacent data transfer device, the processor and the plurality of data transfer devices are connected by the same data bus, and the right transfer circuit is adjacent to the data transfer device. The data transfer device is connected to the right transfer circuit in a ring shape via a signal line, and the data transfer device transfers a preset number of words to the processor, and then the adjacent data transfer device is connected to the processor. A data transfer method characterized by delegating the right to access the data.