JPH05324306A - Electronic equipment - Google Patents

Abstract

PURPOSE:To switch the arbitrary memory area of an original ROM to the one of an additional ROM by using switch information representing which memory area of the original ROM should be switched to the one of the additional ROM. CONSTITUTION:A ROM area switching device is comprised of a microprocessor unit 5, a latch circuit 7, a ROM selection logic circuit 9, and an address switching logic circuit 11, and the original ROM 1 and the additional ROM 3 are packaged on it. An identification code (switch information) to discriminate an area rewritten to the one of the additional ROM 3 is written on the additional ROM 3 in advance. In other words, the identification code representing which memory area of the ROM 1 is switched to the one of the additional ROM 3 is inputted by the ROM selection logic circuit 9. Thence, the arbitrary memory area of the ROM 1 is switched to the memory area of the additional ROM 3 by the ROM selection logic circuit 9 and the address switching logic circuit 11 based on an inputted identification code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device capable of switching an arbitrary storage area of a mounted fixed storage element to an additional fixed storage element mounted separately.

[0002]

2. Description of the Related Art In an electronic device, for example, a microprocessor application device, an original ROM as a fixed storage element in the form of a mask ROM is mounted. A certain program is stored in this original ROM, but there is a bug (defective point in the program) in that program.
May be discovered. The mask ROM means that data is written in advance in a factory to make a non-rewritable fixed storage element. In such a case, the original ROM is replaced with an additional ROM as an additional fixed storage element that stores a normal program.

[0003]

According to the above conventional structure, there are the following problems. That is, the original RO
If the capacity of M is relatively small, there is little cost problem even if it is replaced with a new mask ROM, but if the capacity of the original ROM becomes large, the cost for newly making a mask ROM is large. Therefore, there is a problem that the cost increases. On the other hand, it is conceivable to divide the storage area (address space) of the original ROM into a plurality of blocks and replace the blocks individually or in combination with the additional ROM. That is, only an arbitrary storage area (block) including a portion in which a bug is found is switched, and other normal portions are used as they are. However, such switching is impossible in the conventional electronic equipment.

The present invention has been made on the basis of such a point, and an object of the present invention is to provide an electronic device capable of switching an arbitrary storage area of an original ROM to an additional ROM.

[0005]

In order to achieve the above object, an electronic device according to the present invention is an electronic device in which a fixed storage element is mounted and an additional fixed storage element can be mounted. Switching information input means for inputting switching information indicating whether to switch to the additional fixed storage element, and any storage area of the fixed storage element is switched to the additional fixed storage element based on the switching information input by the switching information input means. And storage area switching means. At that time, it is conceivable to store the switching information in the additional fixed storage element in advance and read it by the switching information reading means. Further, it is possible to provide a switch for inputting the switching information and input the switching information via the switch.

[0006]

First, switching information indicating which storage area of the fixed storage element is switched to the additional fixed storage element is input by the switching information input means. Next, the storage area switching means switches an arbitrary storage area of the fixed storage element to the additional fixed storage element based on the switching information input by the switching information input means. As a method of inputting the switching information by the switching information input means, first, it is considered that the switching information is previously stored in the additional fixed storage element and is read by the switching information reading means which is a software means. Be done. Further, it is conceivable to provide a switch as a hardware means and input the switching information through the switch. In this case, it is not necessary to store the switching information in the additional fixed storage element in advance.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
An example will be described. First, FIG. 1 shows a memory map of the original ROM 1 as a fixed storage element. The storage area of the original ROM 1 is "0000H to 3FFFF.
The address space of "H". Further, the original ROM 1 has a ROM switching setting processing program area, and the ROM switching setting processing program area is the ROM.
A switching setting processing program is stored. Further, in the case of this embodiment, the area of the additional ROM 3 is divided into a plurality of blocks, and each block is switched to a plurality of areas in the original ROM 1 corresponding to its capacity. In this embodiment, in order to facilitate the explanation,
The additional ROM 3 of 64 Kbytes is divided into two storage areas of 32 Kbytes each, and one block A among them is divided into storage areas "18000H to 18000H in the original ROM 1".
It is assumed that the other block B is added to any storage area “40000H to 47FFFH” while being replaced with “FFFFH”. Further, for the sake of explanation, the storage area of the original ROM 1 is divided into 32 Kbytes, and each block is shown by areas (1) to (10).

The ROM area switching device shown in the block diagram of FIG. 2 realizes the switching of the ROM area. The ROM area switching device comprises a microprocessor unit (MPU) 5, a latch circuit 7, a ROM selection logic circuit 9, an address switching logic circuit 11 and the like. Also, the original ROM 1 and additional ROM 3 already mentioned
And have been implemented. The additional ROM 3 has the additional R
An identification code (switching information) that can identify the area to be replaced with the OM3 is written in advance. This identification code is, for example, “FF
It is preferably a code excluding "H". This is EP
The ROM is generally "FFH" when unwritten, and this is to prevent malfunction due to incorrect insertion of the unwritten ROM. Further, when the additional ROM 3 is not mounted, an indeterminate value is read due to the stray capacitance of the circuit, etc. Therefore, it is desirable to use an identification code that is not the same as these values. In the present embodiment, the bus line is pulled up via the high resistance so that it becomes "FFH" when the additional ROM 3 is not mounted.

In the case of this embodiment, the ROM selection logic circuit 9 and the address switching logic circuit 11 shown in FIG.
For example, the configuration is as shown in FIG. First, there are comparison circuits 13 and 15, and signals S17 and S19 are input from the decoders 17 and 19 to the comparison circuits 13 and 15, respectively. 3 bits data based on the identification code stored in the additional ROM 3 is input to the decoders 17 and 19 via the ROM selection control signal 35 which is the output of the latch circuit 7 shown in FIG. 3bi above
The t data is as shown in FIG. That is,
In the memory map shown in Fig. 1, the original RO
When the storage area of M1 is divided into 32 Kbytes, it is divided into the areas (1) to (10) as described above. Each of the areas (1) to (10) is specified by 3-bit data. In the case of this embodiment, the areas
In order to replace the block A of the additional ROM3 in (4),
The 3-bit data “011” for specifying the area (4) is input to the decoder 17. 3 from the decoder 17
A signal S17 corresponding to the bit data is output. In this case, as shown in FIG. 4, the signal S17 only "Y _3" is the signal of the logic "0".

The same 3-bit data is also input to the decoder 19, and in the case of this embodiment, the block B of the additional ROM 3 is added to the area (9) as shown in FIG. 3-bit data "1" that specifies the area (9)
11 ”is input to the decoder 19. A signal S19 corresponding to the 3-bit data is output from the decoder 17. In this case, as shown in FIG.
"Y ₇ " is a signal of logic "0".

On the other hand, the signal S21 is input to the comparison circuits 13 and 15 via the decoder 21. The decoder 21 has a system control address bus 37 shown in FIG.
From this, 4 bit data from A _{15 to} A ₁₈ is input,
A signal for specifying the storage areas (1) to (10) of the original ROM 1 is input. The other address signals A _{0 to} A ₁₄ are directly input to the additional ROM 3. Then, in the comparison circuit 13, the signal S17 from the decoder 17 side and the signal S21 from the decoder 21 side are compared, and if they match, a signal S13 of logic "1" is output, and the AND gate 14 arranged in the subsequent stage. A signal arrives at the logic circuit 23 via the
Select 3. Similarly, the comparison circuit 15 also has a decoder 19
Side signal S19 and decoder 21 side signal S21
Are compared, and if they match, the signal S15 of logic "1"
Is output, whereby a signal reaches the logic circuit 23 via the AND gate 16 and selects the additional ROM 3.
The AND gates 14 and 16 are gates for permitting or prohibiting the propagation of the above-mentioned coincidence signal, and are controlled by the output control signal S29.

A logic circuit 25 is arranged, and a part (Y ₈ and Y ₉ ) of the signal S21 from the decoder 21 is input to the logic circuit 25. The logic circuit 25 outputs a signal S25 of logic “1” to the AND circuit 27 when one of these signals is logic “0”. still,
The input / output relationship of the logic circuit 25 is shown in FIG.
There is no possibility that the input is “00”. The AND circuit 27 has a separate output control signal S29.
Is inputted via the inverting circuit 31 and both signals become logic "1", a signal S27 of logic "1" is outputted to the logic circuit 23 described later. In other words, in the initial state of the step, the additional ROM 3 is original R
It is necessary to add to the additional areas (9) and (10) of the OM1 and read the identification code stored therein, and at that time, the logic circuit 25 and the AND circuit 27 function to make the additional ROM 3 operate. It is something to choose.

The logic circuit 23 includes an AND gate 14,
When at least one of the output signals of the AND gate 16 and the AND circuit 27 becomes the logic "1", the signal S23 of the logic "0" is output. Logic circuit 2
When the signal S23 of logic "0" is output from 3, the additional R
The chip select signal of OM3 will be turned on,
The chip select signal of the original ROM 1 is turned off by the action of the inverting circuit 33, and eventually the additional ROM 3 is selected. That is, the fact that the signals from the AND gate 14, AND gate 16, and AND circuit 27 become logic "1" means that the storage area is replaced or added, or the storage area is added at the initial stage. This is because the additional ROM 3 needs to be selected.

A logic circuit 51 is arranged, and the output control signal S29 and a part (Y ₉ ) of the signal S21 from the decoder 21 are input to the logic circuit 51.
When both of these signals are logic "0", the signal S51 of logic "1" is input to the OR circuit 53. In addition to the above signals, the OR gate 53 has an AND gate 16
The signal S16 from is also input. The OR circuit 53 is an additional ROM when either of these signals becomes a logic "1".
The address signal A _{15 of} 3 is set to logic "0". That is, by this, the block B of the additional ROM 3 is selected.

The operation will be described based on the above configuration.
In this embodiment, a printer is used as an example of the electronic device for description. First, as shown in the flowchart of FIG. 6, when starting, the initial setting (sequence S1) starts. In this sequence 1, "RAM clear", "R
OM area setting "," initial setting of I / O port and the like "and the like are performed. When these initial settings are completed, the presence or absence of print data is determined (sequence S2). When there is print data, the process shifts to printing as it is (sequence S).
3). If there is no print data, the presence / absence of print data is repeatedly determined.

Next, the "ROM area setting" among the above-mentioned initial settings will be described with reference to the flowchart of FIG. When the process is started, first, the identification code of the additional ROM 3 is read (sequence S4).
As a precondition for reading this identification code, it is necessary to arrange the additional ROM 3 in the storage area “40000H to 4FFFFH” (additional area) of the original ROM 1 as shown by the broken line in FIG. This is the RO shown in FIG.
When the above-mentioned additional area is added by the M logic selection circuit 9, the additional
It is realized by chip-selecting OM3.

Next, the presence or absence of the additional ROM 3 is determined depending on whether the read data is not "FFH" (sequence S5). If there is no additional ROM 3, the storage area is set to "0".
0000H to 3FFFFH, output control signal S
29 is set to "0" (sequence S6), and the process ends. As such an example, for example, there is a case where the additional ROM 3 is not mounted, and in that case, “FFH” is read as described above. Further, even when the additional ROM 3 for which data writing has not been performed is mounted, "FFH" is read out, and it is substantially treated as non-mounting. Next, the additional ROM 3 determines whether to add or replace the memory (sequence S7). That is, it is determined whether or not both blocks A and B are added (sequence S8), and when both blocks A and B are added, the storage area is set to "00000H to 4FFFFH" and the output control signal S29 is set to "0". Then (Sequence S
9) and ends. On the other hand, if neither block A nor B is added, it is determined whether only block B is added (sequence S10). When only block B is added, the chip select selection control data is output to the latch circuit 7 (sequence S11) and the memory area is set to "000".
00H to 47FFFH, output control signal S29
Is set to "0" (sequence S12), and the process ends. On the other hand, when only the block B is not added, in other words, when both the blocks A and B are replaced, the chip select selection control data is output to the latch circuit 7 (sequence S13) and the memory area is set to "00000H".
Through 3FFFFH, the output control signal S29 is set to "0" (sequence S14), and the process ends.

The above operation will be described as an operation of the comparison circuits 13 and 15. First, due to the operation of the comparison circuit 13, the chip select signal of the additional ROM 3 is turned on in the storage area "18000H to 20000H".
M3 is selected. Also, by the action of the comparison circuit 15,
When the storage area is "40000H to 48000H",
When the chip select signal of the additional ROM3 is turned on, additional R
OM3 is selected. Then, the addresses are switched accordingly. In addition, in this way, additional ROM3
When dividing into a plurality of blocks, as the number of divisions increases, the number of comparison circuits shown in FIG. 3 also increases accordingly.

According to this embodiment, the following effects can be obtained. First, the storage area of the original ROM 1 is not switched for each ROM, but the original RO
It is possible to divide the storage area of M1 into a plurality of blocks and perform the processing in block units. Therefore, even when the capacity of the original ROM 1 is large, the storage area can be switched at a relatively low cost. Further, since the storage area is switched by a software means rather than a hardware means such as a switch, a switching connector, a jumper wire, etc., no complicated work is required and a connection error or There is no contact failure, and the reliability can be greatly improved.
Further, since the switching of the storage area of the ROM is facilitated, it is possible to easily change the microprocessor application device having a certain specification to another specification. Further, the additional ROM 3 is divided into a plurality of blocks, and the storage area can be switched in block units.

Which storage area of the original ROM is switched to the additional ROM 3 is arbitrary. For example, as shown in FIG. 8, the storage areas (2) and (3) of the original ROM 1 are changed.
May be switched to the additional ROM 3. Other,
The content of the switching information stored in the additional ROM 3 may be set arbitrarily.

Next, a second embodiment of the present invention will be described with reference to FIG. In the case of this embodiment, a dip (DIP, dual in-line package) switch 8 is mounted instead of the latch circuit 7 in the first embodiment,
The storage area is switched by a hardware means. That is, the switching information is input through the DIP switch 8 to cause the ROM selection logic circuit 9 and the address switching logic circuit 11 to function. In this case,
It is not necessary to store the switching information in the additional ROM 3 in advance. Therefore, although some work is required, it is possible to obtain substantially the same effects as in the case of the first embodiment.

Next, a third embodiment will be described with reference to FIGS. In the case of the first and second embodiments,
A ROM switching program area is provided in the storage area of the original ROM 1, and R is stored in this ROM switching program area.
The OM switching program is stored. In this case, the ROM switching program area is a non-switchable area. On the other hand, in the case of the present embodiment, the ROM switching program area is provided in the storage area of the additional ROM 3 to store the ROM switching program therein, and the ROM switching program is switched accordingly.

First, as shown in FIG. 10, the additional ROM 3
Memory area is divided into a block A and a block B, and a ROM switching program area is provided in the block B to store the ROM therein.
Store the switching program. This is switched for each block as in the case of the third embodiment. The switching procedure will be described below with reference to the flowchart of FIG. First, when the process is started, the presence or absence of the identification code is determined (sequence S12). If there is no identification code, the process ends. If the identification code is present, it is determined whether or not the memory is replaced (sequence S13). When it is not the replacement of the memory, the process ends as it is. On the other hand, when the memory is replaced, it is determined whether or not the ROM switching program area is included (sequences S14 and S15).

When the ROM switching program area is included, as shown in FIG. 2, the ROM selection control signal 35 output from the storage element 7 is controlled and the address switching output from the ROM selection logic circuit 9 is performed. By controlling the control signal 43, the storage area "08000H to 0FFFFH"
Is replaced with the block B of the additional ROM 3 (sequence S
16). When the replacement is completed, the storage area "0
Jump to the ROM switching program in "8000H to 0FFFFH" (sequence S17). After that, this R
The process proceeds according to the OM switching program, and the storage area “00000H to 0FFFFH” is added to the ROM 3
To block A (sequence S18). On the other hand, if the ROM switching program area is not included in the sequence S15, the process proceeds to the sequence S19, the area designated by the identification code is replaced, and the processing ends.

Therefore, also in the case of this embodiment, the same effect as in the case of the first and second embodiments can be obtained. In this embodiment, it is needless to say that it is necessary to provide the ROM switching program area in the block B to be replaced first.

The present invention is not limited to the above embodiments. First, the original R shown in each of the above embodiments
The capacities of the OM1 and the additional ROM 3 are all examples, and can be similarly applied to arbitrary capacities. Further, although the printer has been described as an example of the electronic device, the invention can be applied to various other electronic devices. In addition, when the additional ROM 3 is divided into a plurality of blocks and is switched, the number of divisions, the capacity of each block, and the like are also arbitrary.

[0027]

As described in detail above, according to the electronic device of the present invention, an arbitrary storage area of the fixed storage element can be switched to the additional fixed storage element. Therefore, even if the fixed storage element has a large capacity, a comparison is made. It has become possible to switch storage areas at an extremely low cost.

[Brief description of drawings]

FIG. 1 is a diagram showing an original RO according to a first embodiment of the present invention.
It is a figure which shows the memory map of M.

FIG. 2 is a block diagram showing the configuration of a ROM area switching device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a first embodiment of the present invention and is a diagram showing a part of a configuration of a ROM area switching device.

FIG. 4 is a diagram showing the first embodiment of the present invention and is a diagram for explaining the relationship between 3-bit data input to the decoders 17 and 19 shown in FIG. 7 and a storage area.

FIG. 5 is a diagram for explaining the input / output of the logic circuit 25 in the diagram showing the first embodiment of the present invention.

FIG. 6 is a flow chart showing the operation of the first embodiment of the present invention.

FIG. 7 is a flow chart showing the operation of the first embodiment of the present invention.

FIG. 8 is a diagram showing an original RO according to the first embodiment of the present invention.
It is a figure which shows the memory map of M.

FIG. 9 is a diagram showing a second embodiment of the present invention and is a diagram showing a part of the configuration of the ROM area switching device.

FIG. 10 is a diagram showing an original R according to a third embodiment of the present invention.
It is a figure which shows the memory map of OM.

FIG. 11 is a flow chart showing the operation of the third embodiment of the present invention.

[Explanation of symbols]

 1 Original ROM (fixed storage element) 3 Additional ROM (additional fixed storage element) 5 Microprocessor unit 7 Latch circuit 8 DIP switch 9 ROM selection logic circuit 11 Address switching logic circuit

Claims (3)

[Claims] 1. In an electronic device in which a fixed storage element is mounted and an additional fixed storage element can be mounted, switching information for inputting switching information indicating which storage area of the fixed storage element is switched to the additional fixed storage element. An electronic device comprising: an input means; and a storage area switching means for switching an arbitrary storage area of a fixed storage element to an additional fixed storage element based on the switching information input by the switching information input means. 2. The electronic device according to claim 1, wherein switching information is stored in advance in the additional fixed storage element, and the switching information is read by the switching information reading means. 3. The electronic device according to claim 1, wherein a switch for inputting switching information is provided, and the switching information is input via the switch.