JP2007122796A - Nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory capable of achieving cost reduction by enhancing simplification of a circuit constitution and miniaturization of a circuit scale and also capable of attaining stabilization of the operation, when an OTP function, etc., are obtained for a part of memory areas of the nonvolatile memory. <P>SOLUTION: A memory cell array 1, assigns nonvolatile memory cells in a part thereof to an initial data storage area 12. A writing data control circuit 3 checks whether an input address coincides with an address of the initial data storage area 12 in the memory cell array 1, and when both of them are not coincident, input data D0-D7 are output, while preset optional fixed data are output when they are coincident. A data input circuit 4 writes the data into the nonvolatile memory cell of the memory cell array 1 to be selected by an address decoder 2, and at this time, the input data D0-D7 from the writing data control circuit 3 or the aforementioned fixed data are written into the nonvolatile memory cell. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention is a non-volatile memory such as an EEPROM (Electrically Erasable Programmable ROM), which restricts free rewriting of data in a part of the memory area, and can be written only once OTP (One Time PROM) The present invention relates to a nonvolatile memory that realizes the above.

Conventionally, when an OTP function is given to a nonvolatile memory such as an EEPROM, the following method has been adopted.
(1) In a non-volatile memory such as an EEPROM, an OTP function is mounted in addition to the non-volatile memory (hereinafter referred to as the first prior art).
(2) In a nonvolatile memory such as an EEPROM, for example, an external terminal for realizing the OTP function is provided, and an external component such as a jumper line is connected to the external terminal to realize the OTP function (hereinafter referred to as the OTP function). The second prior art).
(3) By using the technique described in Patent Document 1, the OTP function has been realized as follows (hereinafter referred to as the third conventional technique).

a) In the third prior art, a part of the memory is allocated to the OTP area, and “
“Rewriteability identification flag” is set.
b) At the stage before writing to the memory such as when the power is turned on, the setting contents of the “rewriteability identification flag” are loaded from the OTP area and stored in the register. When writing to the memory, whether or not to rewrite the OTP area on the memory is determined based on the value (content) of the data stored in the register.

c) The “rewriteability identification flag” is present in the OTP area. In addition, when writing non-permitted data is written to the “rewritability identification flag”, it becomes impossible to rewrite the OTP area as described above, so the “rewritability identification flag” itself cannot be rewritten,
As a result, the OTP function is realized.
Japanese Patent Laid-Open No. 10-106275

However, since the first conventional technique is equipped with the OTP function in addition to the nonvolatile memory, there is a problem in that the chip area increases and extra manufacturing costs are required.
In addition, in the second prior art, it is necessary to provide a dedicated external terminal in order to realize the OTP function, and it is necessary to add an external component. is there.

Furthermore, in the third prior art, the logic circuit or the like for realizing the above OTP function has a complicated configuration and a large circuit scale. Further, since the memory is loaded during an unstable operation period such as when the power is turned on, there is a problem that a malfunction may occur.
Accordingly, in view of the above points, an object of the present invention is to reduce the cost by simplifying the circuit configuration and reducing the circuit scale when realizing the OTP function or the like for a part of the memory area of the nonvolatile memory. It is an object of the present invention to provide a non-volatile memory that can realize the stabilization and can stabilize the operation.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
In other words, according to a first aspect of the present invention, there is provided a nonvolatile memory having a memory cell array in which a plurality of electrically rewritable nonvolatile memory cells are arranged. The initial data is assigned to the initial data storage area to which data is written in advance, and it is determined whether or not the writing area input for writing data matches the initial data storage area. Data writing means is provided for writing input data to the writing area, and writing fixed data set in advance to the initial data storage area when they match.

In a second aspect based on the first aspect, the data writing means determines whether or not the input address matches the address of the initial data storage area, and outputs a match signal if they match. An address comparison circuit that outputs a mismatch signal when the two do not match, and an external input data when a mismatch signal is output from the address comparison circuit, and a match signal from the address comparison circuit A data selection output circuit for selectively outputting fixed data set in advance, and when the input data is output from the data selection output circuit, the input data is specified by an input address. When the fixed data is output from the data selection output circuit, the fixed data is written to the initial data. Having a data input circuit for writing in the nonvolatile memory cell of 憶領 zone, the.

According to a third invention, in the first or second invention, the contents of arbitrary initial data written in advance in the initial data storage area and the fixed data set in advance corresponding to the initial data are different. I made it.
According to a fourth aspect of the present invention, in the first or second aspect of the present invention, any initial data written in advance in the initial data storage area and the fixed data set in advance corresponding to the initial data have the same contents It was made to become.

According to a fifth invention, in the first or second invention, the initial data storage area is divided into a first storage area and a second storage area, and an arbitrary initial written in the first storage area in advance The contents of the data and the fixed data set in advance corresponding to the initial data are made different from each other, and arbitrary initial data written in advance in the second storage area and set in advance corresponding to the initial data The contents are the same as the fixed data.

According to the present invention having such a configuration, when the OTP function and the ROM function are realized for a part of the memory area of the nonvolatile memory, the circuit configuration is simplified and the circuit scale is reduced to reduce the cost. Can be realized and the operation can be stabilized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
A configuration of a nonvolatile memory according to an embodiment of the present invention will be described with reference to FIG.
The nonvolatile memory according to this embodiment is applied to, for example, an EEPROM. As shown in FIG. 1, the memory cell array 1, the address decoder 2, the write data control circuit 3, the data input circuit 4, the data And at least an output circuit 5.

The memory cell array 1 includes a plurality of nonvolatile memory cells (electrically rewritable data)
(Not shown) are arranged in a matrix. Each nonvolatile memory cell has 1
Bit data can be stored.
The memory cell array 1 has addresses 1 to n as shown in FIG. 2, and for example, 8-bit data D0 to D7 can be read from and written to the nonvolatile memory cells at the respective addresses. Therefore, one block in FIG. 2 corresponds to a nonvolatile memory cell of the memory cell array 1.

The memory cell array 1 assigns addresses 1 to (n−1) among the storage areas to the normal storage area 11 and assigns the remaining n addresses to the initial data storage area 12.
The normal storage area 11 is an area where the user can write arbitrary data at any time. The initial data storage area 12 is an area in which arbitrary initial data is written in advance. The initial data is written, for example, when the wafer is in the middle of the manufacturing process and before being encapsulated by the mould.

The initial data storage area 12 includes an OTP area 12a for realizing the OTP function, a ROM
A ROM area 12b for realizing the function is configured or divided.
The address decoder 2 receives an address input signal and selects (specifies) a nonvolatile memory cell in the memory cell array 1 corresponding to the address.
The write data control circuit 3 compares whether or not the input address matches the address of the initial data storage area 12 of the memory cell array 1, and if the two do not match, outputs the input data D0 to D7, If the two match, arbitrary fixed data set in advance is output.

The data input circuit 4 writes data to the non-volatile memory cells of the memory cell array 1 selected by the address decoder 2, and at this time, external input data D0 to D7 output from the write data control circuit 3 or Write arbitrary fixed data set in advance internally.
The data output circuit 5 reads 8-bit data D0 to D7 written in the nonvolatile memory cell at the designated address of the memory cell array 1 selected by the address decoder 2 (FIG. 2).
reference).

Here, in this embodiment, arbitrary initial data written in advance in the OTP area 12a in FIG. 2 and fixed data preset in the write data control circuit 3 corresponding to this initial data are made to have different contents. ing.
Also, the arbitrary initial data written in advance in the ROM area 12b of FIG. 2 and the fixed data preset in the write data control circuit 3 corresponding to the initial data have the same contents.

Next, a specific configuration of the write data control circuit 3 shown in FIG. 1 will be described with reference to FIG.
As shown in FIG. 3, the write data control circuit 3 includes an address comparison circuit 31 and data selection output circuits 32-0 to 32-7.
The address comparison circuit 31 has an input address of the initial data storage area 1 of the memory cell array 1.
It is determined whether or not the address n, which is the address of 2, matches, and if both match, a match signal is output, and if both do not match, a mismatch signal is output.

The data selection output circuits 32-0 to 32-7 output the input data D0 to D7 from the outside when the mismatch signal is output from the address comparison circuit 31, and the match signal is output from the address comparison circuit 31. In some cases, fixed data that is fixed in advance is selectively output.
For this reason, the data selection output circuits 32-0 to 32-7 receive the input data D0 to D at the input terminal B.
D7 is input, and fixed data is input to the input terminal A, and one of the two input data is used as an output signal (selection signal) from the address comparison circuit 31 input to the selection terminal S. It is designed to output selectively according to.

Here, as shown in FIG. 2, arbitrary write fixed data input to the input terminal A can be set to data “1” or “0” by pulling up or pulling down the input terminal A, for example. It has become.
In FIG. 3, the configuration of the memory cell array 1 and the address decoder 2 excluding the write data control circuit 3 is the same as the configuration of FIG.

Next, an operation example of the embodiment having such a configuration will be described with reference to the drawings.
In this embodiment, as shown in FIG. 2 in the initial data storage area 12 of the memory cell array 1, for example, “0100” is written in advance as the initial data D0 to D3 in the OTP area 12a. Corresponding to this, as shown in FIG. 3, the data selection output circuit 32-0
To fixed data to be input to 32-3, "1", "0", "1",
It is assumed that “1” is set in advance. Therefore, initial data and fixed data are
It is a different value.

On the other hand, in the ROM area 12b of FIG. 2, for example, “1010” as the initial data D4 to D8.
Is written in advance. Correspondingly, the data selection output circuit 32-4
To 32-8 as fixed data, "1", "0", "1",
It is assumed that “0” is set in advance. Therefore, the initial data and the fixed data have the same value.

A case where data is written to a desired address in the memory cell array 1 under such settings will be described.
First, the address comparison circuit 31 determines whether or not the input address matches the address n which is the address of the initial data storage area 12 of the memory cell array 1, and outputs a match signal if both match, If they do not match, a mismatch signal is output.

The data selection output circuits 32-0 to 32-7 output external input data D0 to D7 to the data input circuit 4 when a mismatch signal is output from the address comparison circuit 31. The data input circuit 4 writes the input data D0 to D7 to the nonvolatile memory cells of the memory cell array 1 selected by the address decoder 2.
On the other hand, when the coincidence signal is output from the address comparison circuit 31, the data selection output circuits 32-0 to 32-7 output each fixed data set to the input terminal A to the data input circuit 4. To do. The data input circuit 4 writes the fixed data as data D0 to D7 in the initial data storage area 12 selected by the address decoder 2 (see FIG. 2).
.

Here, as described above, in the OTP area 12a, for example, "initial data D0 to D3"
"0100" is written in advance, and corresponding to this, as fixed data inputted to the selection output circuits 32-0 to 32-3, "1", "0", "1", "1", which are different from the initial data D0 to D3. 1
"Is set in advance.
On the other hand, for example, “1010” is written in advance as the initial data D4 to D8 in the ROM area 12b, and corresponding to this, the initial data D4 as fixed data input to the selection output circuits 32-4 to 32-8. “1”, “0”, “1”, and “0”, which are the same as those of .about.D8, are preset.

For this reason, in the OTP area 12a, the initial data “0100” written in advance can be rewritten only once with the fixed data “1011” set differently. Thereafter, even if the OTP area 12a is rewritten to external input data, the OTP area 12a is rewritten to the fixed data and has an OTP function.
On the other hand, the ROM area 12b stores the initial data “101” written in advance at the time of rewriting.
“0” is the same as that and is rewritten to the preset fixed data “1010”.
Therefore, even if the ROM area 12b is rewritten to external input data, the ROM area 12b is rewritten with the same data as the contents of the initial data and has a ROM function.

Next, a case where data is read from a desired address in the memory cell array 1 will be described.
In this case, the address decoder 2 receives the address input signal and selects a nonvolatile memory cell in the memory cell array 1. Then, the data output circuit 5 reads 8-bit data D0 to D7 written in the nonvolatile memory cell of the memory cell array 1 selected by the address decoder 2 (see FIG. 2).

As described above, according to this embodiment, when the OTP function and the ROM function are realized for a part of the memory cell array (memory area) of the nonvolatile memory, the circuit configuration is simplified and the circuit scale is reduced. As a result, the cost can be reduced and the operation can be stabilized.
Next, application examples of the embodiment according to the present invention will be described.

In this embodiment, as described above, initial data is written in advance in the OTP area 12a, and corresponding fixed data different from the initial data is preset in the selection output circuits 32-0 to 32-3. I was able to do it.
Therefore, the embodiment having such a function is applied to an electronic apparatus that has a first circuit having a high-level function and a second circuit having a low-level function, and that both circuits can be selectively used by switching a switch. The case will be described.

In this case, in the OTP area 12a, data for selecting the first circuit having a high-level function is written in advance as initial data. In response to this, the data selection output circuit 32-
In 0 to 32-3, data for selecting a second circuit having a lower function as fixed data is set in advance.
When data is written and set in this manner, an electronic device processed so as to use the first circuit of the high-level function can use the first circuit by using the initial data written in the OTP area 12a. .

On the other hand, in the electronic device processed so as to use the second circuit having the lower function, the initial data written in the OTP area 12a is rewritten to the set fixed data, and the rewritten fixed data is used. A second circuit can be used.
For this reason, the manufacturer of the electronic device can selectively set the use of the first circuit having the high-level function and the second circuit having the low-level function for the electronic device at the time of shipment. However, if the user of the electronic device is set to use the second circuit having the lower function, the user cannot use the first circuit having the higher function illegally.

In the embodiment according to the present invention, initial data is written in the ROM area 12b in advance, and in response to this, fixed data that is the same as the initial data is stored in advance in the data selection output circuits 32-4 to 32-8. Enabled to set.
Therefore, an embodiment having such a function can be applied to an electronic device that requires a user ID when used by a user.

In this case, a user ID is written in advance in the ROM area 12b as initial data. Correspondingly, the same user ID is previously set as fixed data in the data selection output circuits 32-4 to 32-7.
In this way, when the user uses the electronic device, the user ID input to the electronic device can be used in comparison with the written user ID.

It is a block diagram which shows the schematic structure of embodiment of this invention. It is a figure which illustrates typically the storage area of a memory cell array. It is a block diagram which shows the detailed structure of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Address decoder, 3 ... Write data control circuit, 4 ... Data input circuit, 5 ... Data output circuit, 12 ... Initial data storage area, 12a ..OTP area, 12b ... ROM area, 31 ... address comparison circuit,
32-0 to 32-7 ... Data selection output circuit

Claims (5)

In a nonvolatile memory having a memory cell array in which a plurality of nonvolatile memory cells capable of electrically rewriting data are arranged,
The memory cell array allocates some nonvolatile memory cells to an initial data storage area in which arbitrary initial data is written in advance,
It is determined whether or not a write area that is input to write data matches the initial data storage area. If the two do not match, the input data is written to the write area, while both match. In some cases, the nonvolatile memory includes data writing means for writing fixed data set in advance in the initial data storage area. The data writing means includes
An address comparison circuit that determines whether or not the input address matches the address of the initial data storage area, outputs a match signal if both match, and outputs a mismatch signal if both do not match,
When a mismatch signal is output from the address comparison circuit, input data from the outside,
On the other hand, when a coincidence signal is output from the address comparison circuit, a data selection output circuit that selectively outputs preset fixed data;
When the input data is output from the data selection output circuit, the input data is written to a nonvolatile memory cell specified by an input address, and when the fixed data is output from the data selection output circuit. A data input circuit for writing the fixed data into the nonvolatile memory cell of the initial data storage area;
The nonvolatile memory according to claim 1, further comprising: 3. The initial data written in the initial data storage area in advance and the fixed data set in advance corresponding to the initial data have different contents. Non-volatile memory as described. 2. The arbitrary data written in advance in the initial data storage area and the fixed data set in advance corresponding to the initial data have the same contents. The non-volatile memory according to 2. The initial data storage area is divided into a first storage area and a second storage area;
Arbitrary initial data written in advance in the first storage area and the fixed data set in advance corresponding to the initial data have different contents,
2. The arbitrary initial data written in advance in the second storage area and the fixed data set in advance corresponding to the initial data have the same contents. The non-volatile memory according to 2.

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