JP6035760B2 - Semiconductor memory device and method for controlling semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device using a one-time programmable nonvolatile memory (hereinafter referred to as an OTP memory) and a method for controlling the semiconductor memory device using an OTP memory.

  Conventionally, non-volatile memories in which stored information does not disappear even when the power is turned off are used for various purposes such as storage of control programs for electronic devices and data storage. Non-volatile memories include an OTP memory that can be written only once, and a multi-time programmable nonvolatile memory (hereinafter referred to as an MTP memory) that can erase and rewrite written information.

  Nonvolatile memory systems include mask ROM type, electric fuse type, hot carrier type, antifuse type, CMOS floating gate type, and flash type. Among them, the methods used as OTP memory are generally mask ROM type, electric fuse type, hot carrier type, antifuse type and CMOS floating gate type, and the method used as MTP memory is generally CMOS floating gate. Mold and flash mold. When there is no change after the program or data is determined before manufacturing, a mask ROM type OTP memory with a low manufacturing cost is a preferable choice. In addition, when it is necessary to rewrite frequently, a flash MTP memory is a preferable choice although the manufacturing cost is high. In the case of a flash type, it is generally said that rewriting can be performed 100,000 times or more.

  One of the uses of the nonvolatile memory is to store parameters (data) for adjustment of an analog circuit or the like. For example, there is a case where data for adjustment and correction of variations in analog signal values generated due to manufacturing variations of semiconductor devices or differences in use environments of semiconductor devices is stored. In such an application, it is not necessary to assume that data is frequently erased and written in the memory. Therefore, an alternative is to use an OTP memory with a low manufacturing cost instead of a high manufacturing cost MTP memory. A pseudo MTP memory device may be configured and used. Patent Document 1 describes a pseudo MTP memory configured using a plurality of storage element groups using an OTP memory.

JP 2010-238278 A

  However, in the pseudo MTP memory in Patent Document 1, after data is written to a predetermined address (select address) of a storage element group that stores data, a predetermined value is stored in the storage element group that stores information for designating a select address. There is a problem that the processing at the time of data writing is complicated and takes time, such as writing information, and then generating the read address of the predetermined information and holding it in the select address holding unit.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A semiconductor memory device according to this application example includes a first storage unit that includes a plurality of words, and selects one of the plurality of words by a first address, and for specifying the first address. And a second storage unit that stores first information, and the first address specified from the first information when writing data to the first storage unit is the first storage This is an address for selecting the next word of the first address specified from the first information when reading data from the storage unit, and when the data is written to the first storage unit, substantially the same timing Then, the first information is written in the second storage unit.

  According to this configuration, the first storage unit configured by a plurality of words and one of the words is selected by the first address, and the second information for storing the first information for specifying the first address The first address specified from the first information when data is written to the first storage unit is specified from the first information when reading data from the first storage unit. Is a value for selecting a word next to the word selected by the first address, and the writing of the first information to the second storage unit is substantially the same as the timing of writing the data to the first storage unit By performing at the timing, it is possible to eliminate the time required for writing to the second storage unit after the time required for writing to the first storage unit by setting a new address value, and to increase the processing efficiency. Can do.

  The first information may be the address value of the first storage unit or the second storage unit as it is, or may be a flag or a code. In addition, the first information is stored in the second storage unit, but the first information used when specifying the first address is stored in the second storage unit. It may be either provided from the outside of the semiconductor memory device. For example, when data is written at the time of shipment of the semiconductor memory device, it may be preferable to provide the first information from the outside of the semiconductor memory device using a tester or the like.

[Application Example 2]
In the semiconductor memory device according to the application example described above, it is preferable that the second storage unit can store at least the same number of pieces of the first information as the number of words in the first storage unit.

  According to this configuration, the first information is information indicating that data has been written to a predetermined word in the first storage unit, and the second storage unit has the number of words in the first storage unit. Since the same number or more of the first information can be stored, it is possible to identify all the words in the first storage unit based on the first information stored in the second storage unit.

[Application Example 3]
In the semiconductor memory device according to the application example described above, it is preferable that a data line for the first storage unit and a data line for the second storage unit are different lines.

  According to this configuration, by providing different data lines in the first storage unit and the second storage unit, the operation of the first storage unit and the operation of the second storage unit can be performed in parallel. it can.

[Application Example 4]
In the semiconductor memory device according to the application example described above, it is preferable that data is written to the first storage unit once for each of the plurality of words.

  According to this configuration, the OTP memory can be used for the first storage unit by writing to any one word in the first storage unit once, and the manufacturing cost of the semiconductor storage element can be reduced. Can be planned.

[Application Example 5]
A method for controlling a semiconductor memory device according to this application example stores a first storage unit configured by a plurality of words and first information for specifying a first address for selecting one of the plurality of words. The first address specified from the first information when the data is written to the first storage unit using the second storage unit is the time when the data is read from the first storage unit. The second storage unit is an address for selecting the next word of the first address specified from the first information, and when writing data to the first storage unit, the second storage unit at substantially the same timing. The first information is written in the storage area.

  According to this method, the first storage unit in which an arbitrary word is selected by the first address and the second storage unit that stores the first information that specifies the first address are used. The first address specified from the first information when writing data to the storage unit is the next word after the first address specified from the first information when reading data from the first storage unit. This is the address to be selected, and when writing data to the first storage unit, the first information is written to the second storage unit at substantially the same timing, thereby setting a new address value and The time required for writing in the second storage after the time required for writing in the storage can be eliminated, and the processing efficiency can be increased.

[Application Example 6]
In the method of controlling a semiconductor memory device according to the application example, it is preferable that the second storage unit can store at least the same number of pieces of first information as the number of words in the first storage unit.

  According to this method, the first information is information indicating that data has been written to a predetermined word in the first storage unit, and the second storage unit is a word in the first storage unit. Since the first information equal to or more than the number can be stored, all the words in the first storage unit can be identified by the first information stored in the second storage unit.

[Application Example 7]
In the method of controlling a semiconductor memory device according to the application example described above, it is preferable that a data line for the first memory unit and a data line for the second memory unit are different lines.

  According to this method, by providing different data lines in the first storage unit and the second storage unit, the operation of the first storage unit and the operation of the second storage unit can be performed in parallel. it can.

[Application Example 8]
In the method of controlling a semiconductor memory device according to the application example described above, it is preferable that data is written to the first storage unit once for each of the plurality of words.

  According to this method, it is possible to use the OTP memory for the first storage unit by writing once to any one word in the first storage unit, and to reduce the manufacturing cost of the semiconductor storage element. Can be planned.

1 is a schematic block diagram of a semiconductor memory device according to a first embodiment. The schematic block diagram of the semiconductor memory device in 2nd Embodiment. The schematic block diagram of the semiconductor memory device in 3rd Embodiment. 1 is a schematic diagram of a timing chart in a semiconductor memory device. 1 is a schematic diagram of a timing chart in a semiconductor memory device. The figure which shows the example of the state of a 1st memory | storage part and a 2nd memory | storage part. FIG. 10 is a schematic block diagram of a semiconductor memory device according to a fourth embodiment.

  Embodiments of the present invention will be described with reference to the drawings. In addition, the figure to be used is for convenience of explanation. In the following description, a case where the potential of the signal value is higher than a predetermined threshold is described as H level, and a case where the potential of the signal value is lower than the predetermined threshold is described as L level.

(First embodiment)
FIG. 1 shows a schematic block diagram of a part of a semiconductor memory device 100 to which the present invention is applied. The semiconductor storage device 100 includes a first storage unit 10, a second storage unit 20, an address generation unit 30, and a control unit 40. The semiconductor memory device 100 stores predetermined parameters for adjusting or setting an external device (not shown) connected via an external signal 90. The predetermined parameter is stored in the first storage unit 10, output to the control unit 40 as output data 12, output from the control unit 40, and transmitted to the external device via the external signal 90.

  The control unit 40 is a part that controls the first storage unit 10, the second storage unit 20, and the address generation unit 30 based on an instruction from the external device via the external signal 90, and transmits and receives data to and from each of them. Then, a control signal described later necessary for the operation is generated. The control unit 40 performs an interface with the external signal 90. However, the external signal 90 may be in the form of a bus or may be configured by a dedicated connection line. The processing portion for the external device in the control unit 40 may have a function according to the specification of the external device, and does not directly affect the contents of the present invention.

  The control signals output by the control unit 40 include an RW switching signal 41, a latch timing signal 42, a first read instruction signal 43, a second read instruction signal 44, and a write instruction signal 45. These control signals are signals generated by the control unit 40 in order to execute a command or the like given from the external device via the external signal 90.

  The RW switching signal 41 is a control signal for the address generation unit 30 and is a signal used to identify whether the instruction from the external device is a parameter reading instruction or a parameter writing instruction.

  The latch timing signal 42 is a control signal for the address generation unit 30 and is a signal used to hold a value output as the first address 31.

  The first read instruction signal 43 is a control signal for the first storage unit 10 and is a signal used to instruct reading of data from the first storage unit 10. Data read from the first storage unit 10 is transmitted to the control unit 40 as output data 12 and is transmitted to an external device via an external signal 90.

  The second read instruction signal 44 is a control signal for the second storage unit 20 and is a signal used to instruct reading of data from the second storage unit 20. Data read from the second storage unit 20 is transmitted to the address generation unit 30 as output data 22.

  The write instruction signal 45 is a signal for instructing data writing to the first storage unit 10 and the second storage unit 20. Write data to the first storage unit 10 is input data 11, and write data to the second storage unit 20 is input data 21. Both the input data 11 and the input data 21 are output from the control unit 40.

  The first storage unit 10 includes a plurality of words of non-volatile memory. The number of bits in one word is not particularly limited as long as it has the number of bits required for the external device described above. The first address 31 is used to specify which word among the plurality of words is selected. A write instruction to the first storage unit 10 is given by a write instruction signal 45 output from the control unit 40, and the value of the input data 11 is stored. In addition, a read instruction from the first storage unit 10 is performed by a first read instruction signal 43 output from the control unit 40, and a value is output as the input data 21.

  The second storage unit 20 includes a nonvolatile memory having the same number of words as the first storage unit 10. The number of bits of one word in the second storage unit 20 is the same as the number of words, and a predetermined one word in the first storage unit 10 is associated with a predetermined one bit in all the words in the second storage unit 20. The predetermined 1-bit bit position is the same in all words. This 1-bit information is called first information. The second storage unit 20 is a memory having the same number of first information as the number of words in the first storage unit 10. In the present embodiment, it is assumed that the initial value of each bit in the second storage unit 20 is H level.

  When data is written to a predetermined one word in the first storage unit 10, a predetermined 1-bit value for the word specified by the second address 32 in the second storage unit 20 at substantially the same timing. Is written to change. The value of the first address 31 and the value of the second address 32 only have to correspond one-to-one, and may be the same value or different, but the control logic is simpler when the same value is used. There are many cases. For example, when data is written to the word selected when the value of the first address 31 is “10” with respect to the first storage unit 10, the second address 32 of the second storage unit 20 is The value of a predetermined 1 bit of the word selected when “10” may be changed.

  Further, the position of the predetermined 1 bit described above may be an arbitrary position as long as the predetermined 1 bit corresponds to the value of the first address 31 on a one-to-one basis. A write instruction to the second storage unit 20 is given by a write instruction signal 45 output from the control unit 40. As described above, in this embodiment, the initial value of each bit of the second storage unit 20 is H level. Therefore, in the present embodiment, writing in which the value is changed indicates that the H level is rewritten to the L level, and the data to be changed is determined by the control unit 40 and transmitted to the second storage unit 20 as the input data 21. The

  A read instruction to the second storage unit 20 is given by a second read instruction signal 44 output from the control unit 40. At the time of reading in the second storage unit 20, the value of the second address 32 is ignored, and data when all the words are selected simultaneously is output as the output data 22. In this case, the output value of each bit of the output data 22 is a logical product of the bit values at the same position in all words. When writing, the value of a predetermined bit of the word selected by the second address 32 is changed. When reading, the values of all the words are simultaneously read, so that all the changed first information is read. Will be read.

  The power consumption during writing of data in the nonvolatile memory is generally larger than the power consumption during reading. By limiting the writing of data to the second storage unit 20 to a predetermined 1 bit of one word selected by the second address 32, power consumption at the time of writing to the second storage unit 20 is reduced. Can do.

  The address generation unit 30 is a part that generates the first address 31 and the second address 32 based on the value (a plurality of first information) of the output data 22. The plurality of pieces of first information are latched in the address generator 30 at a timing defined by the latch timing signal 42.

  Address control for the first storage unit 10 is performed as follows. When the RW switching signal 41 instructs reading, an address value defined by a plurality of pieces of first information is output as the first address 31. When the RW switching signal 41 instructs writing, an address value for selecting the next word after the word selected by the address defined by the plurality of first information is output as the first address 31.

  The address control for the second storage unit 20 is performed as follows. When the write instruction signal 45 permits writing, an address value for selecting a word next to a word selected by an address defined by the plurality of first information is output as the second address 32. In other cases, the value of the second address 32 is ignored in the second storage unit 20, and all the words in the second storage unit 20 are selected. Note that an address value for selecting all words may be defined as the value of the second address 32, and the address value may be output when the second read instruction signal 44 instructs reading.

  The write instruction signal 45 is controlled by the control unit 40 so as to issue a write instruction after a predetermined period in the write cycle of the semiconductor memory device 100 has elapsed. For this reason, the second storage unit 20 is in a read state during the predetermined period. A plurality of pieces of first information read at this time are latched by the latch timing signal 42 and used to generate the first address 31 and the second address 32.

  The input data 11 is data that is generated and output by the control unit 40 based on the setting data transmitted by the external signal 90. The value of the input data 11 may be the same as the setting data, or may be a different value by encoding the setting data by a predetermined method. When the setting data is encoded into the input data 11, the control unit 40 needs to decode the value of the output data 12 and transmit it to the external device via the external signal 90.

  The input data 21 is data that is managed by the control unit 40 and is generated and output as a value that changes a predetermined 1-bit value when writing to the first storage unit 10 is performed. By having the information related to the plurality of pieces of first information in the control unit 40, the configuration in the semiconductor memory device 100 can be simplified when it is necessary to manage the plurality of pieces of first information in the external device. When it is not necessary to manage a plurality of pieces of first information in the external device, although not shown, the value of the input data 21 may be generated by the address generation unit 30 from which the plurality of pieces of first information are read.

  Next, the operation of the semiconductor memory device 100 will be described using a timing chart. FIG. 4 shows a timing chart 200 showing a write operation in the semiconductor memory device 100, and FIG. 5 shows a timing chart 300 showing a read operation. In any figure, → t in the figure indicates the passage of time. In the figure, the signal level on the H side is H level, and the signal level on the L side is L level.

  First, a write operation in the semiconductor memory device 100 will be described using the timing chart 200. The control unit 40 starts control of the write operation when a write instruction is issued from the external device via the external signal 90.

  At timing T1, control by the control unit 40 is started in response to an instruction from the external device. The RW switching signal 41 is set to a value indicating a write operation (L level), and the second read instruction signal 44 is set to a value indicating a read instruction (L level). As a result, a plurality of pieces of first information (A) are output from the second storage unit 20.

  By outputting the plurality of first information (A) to the output data 22, the address generation unit 30 selects the next word after the word selected by the address defined by the plurality of first information (A). The address (C) is output to the first address 31 and the second address 32.

  Thereafter, at timing T2, the latch timing signal 42 becomes L level, and a plurality of pieces of first information (A) are held in a predetermined latch register in the address generation unit 30. By latching a plurality of first information (A), the second storage unit 20 is instructed to write, the second address 32 becomes valid, a predetermined word is selected, and the value of the output data 22 changes. The influence on the first address 31 and the second address 32 can be eliminated. Note that the generated first address 31 and second address 32 may be latched instead of the plurality of pieces of first information (A).

  At timing T3 after the plurality of pieces of first information (A) are latched, the control unit 40 sets the write instruction signal 45 to a value (L level) indicating a write instruction. Although the setting of the values (D and E) for the input data 11 and the input data 21 is described as being set immediately after the timing T1 in FIG. 4 for the sake of convenience, the setting is performed between the timing T1 and the timing T3. That's fine.

  By setting the write instruction signal 45 to the L level, the value (C) of the second address 32 becomes valid in the second storage unit 20. As a result, the input data 11 (D) is written to the first storage unit 10 and the second input data (E) is written to the second storage unit 20. As a result, the plurality of pieces of first information includes information that writing has been performed at the address (C) of the first storage unit 10. As a result, the plurality of pieces of first information in the second storage unit 20 have information on all addresses that have already been written in the first storage unit 10.

  An example of this state is shown in FIG. 6A schematically shows the state of the first storage unit 10, and FIG. 6B schematically shows the state of the second storage unit 20. Here, the number of words in the first storage unit 10 is m (m is a natural number). As shown in FIG. 6A, in the first storage unit 10, data is written in a word selected by the addresses A0, A1, and A2.

  The second storage unit 20 in this case is as shown in FIG. When writing is performed to the address A0 of the first storage unit 10, the value of the bit corresponding to the address A0 of the word selected by the address A0 of the second storage unit 20 is changed from the H level to the L level. . When writing is performed to the address A1 of the first storage unit 10, the value of the bit corresponding to the address A1 of the word selected by the address A1 of the second storage unit 20 is changed from the H level to the L level. . When writing is performed to the address A2 of the first storage unit 10, the value of the bit corresponding to the address A2 of the word selected by the address A2 of the second storage unit 20 is changed from the H level to the L level. .

  Next, a read operation in the semiconductor memory device 100 will be described using the timing chart 300. The control unit 40 starts the control of the read operation when a read instruction is issued from the external device via the external signal 90.

  At timing T5, control by the control unit 40 is started in response to an instruction from the external device. The RW switching signal 41 is set to a value (H level) indicating a read operation, and the second read instruction signal 44 is set to a value (L level) indicating a read instruction. Thereby, a plurality of first information (G) is output from the second storage unit 20.

  By outputting the plurality of first information (G) to the output data 22, the address generation unit 30 outputs the address (H) defined by the plurality of first information (G) to the first address 31.

  Thereafter, at timing T6, the latch timing signal 42 becomes L level, and a plurality of pieces of first information (G) are held in a predetermined latch register in the address generation unit 30. Further, the first read instruction signal 43 is set to a level (L level) indicating a read instruction, whereby the word value (J) selected by the address value (H) of the first storage unit 10 is used as the output data 12. It is output to the control unit 40. The control unit 40 transmits data based on the value (J) or (J) of the output data 12 to the external device via the external signal 90.

  In the state shown in FIG. 6, when a read instruction is given from the external device, the value read as the output data 22 from the second storage unit 20 is the value indicated by K in FIG. The address generated from is the address A2. The value of the word selected by the address A2 of the first storage unit 10 is the value (J) described above. Incidentally, when a write instruction is given from an external device in this state, the values output as the first address 31 and the second address 32 generated in the address generation unit 30 are values indicating the address A3, and the control unit 40 The input data 21 generated in is the value that sets the word corresponding bit position A3 to the L level.

  The storage elements of the first storage unit 10 and the second storage unit 20 are both OTP memories, and control elements (such as sense amplifiers) unique to the OTP memory are present in the first storage unit 10 and the second storage unit 20 respectively. . The structure of the OTP memory is simple compared to the MTP memory. By applying the present invention, a pseudo MTP memory that makes use of the characteristics of the OTP memory can be configured.

(Second Embodiment)
FIG. 2 shows a semiconductor memory device 101 according to this embodiment. In the following embodiments including this embodiment, the same or similar components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In addition, even if the configuration is different, the description of the same operation as the corresponding portion in the first embodiment is omitted.

  The semiconductor storage device 101 includes a first storage unit 10, a second storage unit 50, an address generation unit 70, and a control unit 40. The semiconductor memory device 101 stores predetermined parameters for adjusting or setting an external device (not shown) connected via the external signal 90. The predetermined parameter is stored in the first storage unit 10, output as output data 12, and transmitted to an external device via an external signal 90.

  The difference between the semiconductor memory device 101 and the semiconductor memory device 100 described above is due to a difference in configuration between the second storage unit 50 and the second storage unit 20 and a difference in configuration between the address generation unit 30 and the address generation unit 70. is there. The second storage unit 20 has the same number of word storage elements as the first storage unit 10, but the second storage unit 50 stores one word having the same number of bits as the first storage unit 10. It is composed of elements.

  For this reason, it is not necessary for the address generator 70 to set an address for the second storage unit 50, and one word is always accessed regardless of the value of the first address 31. In the one word, the value of a predetermined bit corresponding to the predetermined word in the first storage unit 10 is changed. Note that the second storage unit 50 is configured by an OTP memory in the same manner as the second storage unit 20. As a characteristic of the OTP memory, once changed to the L level, it cannot be changed to the H level, but access for changing the H level to the L level can be repeatedly performed. The write control in the second storage unit 50 may be performed for each bit. The position of the bit whose value is to be changed next can be determined from the change state of a plurality of bits.

  In the example of the present embodiment, the area in the second storage unit 50 can be reduced and the control of the address generation unit 70 can be simplified as compared with the example shown in the first embodiment.

(Third embodiment)
FIG. 3 shows the semiconductor memory device 102 in this embodiment. The semiconductor storage device 102 includes a first storage unit 10, a second storage unit 60, an address generation unit 80, and a control unit 46. The semiconductor memory device 102 stores predetermined parameters for adjusting or setting an external device (not shown) connected via the external signal 90. The predetermined parameter is stored in the first storage unit 10, output as output data 12, and transmitted to an external device via an external signal 90.

  The difference between the present embodiment and the above-described embodiment is that the second storage unit 60 and the configuration corresponding to the second storage unit 60 (the second storage unit 20 and the second storage unit 50) are different, the address generation unit The difference is the configuration difference between 80 and the portion corresponding to the address generation unit 80 (the address generation unit 30 or the address generation unit 70), and the configuration difference between the control unit 46 and the control unit 40.

  The second storage unit 60 has the same number of 1-bit storage elements per word as the number of words in the first storage unit 10. The input data 23 output from the control unit 46 is 1-bit data, which is supplied to all words. When writing to the second storage unit 60 is performed, the value (1 bit) of the word selected by the value of the first address 31 is changed. In addition, the outputs of all the words are output independently and constitute output data 22. When reading from the second storage unit 60, all words are selected.

  The address generated by the address generation unit 80 is the first address 31, and the first address 31 is output to the second storage unit 60. It is the same as in the second storage unit 20 that the word selection in the second storage unit 60 is required only when data is rewritten. Therefore, also in the first embodiment, the first address 31 can be used in the second storage unit 20 and the address generation unit 80 can be used as in the present embodiment. In addition, the 2nd memory | storage part 60 is comprised from OTP memory similarly to embodiment mentioned above.

(Fourth embodiment)
The present embodiment is an embodiment in the case where the addresses of the first storage unit 10 and the second storage unit 20 are designated from an external device. FIG. 7 shows the semiconductor memory device 103 in this embodiment. The semiconductor memory device 103 has a test selector 91. The internal control signal 96 in FIG. 7 represents the input data 11, the output data 12, and the input data 21 collectively. Similarly, the internal control signal 97 collectively represents the RW switching signal 41, the latch timing signal 42, the first read instruction signal 43, the second read instruction signal 44, and the write instruction signal 45. Regarding other configurations, the semiconductor memory device 103 has the same configuration as the semiconductor memory device 100.

  One of the external input address 92 and the first address 31 is selected by the test selector 91 and is output to the first storage unit 10 as the first memory address 94. Similarly, either the external input address 93 or the second address 32 is selected by the test selector 91 and is output to the second storage unit 20 as the second memory address 95.

  Although not shown, the selection instruction by the test selector 91 may be performed by setting an external pin of the external device or the semiconductor memory device 103. For example, an external device or an external pin of the semiconductor memory device 103 has a test pin having a function of setting a test mode, and the output of the test selector 91 when the test pin has a predetermined value indicating the test mode is an external input address 92 and the external input address 93 may be used. Thereby, the write operation and the read operation can be performed by directly specifying the addresses of the first storage unit 10 and the second storage unit 20 from the outside.

  Although not shown, the input data 11 and the input data 21 in the test mode may be provided from an external pin by providing a selector similar to the test selector 91. Note that the selector may not be provided and may be provided via the external signal 90 and the control unit 40.

  The application examples and embodiments according to the present invention have been described above, but the implementation of the present invention is not limited to the application examples or embodiments described above. For example, the input data 21 may be generated by the address generation unit 30 and output to the second storage unit 20 or the second storage unit 50. Since the input data 23 may be a fixed value, it may be set in the second storage unit 60. The present invention can be widely applied without departing from the spirit of the present invention.

  DESCRIPTION OF SYMBOLS 10 ... 1st memory | storage part, 11 ... Input data, 12 ... Output data, 20 ... 2nd memory | storage part, 21 ... Input data, 22 ... Output data, 23 ... Input data, 30 ... Address generation part, 31 ... 1st address , 32 ... second address, 40 ... control unit, 41 ... RW switching signal, 42 ... latch timing signal, 43 ... first read instruction signal, 44 ... second read instruction signal, 45 ... write instruction signal, 46 ... control 50 ... second storage unit 60 ... second storage unit 70 ... address generation unit 80 ... address generation unit 90 ... external signal 91 ... test selector 92 ... external input address 93 ... external input address 94: First memory address, 95: Second memory address, 96: Internal control signal, 97: Internal control signal, 100: Semiconductor memory device, 101: Semiconductor memory device, 102: Semiconductor memory device 103 ... semiconductor memory device, 200 ... timing chart, 300 ... timing chart.

Claims (5)

A first storage unit configured by a plurality of word lines, wherein one of the plurality of word lines is selected by a first address;
A second storage unit for storing first information for specifying the first address;
Including
The first address specified from the first information when writing data to the first storage unit is specified from the first information when reading data from the first storage unit An address for selecting the next word line after the first address;
When data is written to the first storage unit, the first information is written to the second storage unit at substantially the same timing,
Wherein when data is read from the second storage unit, characterized in that outputs a logical product of the selected all the word lines of the plurality of word lines, connected to stored in the memory cell data value on the same bit line A semiconductor memory device.   2. The semiconductor memory device according to claim 1, wherein the second storage unit can store at least the same number of the first information as the number of word lines of the first storage unit.   3. The semiconductor memory device according to claim 1, wherein a data line for the first storage unit and a data line for the second storage unit are different lines.   4. The semiconductor memory device according to claim 1, wherein data is written to the first storage unit once for each of the plurality of word lines. 5. A method for controlling a semiconductor memory device, wherein a first storage unit configured to store a first storage unit configured by a plurality of word lines and a first address for specifying a first address for selecting one of the plurality of word lines is stored. 2 storage units,
The first address specified from the first information when writing data to the first storage unit is specified from the first information when reading data from the first storage unit An address for selecting the next word line after the first address;
When writing data to the first storage unit, the first information is written to the second storage unit at substantially the same timing,
Wherein when data is read from the second storage unit, select all of the word lines, the control method of the semiconductor memory device and outputs a logical product of the stored data values to the same bit line.

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