JPH05323949A - Drawing processor - Google Patents

Abstract

PURPOSE:To obtain the drawing processor which has a fast drawing speed and is inexpensive by displaying effective data between data of an image memory and a display memory, pixel by pixel. CONSTITUTION:Base image data are developed in an image memory (VRAM) 108, and the display memory (SRAM) 110 is provided and display data to be superimposed are developed. Then the drawing processor is provided with a display address generating circuit 112 for the display memory 110, a display detecting circuit 116 which detects whether or not there are the display data to be superimposed, and a selector circuit 117 which is controlled with its output signal. The output of the display detecting circuit 116 is connected to a D/A converter 118 with a look-up table, which is switched with the output signal of the display detecting circuit 116. Further, a horizontal and a vertical synchronizing signal are used to initialize the display address generating circuit 112, and the selector circuit 117 selects and sends effective data between the data of the VRAM 108 and SRAM 110 to the D/A converter 118, so that the data are displayed on a video monitor 120.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drawing processing apparatus for displaying a plurality of display screens on a display such as a CRT display in an overlapping manner.

[0002]

2. Description of the Related Art FIG. 4 shows a block configuration example of a conventional drawing processing apparatus. The central processing unit 1 of FIG. 4 controls the drawing processing unit 3 using an 8- or 16-bit microprocessor.
The system memory 2 is a memory for storing various information such as a program for operating the central processing unit 1 and calculation data. The drawing processing unit 3 uses a microprocessor to perform drawing processing and display processing. The DMAC (Direct Memory Access Controller) 4 does not directly transfer the data of the system memory 2 to the drawing processing unit 3 via the microprocessor of the central processing unit 1, but directly. This is a controller that transfers data from the system memory 2 to the drawing processing unit 3.

An image memory (VRAM) 5 is a memory for developing drawing data processed by the drawing processing unit 3.
The conversion circuit 6 converts the drawing data of the image memory 5 for images from parallel data to serial data and uses it as a video monitor signal. The video monitor 7 is a well-known R
The monitor operates with a GB signal, a horizontal synchronizing signal, and a vertical synchronizing signal.

The address bus 8 is connected to a central processing unit 1, a system memory 2 and a device of a DMAC (Direct Memory Access Controller) 4. The data bus 9 includes a central processing unit 1, a system memory 2 and D
The device connected to the MAC 4 and each device of the drawing processing unit 3
It is a bus that delivers data. Control bus 10
Is a bus for processing a read signal / write signal, a wait control signal, etc. output from the central processing unit 1.

FIG. 5 is an explanatory view of the display operation of the sync signal and the CRT screen. The display screen 11 displays the data allocated in the image memory 5. The specifications of the video monitor 7 are non-interlace mode without interlace scanning.
Do The horizontal synchronization cycle 13 is a horizontal synchronization signal (HSYNC
C) 12 and is composed of a horizontal sync width (HS) 14, a horizontal display period 15, a horizontal back-poch signal (HBP) 16 and a horizontal front-poch signal (HFP) 17. The vertical synchronization cycle 22 is the vertical synchronization signal (VSYNC) 2
It is controlled by 1 and comprises a vertical sync width (VS) 23, a vertical display period 24, a vertical back porch signal (VBP) 25 and a vertical front porch signal (VFP) 26.

The above signals are signals generated by initializing the drawing processing unit 3 of FIG. 4 by the operation of the program. FIG. 6 shows an example of a screen display function of a conventional drawing processing device. This shows that the normal display function (base screen) can display two split screens and one window screen. This function can be executed by setting various registers of the drawing processing unit 3.

[0007]

However, in the conventional apparatus having the above-mentioned structure, it is possible to perform the divided display of the area set on the divided screen or the window screen with respect to the base screen. For example, as shown in FIG. In the example of the map display of an in-vehicle navigation system, the current position display 71
When it is desired to superimpose the map layer 72 and the trajectory layer 73 on each other, that is, when the image data of arbitrary shape is superposed on the base screen,
It is generally difficult to display on the conventional split screen or window screen shown in FIG.

As a first method for overcoming the above problems, there is a method of superimposing image data of an arbitrary shape of the locus layer 73 on the map layer 72 of FIG. 7 by software. There is a problem that the amount of calculation processing for overwriting the trajectory data on the map layer 72 is very large and the drawing speed becomes slow.

As a second method, there is a method using a plurality of drawing processing units as shown in FIG. For example, the drawing processing unit 81 on the master side performs the processing of the map layer 72, the drawing processing unit 82 on the slave side performs the processing of the trajectory layer, and the drawing processing unit 83 on the slave side is used if necessary. If the method is adopted, it is possible to perform drawing at high speed, but there is a problem in that a drawing processing unit and a memory for layers to be processed are required and the device becomes expensive in terms of price.

The present invention has been made in view of the above points, and in the drawing processing apparatus which eliminates the above problems and superimposes image data of an arbitrary shape on a base screen. An object of the present invention is to provide an inexpensive drawing processing device having a high drawing speed.

[0011]

In order to solve the above problems, the present invention relates to a drawing processing apparatus for superimposing a plurality of display screens on a display such as a CRT display, and an image memory (VRAM) 108 as shown in FIG. A base image
Display memory (SRAM) 11 separately
0 is set and the display data to be superimposed is expanded. A display address generation circuit 112 for the display memory 110 and a display detection circuit 116 for detecting the presence or absence of display data to be overlaid.
And a selector circuit 117 controlled by the output signal of the display detection circuit 116.

The output of the display detection circuit 116 is a D / D with a look-up table (for designating the color of a pixel).
The above-mentioned display detection circuit 1 is connected to the A converter 118.
The look-up table is switched by an output signal of 16. The display address generating circuit 112 is initialized by using the horizontal synchronizing signal and the vertical synchronizing signal, and the selector circuit 117 causes the image memory 108 or the display memory 11 to be initialized.
It is characterized in that means for selecting the valid data of 0 and sending it to the D / A converter 118 and displaying it on the video monitor 120 is provided.

[0013]

According to the present invention, in a drawing processing apparatus for superposing image data of arbitrary shape on a base screen,
To provide a cheaper drawing processing device that achieves a higher drawing speed than the conventional technique of superimposing only one drawing processing unit with software and that performs superimposing with a plurality of conventional drawing processing units. You can Further, the display memory 110, the display detection circuit 116, and the selector circuit 117 of the present invention.
By making a plurality of inputs of the above, it becomes possible to provide a drawing processing device for performing multiple superimposition on the base screen, and the more superimposing is performed, the faster and cheaper the device becomes than the conventional one. ..

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an example of a block configuration of a drawing processing apparatus of the present invention. As shown in the figure, this device is a central processing unit 10
1, system memory 102, drawing processing unit 103, DMA
C (Direct Memory Access Controller) 10
4, address bus 105, data bus 106, control bus 107, image memory (VRAM) 108, P /
S converter 109, display memory (SRAM) 110, P /
S converter 111, display address generation circuit 112, display address bus 113, display data bus 114, display control bus 115, display detection circuit 116, selector circuit 117, D / A converter 118, latch circuit 119,
It is composed of a video monitor 120.

The central processing unit 101 shown in FIG.
Drawing processing unit 10 using a 6-bit microprocessor
Control 3 The system memory 102 is a memory for storing various information such as a program for operating the central processing unit 101 and calculation data. Drawing processing unit 103
In this system configuration example, performs drawing processing and display processing using a microprocessor. The DMAC (Direct Memory Access Controller) 104 is
Data in the system memory 102 is stored in the central processing unit 101.
It is a controller that directly transfers from the system memory 102 to the drawing processing unit 103 without passing through.

The image memory 108 is a memory for expanding the drawing data of the base screen which is processed by the drawing processing unit 103. The P / S converter 109 is a circuit for converting the contents of the image memory 108 from parallel to serial data, and in the present embodiment, a 4-bit output signal is obtained.
The display memory 110 is a memory for developing data for superimposing image data of an arbitrary shape on the base screen. In the present embodiment, the image memory 108 and the drawing processing unit 103 are used. It is possible to deliver the data via the. The P / S converter 111 is a circuit for converting the contents of the display memory 110 from parallel to serial data, and a 4-bit output signal is obtained in this embodiment.

A display switching signal from the central processing unit 101 is used to perform bus switching with the display address bus 113. The display address generation circuit 112 is initialized by the horizontal synchronizing signal, the vertical synchronizing signal, and the blank signal of the drawing processing unit 103, and the image memory 108 and the display memory 1 are initialized.
The drawing processing unit 10 is synchronized with the synchronization of the display of 10 data.
A circuit for controlling the display address using the display address signal 3 is connected to the display address bus 113, and the display address bus 113 and the display address bus 113 are switched by a display switching signal from the central processing unit 101.

FIG. 2 shows a synchronizing signal and display address generating circuit 1
12 shows 12 display address initialization signals. The drawing processing unit 103 in FIG. 1 generates various signals such as a horizontal synchronization signal 202, a horizontal blank signal 203, a vertical synchronization signal 206, a vertical blank signal 207, and a display address initialization signal 208 by using the display clock 201 in FIG. To do. The various signals perform the drawing display operation as described with reference to FIG.

In the display address initialization signal 208, all the horizontal synchronizing signal 204, horizontal blanking signal 205, vertical synchronizing signal 206 and vertical blanking signal 207 are Hi.
An initialization signal is generated at the gh level, and when this signal is generated, the initial start position of the display screen is detected. The display address bus 113 includes a drawing processing unit 103, an image memory 108, and a display memory 110.
It is connected to the. The display data bus 114 is a bus that is connected to the drawing processing unit 103, the drawing memory 108, and the display memory 110 to transfer data.

The display control bus 115 processes a read signal / write signal output from the drawing processing unit 103, a chip select signal of the image memory 108 and the display memory 110, and the like. The display detection circuit 116 uses the P / S
This is a circuit that logically sums the data of the 4-bit output signal of the converter 111. In the present embodiment, as an algorithm for superimposing the data of the display memory 110 on the image memory 108, the 4-bit data of the display memory 110 is used. When the logical sum of the output signals is a logic level High level, it is considered valid. So if you don't want to
It suffices that the logical sum of the 4-bit output signals of the P / S converter 111 becomes the logic level Low level. That is, if any of the 4-bit output signals of the display memory 110 is at the high level, the data of the display memory 110 is preferentially displayed, and the corresponding data of the image memory 108 is invalidated and not displayed.

The selector circuit 117 receives the 4-bit output signal from the P / S converters 109 and 111 as an input, and outputs the output signal from the display detection circuit 116 to the image memory 1.
It is a circuit for switching and outputting the data of 08 and the data of the display memory 110. Known analog RBG output D /
The A-converter 118 has a look-up table function in this embodiment. The latch circuit 119 is a circuit that latches the display address because it is multiplexed with the display data bus 114 of the display address bus output from the drawing processing unit 103 of this embodiment.
The video monitor 120 is a monitor that operates with known RGB signals, horizontal synchronizing signals, and vertical synchronizing signals.

FIG. 3 shows an example of data of the image memory and the display memory input to the selector circuit 117. Figure 3
The display clock 301 is the same as the clock 201 in FIG. Further, in this embodiment, this clock is t
_It shows the passage of time from ₁ to t ₂₂ . The bit data 302 to the bit data 305 are the image memory 108.
The bit data 302 has weighting of upper bits and the bit data 304 has weighting of lower bits. Bit data 306 to bit data 30
Reference numeral 9 is bit data from the display memory 110. The bit data 306 has weighting of upper bits and the bit data 309 has weighting of lower bits.

Data 313 to 315 represent the data of the display memory 110 output in synchronization with the display clock 301, and the data 313 and the data 315 represent the data of the display memory 110. Is all logic level and low level, the data in the display memory 110 is invalid as described above. In the area from t ₁₁ to t ₁₇ shown in the data 314, the logical sum of the data of the display memory 110 is the logic level and is the High level, and the output of the display detection circuit 116 in FIG. 1 is the output of the selector circuit 117. Indicates that the display memory 110 side is selected and the display memory 110 becomes valid.

Data 310 to data 312 represent image memory data output in synchronization with the display clock 301. The data 310 and the data 312 are the image memory 10.
It is shown that the data of 8 is valid. The data 311 (t _{11 to} t ₁₇ ) of the image memory 108 becomes invalid. That is, t _{1 to} t
₁₀ during the data of the image memory 108 - motor 310, t ₁₁ ~t
₁₇ between the display memory 110 de - data 314, t ₁₈ ~t
_During the period ₂₂ , the data 312 of the image memory 108 is displayed on the video monitor 120.

In the present embodiment, the navigation system has been described as an example, but the display memory 110 of the present invention is used.
By using a plurality of inputs to the display detection circuit 116 and the selector circuit 117, it becomes possible to provide a drawing processing device for performing multiple superposition on the base screen, and a window such as a workstation device can be realized. It can also be applied to a drawing processing device having multiple screens.

[0026]

As described in detail above, according to the present invention, the following effects are expected. (1) In a drawing processing apparatus for superimposing image data of an arbitrary shape on a base screen, a higher drawing speed than that for performing superposition with only one drawing processing unit of the prior art is used. It is possible to provide an inexpensive drawing processing apparatus which is obtained and which is performed by superimposing a plurality of drawing processing units of the related art.

(2) Further, by providing a plurality of inputs of the display memory, the display detection circuit and the selector circuit of the present invention, it becomes possible to provide a drawing processing apparatus for performing multiple superposition on the base screen. However, the more superposition is performed, the faster and cheaper the device becomes than the conventional one. Therefore, the present invention can be applied to a drawing processing device such as a workstation having multiple window screens.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a drawing processing apparatus of the present invention.

FIG. 2 is a diagram showing a synchronization signal and a display address initialization signal of a display address generation circuit.

FIG. 3 is a diagram showing an example of data of an image memory and a display memory input to a selector circuit.

FIG. 4 is a diagram showing an example of a block configuration of a conventional drawing processing device.

FIG. 5 is an explanatory diagram of a display operation of a sync signal and a CRT screen.

FIG. 6 is a diagram showing an example of a screen display function of a conventional drawing processing device.

FIG. 7 is a diagram showing a map display example of an in-vehicle navigation system.

FIG. 8 is a diagram illustrating an example of a drawing processing device including a plurality of drawing processing units.

[Explanation of symbols]

101 central processing unit 102 system memory 103 drawing processing unit 104 DMA (direct memory access
Controller) 105 address bus 106 data bus 107 control bus 108 image memory 109 P / S converter 110 display memory 111 P / S converter 112 display address generation circuit 113 display address bus 114 display data bus 115 display controller -Rubbus 116 Display detection circuit 117 Selector circuit 118 D / A converter 119 Latch circuit 120 Video monitor

Claims (2)

[Claims] 1. A drawing processing apparatus having a display device having an image memory and capable of superposing and displaying a plurality of display screens on a display surface of the display device, wherein a display memory is provided separately from the image memory. Along with the provision of detection means for detecting which of the data of the image memory and the data of the display memory corresponding to the pixel of the display screen is more effective, and means for selecting the more effective data. The data of the image memory and the data of the display memory are detected on the display surface of the display device by using the detecting means and the selecting means of the data. A drawing processing device, characterized in that a means for displaying is provided. 2. The display memory is expanded to a plurality of units, and the effective data detecting means and the selecting means are used as data of the image memory.
2. The drawing processing apparatus according to claim 1, wherein the drawing processing apparatus can be expanded so that valid data can be detected and selected from the data of the display memory and the plurality of display memories.