JP3048807B2 - Image processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method having a plurality of image output devices and an apparatus therefor.

[0002]

2. Description of the Related Art A conventional image output apparatus which simultaneously uses a plurality of output devices and outputs a different screen to each output device will be described with reference to FIG. The CPU 901 is
Controls the entire display device. The main VRAM 909 is a storage memory for image data, and is accessed by the CPU 901.

A display controller A 902 has a CRT 90
7 to control the display of image data. The CRT VRAM 904 is a memory that stores display data to be displayed on the CRT. DAC90
6 is a CRT output from the display controller A902.
Display digital data for display to analog display data.

On the other hand, the display controller B 903 is
LCD display data and a control signal are supplied to D908 to control the display of image data. VRAM9 for LCD
A memory 05 stores display data to be displayed on the LCD.

In this configuration, image data to be displayed for each display device is transferred from the main VRAM to the CRT VR.
The display is performed after loading into the AM and the LCD VRAM, respectively.

FIG. 10A is a diagram for explaining an example of the relationship between the main VRAM area and the display areas on the CRT 907 and the LCD 908. 1001 is a main VRAM
1002a is a CRT display area, 1003a
Indicates an LCD display area.

In FIG. 10B, 1002b is 100
This is an enlarged display of only the area 2a, and this image is displayed on the CRT 907. 1003b is 100
This is an enlarged display of only the area 3a, and this image is displayed on the LCD 908.

Next, the CRT with the hardware configuration shown in FIG.
The operation flow when displaying the image at 907 will be described with reference to FIG.

First, in step S1101, the image data already stored in the main VRAM
The area to be displayed in T907 is specified. This specification
For example, an address value of image data stored in the main VRAM 909 is input from an input device such as a keyboard (not shown).

In step S1102, the CPU 901
Is the VR for CRT from the designated area of the main VRAM 909.
Display controller A to display transfer request command to AM904
902.

In step S1103, the display controller A 902 reads the image data in the designated area from the main VRAM 909 and transfers it to the CRT VRAM 904.

In step S 1104, the display controller A 902 reads data from the CRT VRAM 904 and outputs the data to the D / A converter (DAC) 906.

In step S1105, the DAC 906 converts the digital display data into analog display data and
Output to RT907. At the same time, the display controller A90
2 by synchronizing the CRT control signal generated in 2 with the analog display data and outputting it to the CRT 907,
The display is performed at T907.

FIG. 12 is a diagram showing an example of the configuration of the display controller A 902 and the display controller B 903.
Here, reference numeral 1201 denotes a CPU I / F, which transmits / receives data to / from the CPU 901 and transmits / receives data to / from the main VRAM 909. Reference numeral 1202 denotes a timing control circuit,
RAM 904 or LCD VRAM 905 (hereinafter simply referred to as V
RAM) and controls the display control signal generation circuit. The VRAM I / F 1203 is a VRAM
Interface for access to the
A control signal for refreshing the AM is output. The display control signal generation circuit 1204 includes the timing control circuit 120
A display control signal, that is, a vertical synchronizing signal or a horizontal synchronizing signal, is generated from the timing signal input from the second input terminal. The display data conversion circuit 1205 converts the image data read from the VRAM in byte units into bit serial display data and outputs the data.

In the configuration of the conventional image display device described above, when the display screen is changed, the main VRAM 90 is used.
9 by changing the image data.

[0016]

However, in the above-mentioned conventional example, the display screen and the image data of the main VRAM are one in size.
Basically, the same background image is displayed on a plurality of display screens, and the same background image is displayed on one display screen while another image is superimposed. A separate image corresponding to each display screen must be prepared in the VRAM, and a large-capacity main VR
AM was required, and the same background image had to be copied to each position of the main VRAM corresponding to each display screen, resulting in a large processing time overhead.

Further, it has been difficult to modulate the image data of the main VRAM, for example, to change the display color or change the luminance at high speed with a small amount of the main VRAM.

In recent years, the above-described image processing function has become important. For example, as the demand for an image processing apparatus for presentation using OA equipment has increased, the display screen for presentation and the screen display for operation have been described. Functions are needed.

The present invention has been made in view of the above-mentioned conventional example. Even if the original output image data is basically the same, a plurality of different image output means can transmit a different image to each of the plurality of image output means. It is another object of the present invention to provide an image processing method and an image processing method capable of outputting an image easily and with a small capacity of an image storage means.

[0020]

In order to achieve the above object, an image processing apparatus according to one aspect of the present invention has, for example, the following configuration. That is, an image processing apparatus for forming an image on a first image output device and a second image output device, and a common output for outputting to the first image output device and the second image output device Image storage means for storing image data in a plurality of planes, and a plane not outputting to the first image output device among the plurality of planes when outputting the output image data to the first image output device Mask data storage means for storing mask data for instructing the mask data, and based on the mask data stored in the mask data storage means, of the output image data stored in the image storage means, Display control means for outputting data to the first image output device.

An image processing apparatus according to another aspect of the present invention has, for example, the following configuration. That is, an image processing device that forms an image on a plurality of image output devices, an image storage unit that stores common output image data to be output to the plurality of image output devices, and an area in the output image data is set Area data storage means for storing area data to be stored, partial image data storage means for storing partial image data to be displayed in the area, and output image data stored in the image storage means to the plurality of image output devices. Output control means for outputting, and a first of the plurality of image output devices
When outputting the output image data to an image output device,
Switching means for outputting the partial image data within the area and outputting the output image data outside the area based on the area data stored in the area data storage means. Further, an image processing apparatus according to another aspect of the present invention has, for example, the following configuration. That is, a first image output unit, a second image output unit, an image storage unit that stores common output image data to be output to the first image output unit and the second image output unit, Partial image storage means for storing partial image data to be output by the first image output device; area storage means for storing area data for setting an image area for outputting the partial image data; In the case where the display is performed on the means, a first image for displaying the partial image data in an area set by the area data stored in the area storage means, and displaying the output image data outside the area. Output control means; and second output control means for reading the output image data from the image storage means and displaying the output image data on the second image output means.

[0022]

According to the above arrangement, in an image processing apparatus for forming an image on the first image output device and the second image output device, common output image data to be output to each image processing device is a plurality of planes. Is stored. Further, mask data indicating a plane not to be output to the first image output device out of the plurality of stored planes is stored. Then, based on the stored mask data, out of the plurality of planes of the stored output image data, data of a plane other than the masked plane is output to the first image output device.

According to another configuration, in an image processing apparatus for forming an image on a plurality of image output devices, an image storage means for storing common output image data to be output to the plurality of image output devices, Area data storage means for storing area data for setting an area in the image data, and partial image data storage means for storing partial image data to be displayed in this area are provided. When outputting the output image data stored in the image storage means to a plurality of image output devices, if the output image data is to be output to a first image output device of the plurality of image output devices, the area data Based on the area data stored in the storage means, switching is performed so that the partial image data stored similar to the partial image data storage means is output in the corresponding area, and the output image data is output outside the area. According to another configuration, an image storage unit that stores common output image data to be output to the first image output unit and the second image output unit, and a unit that outputs the image data to the first image output device The image processing apparatus includes a partial image storage unit for storing image data, and an area storage unit for storing area data for setting an image area for outputting the partial image data. Here, when display is performed on the first image output means, partial image data is displayed in an area set by the area data stored in the area storage means, and output image data is displayed outside the area. The second image output means is controlled to display the output image data read from the image storage means.

[0024]

【Example】

[First Embodiment] An embodiment according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a hardware configuration of an image display device according to the first embodiment. The CPU 101 controls the entire image display device of the first embodiment. Main VRAM 114
Is a memory for storing data to be displayed on the CRT 112 or the LCD 113. The bitmap image data stored in the main VRAM 114 is stored in the CRT 112 or LCD.
In order to display the image data on the main RAM 113, the CPU 101 reads the image data of the main
Then, the display image data is read from the VRAM 105 and displayed on the CRT 112 or the LCD 113. To transfer data selected from the main VRAM 114 to the VRAM 105, the CPU 101
Issues a transfer request command to the CPU I / F 102,
The UI / F 102 sends a timing signal generation request for data transfer to the timing control circuit 103. The timing control circuit 103 generates a data transfer timing signal in synchronization with a predetermined clock signal,
Output to F104. The VRAM I / F 104 stores the image data read from the main VRAM 114 in the VRAM 105 based on the data transfer timing signal.

The VRAM 105 is composed of a plurality of planes so that a multi-color or multi-tone display can be performed.
For example, if each plane corresponds to each component of RGB,
Multicolor display can be performed. Further, in order to perform multi-tone display, for example, four tones are expressed using two planes, and sixteen tones are expressed using four planes. In the first embodiment, an example is shown in which 16 planes are expressed using 4 planes. FIG. 2 shows that the VRAM 105, which is a bitmap memory, has four planes, that is, plane 1
FIG. 4 is a diagram for explaining the correspondence with a display screen, that is, a CRT or an LCD, when the display device is composed of. Since the display screen is composed of four planes, the display screen can display 16 gradations. Here, plane 1, plane 2, plane 3,
The weight coefficient of each data of plane 4 is 2 0
It has a power of 2, a power of 2, a power of 2, a power of 2, and a power of 3.

Next, the hardware configuration of the image display device according to the first embodiment will be described with reference to FIG. VRA
Reading of the bitmap data stored in M105 is performed based on the read request signal output from the timing control circuit 103, and the VRAM I / F 104 generates
The reading is executed in synchronization with the RAM reading control signal. The read bitmap data is stored in the VRAMI
The data is transferred to the display data conversion circuit A107 and the display data conversion circuit B109 via the / F104. The display data conversion circuit A107 and the display data conversion circuit B109 convert the display data into display data suitable for the display device connected to each of them. That is, in the display data conversion circuit A107, the input bitmap data is converted into CRT digital display data, and in the display data conversion circuit B109,
For example, the input bitmap data is converted into display data for LCD by performing gray scale conversion by a dither method.

Next, the display control signal generation circuit A106 receives a synchronization signal generation request signal for the CRT 112 from the timing control circuit 103, and generates a horizontal synchronization signal and a vertical synchronization signal for the CRT 112 in synchronization with the signal. . Similarly, the display control signal generation circuit B108 receives a synchronization signal generation request signal for the LCD from the timing control circuit 103, and
A line synchronizing signal, a frame synchronizing signal, a liquid crystal alternation signal, and the like necessary for display on the CD 113 are generated and sent to the LCD 113, and LCD display data synchronized with these signals is sent from the display data conversion circuit B109 to the LCD 113. As a result, the bitmap data in the VRAM 105 is displayed on the LCD 113.

On the other hand, the digital display data for CRT converted by the display data conversion circuit A107 is sent to the mask calculation circuit 110 and subjected to mask processing. FIG. 3 is an example of a detailed circuit diagram of the mask operation circuit 110, which will be described with reference to FIG.

In the mask operation circuit 110, the CPU
/ F102, the flip-flop (FF) 3
The AND values of the data values stored in 01 to 304 and the CRT digital display data are AND-operated by AND circuits 305 to 308. Here, 4 bits of the CRT digital display data respectively correspond to 4 planes of the bit map memory. That is, C input to the AND circuits 305 to 308
The RT digital display data corresponds to each of the planes 1 to 4. By setting a mask value to each of the four flip-flops, a specific plane can be invalidated. For example, flip-flops 301 to
When 1, 1, 1, and 0 are set in 304, plane 4 is masked and becomes invalid.

Next, each of the masked image signals is D
The data is transferred to the AC 111 and converted into analog display data for CRT. Then, the analog display data for each CRT is transferred to the CRT 112 and displayed on the CRT 112 in synchronization with the horizontal synchronization signal and the vertical synchronization signal output from the display control signal generation circuit A106.

FIG. 4 shows an operation flow of the image display apparatus in the first embodiment until the image data stored in the main VRAM 114 is displayed on the CRT 112 or the LCD 113.

In step S401, when an image display request command, for example, an image display request command is input from the keyboard 120, in step S402, the CPU 10
1 issues a transfer request command to the CPU I / F 102, and C
The PUI / F 102 sends a timing signal generation request for data transfer to the timing control circuit 103. The timing control circuit 103 generates a data transfer timing signal in synchronization with a predetermined clock signal,
Output to F104.

Then, in step S403, VRAMI
/ F104 is based on the data transfer timing signal,
The image data read from the main VRAM 114 is stored in the RAM 105.

From step S404 and step S406
Are executed in parallel.

Step S404 is processing related to LCD display. In this step, VRAM 105
The display data conversion circuit B109 inputs the image data read via the RAM I / F 104, converts the image data into display data for LCD, for example, performs gray scale conversion by the dither method, and converts the display data to LCD display data. Convert.

In step S405, LCD display data is displayed on the LCD 113 screen.

In step S406, in this step, the image data read from the VRAM 105 via the VRAM I / F 104 is converted into the display data conversion circuit A1.
07 is input and conversion to digital display data for CRT is performed.

In step S407, the mask operation circuit 1
At 10, a mask operation is performed between the CRT digital display data and a preset mask value.

In step S408, the DAC 111
The masked data is input and converted to analog data.

In step S409, the CRT 112
Image display is performed by inputting analog data.

As described above, in the first embodiment,
The LCD displays a display according to the main VRAM data, and the CRT displays a display screen excluding a specific plane from the LCD display screen. Therefore, the LCD and the CRT are displayed with different color tones, or the same background image is displayed on the LCD and the CRT, but the pen movement coordinates input unit (not shown) inputs the pen movement coordinates, and LCD for moving locus
Can only be displayed. In this case, the movement locus data of the pen is assigned to, for example, plane 4 of the VRAM 105, and in the display on the CRT 112, the display data of the plane 4 is masked by the mask arithmetic circuit so that only the movement locus data of the pen is displayed on the CRT 112. Can be easily erased. On the other hand, the LCD 113 displays an entire image including the movement locus of the pen. FIG. 5 shows an example of the display. In this figure, reference numeral 500 denotes a state of the CRT display screen, and reference numeral 503 denotes a state of the LCD display screen. Reference numeral 501 denotes a movement locus of the pen, which is displayed on the LCD display screen 503 together with other background images.
On the CRT display screen 500, only the background image is displayed.

In the first embodiment, the mask operation circuit is A
Although the ND circuit is used, it is needless to say that various images can be displayed by using another circuit.

As described above, according to the present embodiment, the following effects can be obtained. That is, the main V
The display is performed according to the RAM data, and the CRT is displayed by excluding a specific plane from the display screen of the LCD by a mask function for each plane. Therefore, L
Although the color tone is displayed differently on the CD and the CRT, or the same background image is displayed on the LCD and the CRT, another image can be displayed only on the LCD with a minimum image memory capacity.

[Second Embodiment] In the first embodiment, the CR of each plane output from the display data conversion circuit A107 is
Since the mask calculation was performed on the digital display data for T, masking could be performed only in plane units, and only a specific area could not be masked or displayed. However, in the second embodiment, it is possible to select a specific part of the display screen and continue displaying that part on the LCD screen, and display the same image on both the CRT and the LCD in other areas.

FIG. 6 shows a hardware configuration of an image display device according to the second embodiment. CPU 101 to VRAM 10
5, a data transfer and display control signal generation circuit 106,
The display control signal generation operation in 108 and the display data conversion operation in the display data conversion circuits 107 and 109 are the first.
This is the same as the embodiment.

FIG. 7 shows an example of a display screen desired to be realized in the second embodiment. Hereinafter, the display device of the second embodiment shown in FIG. 6 will be described with reference to FIG. The following description is based on the premise that processing for realizing image display is performed. First,
After briefly describing FIG. 7, the display device of the second embodiment shown in FIG. 6 will be described.

FIG. 7 shows an operation screen of the LCD 113,
Using T112 as the presentation screen,
The screen display when the operation window is opened only on the CD 113 is shown. The LCD display screen 702 displays the entire screen. Here, reference numeral 701 denotes an operation window, which is displayed only on the LCD display screen 702 and not displayed on the CRT display screen 700.

Hereinafter, each processing unit will be described with reference to FIG. 6 and on the premise of the processing for realizing image display shown in FIG.

First, it is assumed that the entire image data to be displayed has already been stored in the VRAM 105. Hereinafter, the entire image data is referred to as “G3”.

First, the user operates the operation window 701.
Is specified by coordinates on the screen from the keyboard 120, for example. For example, since the operation window 701 is rectangular, the coordinates of two diagonal vertices may be specified. C
The PU 101 transmits these coordinate data to the keyboard 120.
After that, it is transferred to the switching signal generation circuit 601 via the CPU I / F 102. The switching signal generation circuit 601 converts the input coordinate data of the window area into
Store in the internal register. On the other hand, the CPU 101 saves the rectangular image part data corresponding to the area of the operation window 701 to another area of the VRAM 105. Hereinafter, the saved image data is referred to as “G2”. Then, the VRAM corresponding to the area of the operation window 701
In the rectangular image portion 105, data for blank display on the CRT 112 is stored. The image data for one page on the VRAM 105 thus obtained is hereinafter referred to as “G
1 ".

Next, using G1, the process of storing the partial data storing the blank of G1 in the buffer 602 is executed in the following procedure.

The CPU 101 gives a buffer latch request command to the switching signal generation circuit 601 via the CPU I / F 102. Then, the switching signal generation circuit 601 outputs a storage request timing signal to the buffer 602 from the display timing signal sent from the timing control circuit 103, and outputs the display data conversion circuit A
The display data output from 107 is stored in the buffer 602. Here, generation of the storage request timing signal is as follows.
For example, the following is performed. That is, the display timing signal sent from the timing control circuit 103 is counted to generate screen address coordinates. Then, compared with the display designation window coordinate data of the internal register, if the screen coordinates are within the designated window, a pulse-like storage request timing signal is generated. In the buffer 602,
The display data output from the display data conversion circuit A107 is stored in synchronization with the storage request timing signal.
At this time, the selector 603 determines that the input buffer 6
Neither the image data from C <b> 02 nor the image data from the display data conversion circuit A <b> 107 are selected, and predetermined data for blanking the display on the CRT 112 is output to the DAC 111.

Next, the CPU 101 stores “G2” stored in the VRAM 105 at the original position. Less than,
This entire image data is called “G3”. And CPU
101 outputs a buffer data display request command to the switching signal generation circuit 601. The switching signal generation circuit 601 receives the command and normally supplies a selection signal to the selector 603 so that the selector 603 selects display data output from the display data conversion circuit A107. Then, during the display timing of the image data stored in the buffer 602, a selection signal is given to the selector 603 so as to select the output from the buffer 602. By doing so, an image display without displaying the operation window 701 shown on the CRT display screen 700 can be obtained.

On the other hand, the LCD 113 has a VRAM 105
"G3", that is, an image including the operation window 701 is displayed.

FIG. 8 is a processing flowchart of the image display device of the second embodiment. Hereinafter, the process in each step will be described with reference to FIG.

In step S801, a command for displaying an operation window is input from the keyboard 120.

In step S802, the area coordinate data of the window to be displayed is input from the keyboard 120. Then, the area coordinate data is stored in the internal register of the switching signal generation circuit 601.

In step S803, blank data is stored in the buffer 602 in the area indicated by the area coordinate data by the method already described above.

In step S804, the above-described method
The entire image data “G3” to be displayed is generated in the VRAM 105.

Processing from step S805 and step S805
The processing from 806 is executed in parallel.

In step S805, the display data conversion circuit B109 converts the entire image data "G3" input from the VRAM 105 into LCD display data, and
Transfer to 113.

In step S807, the display control signal from the display control signal generation circuit B108 and the display data for LCD are input to the LCD 113 and sequentially displayed.

On the other hand, in step S806, the display data conversion circuit A107 converts the entire image data "G3" input from the VRAM 105 into CRT display data.
Transfer to CRT 112.

In step S808, the switching signal generation circuit 601 determines whether or not the display timing corresponding to the coordinate position data of the image for displaying the data in the buffer 602 stored in its internal register has come.

Then, at the time of displaying the data in the buffer 602, at step S809, the selector 60
3 is supplied with a selection signal for selecting output data from the buffer 602. Also, a read request signal is given to the buffer 602.

In step S809, the data from the buffer 602 is transferred to the DAC 111.

In step S811, the data input by the DAC 111 is sequentially converted into analog display data.

In step S812, the display control signal from the display control signal generation circuit A106 and the analog display data are input to the CRT 112 to perform display.

On the other hand, when the display of the data transferred from the display data conversion circuit A107 is selected in step S808, the display data conversion circuit A1 is selected in step S810.
07 to select the data to be transferred from
03 to the display data conversion circuit A1.
07 is transferred to the DAC 111.
Then, the respective steps S811, S812 are executed to sequentially display images.

By the above processing, as shown in FIG.
Different image outputs can be performed by the CRT and the LCD.

In the first embodiment, when the switching signal generation circuit 601, the buffer 602, and the selector 603 described in the second embodiment are constituted by the mask operation circuit 110 and the DAC 111, the operation in a specific screen area is performed. Can be displayed.

As an image output device, a CRT and an LC are used.
Although D has been described as an example, it goes without saying that this may be an output device such as a printer, for example.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

As described above, according to the second embodiment, the following effects can be obtained. That is, different displays can be performed on a specific area of an image on the LCD and the CRT.

[0076]

As described above, according to the present invention, even if the original output image data is basically the same for a plurality of image output means, different images can be quickly sent to each of the plurality of image output means. , And easily and with a small capacity of image storage means,
Can be output.

[0077]

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram of a first embodiment.

FIG. 2 is a diagram showing a correspondence between a display screen and a bitmap memory.

FIG. 3 is a detailed circuit diagram of a mask operation circuit 110 in FIG.

FIG. 4 is an operation flowchart in the first embodiment.

FIG. 5 is a diagram illustrating a display example on the image display device of the first embodiment.

FIG. 6 is a hardware configuration diagram according to a second embodiment.

FIG. 7 is a diagram showing a display example on the image display device of the second embodiment.

FIG. 8 is an operation flowchart in the second embodiment.

FIG. 9 is a hardware configuration diagram of an image display device in a conventional example.

FIG. 10 is a diagram illustrating an example of a relationship between a main VRAM area and a display area of each display device and a screen display.

FIG. 11 is an operation flowchart in a conventional image display device.

FIG. 12 shows display controllers 902 and 90 in FIG.
3 is a detailed block diagram of FIG.

[Explanation of symbols]

 101 CPU 102 CPU I / F 103 Timing control circuit 104 VRAM I / F 105 VRAM 106 Display control signal generation circuit A 107 Display data conversion circuit A 108 Display control signal generation circuit B 109 Display data conversion circuit B 110 Mask operation circuit 111 DA converter ( DAC) 112 CRT 113 LCD 114 Main VRAM.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Kazutoshi Shimada, 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Eisai Tatsumi 3-30-2, Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Shinichi Sunagawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Takashi Harada 3-30-2, Shimomaruko 3-chome, Ota-ku, Tokyo Canon Inc. ( 56) References JP-A-61-250680 (JP, A) JP-A-5-273947 (JP, A) JP-A-4-40491 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , (DB name) G09G 5/00 G06T 1/00 G06T 1/60

Claims (8)

(57) [Claims] 1. An image processing apparatus for forming an image on a first image output device and a second image output device, wherein the image is output to the first image output device and the second image output device. Image storage means for storing common output image data in a plurality of planes; and when outputting the output image data to the first image output apparatus, the image storage means is provided to the first image output apparatus among the plurality of planes. Mask data storage means for storing mask data indicating a plane not to be output; and, based on the mask data stored in the mask data storage means, a masked plane among the output image data stored in the image storage means. An image processing apparatus comprising: display control means for outputting data of a plane to be removed to the first image output device. 2. The apparatus according to claim 1, wherein said mask data storage means stores mask data indicating whether or not to output to said first image output device for each plane.
An image processing apparatus according to claim 1. 3. An image processing apparatus for forming an image on a plurality of image output devices, comprising: image storage means for storing common output image data to be output to the plurality of image output devices; Area data storage means for storing area data for setting an area; partial image data storage means for storing partial image data to be displayed in the area; output image data stored in the image storage means; Output control means for outputting to an output device, and when outputting the output image data to a first image output device of the plurality of image output devices, based on area data stored in the area data storage means, An image processing apparatus comprising: a switching unit that outputs the partial image data in an area and outputs the output image data outside the area. 4. The image processing apparatus according to claim 3, wherein the switching unit outputs the partial image data and the output image data based on a timing signal of the first image output device. . 5. An image storage for storing common output image data to be output to a first image output unit, a second image output unit, and the first image output unit and the second image output unit. Means, partial image storage means for storing partial image data to be output to the first image output device, area storage means for storing area data for setting an image area to output the partial image data, When the display is performed on the image output means, the partial image data is displayed in an area set by the area data stored in the area storage means, and the output image data is displayed outside the area. First output control means; and reading the output image data from the image storage means;
An image processing apparatus comprising: a second output control unit configured to display the image on the second image output unit. 6. The apparatus according to claim 5, wherein the first output control means displays the partial image data and the output image data based on a timing signal of the first image output device. Image processing device. 7. An image processing method for forming an image on a first image output device and a second image output device, wherein the image is output to the first image output device and the second image output device. A common output image data is stored in a plurality of planes of an image storage unit, and when the output image data is output to the first image output device, a plurality of planes of the plurality of planes stored in a mask data storage unit are stored. Based on mask data indicating a plane not to be output to the first image output device, data of planes other than the masked plane among the output image data stored in the image storage means is output to the first image output device. An image processing method for outputting to an apparatus. 8. An image processing method for forming an image on a plurality of image output devices, comprising: storing common output image data to be output to the plurality of image output devices in image storage means; Area data for setting an area is stored in area data storage means, partial image data to be displayed in the area is stored in partial image data storage means, and the first image output apparatus among the plurality of image output apparatuses is When outputting the output image data, based on the area data stored in the area data storage means, the partial image data is output within the area, and the output image data is output outside the area. Image processing method.