JPH0531978B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention includes a center device (also referred to as a master station) that controls transmission, a plurality of terminal devices (also referred to as a terminal station or a terminal), and a host computer (also simply referred to as a computer), and provides communication between the master station and the terminal stations. Or, in a transmission system that sends and receives data between terminal stations and also sends and receives data between a master station and a host computer, performing data transmission according to the speed and speed of data transfer between the host computer and the terminal. Regarding the system that can.

[Prior art and its problems]

In the following description of each figure, the same reference numerals indicate the same or corresponding parts. The closest prior art to the present application is Japanese Patent Application No. 59-244251 (Japanese Unexamined Patent Publication No. 61-123233) filed by the present applicant entitled "Data Transmission System".
(hereinafter referred to as application (1)) and Japanese Patent Application No. 59-244254 (Japanese Patent Application Laid-open No. 61-123235) entitled "Data Transmission System" (hereinafter referred to as application (2)). A general-purpose multiplex signal transmission device (product name: Remote Terminal) to which these inventions are applied is capable of transmitting input from scattered devices to a central computer (e.g., a personal computer) in order to centrally monitor and control devices scattered in various locations. Various data transmission devices have been manufactured for the purpose of collecting data and transmitting control outputs from the computer to scattered devices. These data transmission systems generally have a center device (main station) that controls communication for data transmission and exchanges data with terminals, and multiple terminals. The problem arises as to how to transmit the collected data to the computer, or how to transmit the control output data that the computer has prepared to output to the terminal via the above-mentioned center device. come. Conventionally, therefore, it has been common practice to provide a center device with a communication interface with an external host computer, and to perform data transmission between the center device and the host computer via this interface. This interface can be used as a general-purpose interface such as RS232C, which is also installed in personal computers.
GPiB interface is used. However, even if these interfaces are used, a communication protocol (control procedure) is still required, and in addition to error handling during data communication, data to execute the above procedure is also added. Therefore, there is a drawback that the data transmission time between the computer and the center device becomes slow. For this reason, even if the center device collects data from the terminal at high speed, there may be a delay in the data arriving from the center device to the computer side, or a delay in the transmission of control output from the computer to the terminal. There is a problem with this. In order to solve these problems, it is conceivable that data transmission speed can be increased by connecting a center device using a bus within a computer. This bus is used by a computer to control its internal memory or input/output devices, so data can basically be exchanged in a manner that matches the operating speed of the computer.
It is convenient and greatly improves the above-mentioned problems of long transmission time and slow data transmission. Methods using this bus include those that are standard in the industry, such as Multibus (a trademark of Intel Corporation), as well as methods that are uniquely designed on the computer side. There are various methods for these bus connections, and in this case, there are two modes: access from the computer side to the center device side, and conversely, access from the center device side to the computer side. Furthermore, the center device side has a timing for collecting data from terminals, and the computer side has a timing determined by the flow of the program, and these will conflict unless they cooperate. For this reason, in many data transmission systems, how to control these timings and determine priorities has become an important issue. In addition, one method of controlling these communications is to use dual ports to ensure data exchange without any abnormalities.
Data is exchanged using a mailbox method using RAM. This dual port RAM is a RAM device that has ports for the data bus and address bus on the computer side and ports for the data bus and address bus on the center device side, and this device also has one of the ports. A bus control circuit is provided for writing to or reading from the RAM device. By the way, as mentioned above, the mailbox method is used as a method for exchanging data using dual port RAM, but even with this method, various information is added in the same way as with serial transmission. However, in order to take measures against errors and abnormalities, the problem remains that the net data transmission time inevitably becomes slower. Also, regarding the method of sending control output from a computer to a terminal, there are cases where data is periodically transmitted to several terminals, and cases where data should be transmitted and output with priority to one terminal. Therefore, it is desired that such various data transmissions can be carried out efficiently.

[Purpose of the invention]

The present invention eliminates the above-mentioned problems, enables high-speed data transmission between a host computer and a center device, and enables sequential and periodic normal communication between a host computer and a large number of terminals. The object of the present invention is to provide a data transmission system that can efficiently perform data transmission (hereinafter referred to as cyclic communication) and emergency data transmission (hereinafter referred to as individual communication) with a designated terminal.

[Key points of the invention]

The gist of the present invention is to connect a host computer and a center device via a bus using a dual port RAM, and to store the following two areas in the dual port RAM: addresses of terminals to which data transfer should be prioritized at any given time;
A mail box (area) for transporting Di, Do data, registered data, etc. by individual communication that takes precedence over cyclic communication, and a Di, Do area arranged by address of all terminals for cyclic communication.
A dedicated data memory (area) for data storage is provided, and the computer side can write Do data and read Di data, and the center device side can read Do data and write Di data. The purpose of this invention is to efficiently carry out prioritized data transmission by individually communicating with the terminal at the address using a mailbox and by cyclically communicating with the terminal using the dedicated data memory. . In other words, the main points of the present invention are a center device, a plurality of address-specific terminals connected from the center device via transmission paths, and a common RAM (common RAM) with the center device.
The center device controls data transmission and exchanges data with terminals.
A data transmission system in which data written in RAM is sent to a terminal via a center device, and the center device reads the data received from the terminal and written to the common RAM, thereby exchanging data with the terminal. In the common RAM, a data storage area (dedicated data memory, etc.) for normal communication (for cyclic communication, etc.) and a data storage area (hereinafter referred to as mailbox) used for emergency communication (for individual communication, etc.) are installed. The data storage area for normal communication is provided for each address of each terminal, and the host computer sends and receives data to and from the terminal (Do data and Di
data), and the mailbox is configured to store at least the address of the terminal related to emergency communication and the data (Do data, etc.) to be sent by the host computer to the terminal. At the same time, the center device repeatedly specifies the address of each terminal or the corresponding address (block address, etc.) in a predetermined order while reading and writing to the data storage area for normal communication, and exchanges data. , and at least read the mailbox and give priority to the data exchange by specifying the terminal of the address related to the emergency communication and transmitting the data.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on FIGS. 1 to 4. Figure 1 shows an embodiment of the present invention.
Similarly, FIG. 2 is an explanatory diagram of the communication order, FIG. 3 is a block diagram of the data transmission system, and FIG. 4 is a diagram of the dual port RAM. In FIG. 3, 45, 45-1, 45-2...
is a terminal by address, and 43 is a center device, which controls data transmission between the terminals 45 or between the center device 43 and the terminal 45, and sends and receives data to and from the terminal 45 through this transmission. . 4
4 is a common transmission line connecting the center device 43 and each terminal 45; 41 is a host computer (also simply referred to as a computer) that exchanges data with the center device 43 via the dual port RAM 42; Also 46
is Di data that is input from the outside of this system to the terminal 45 and is further sent to the computer 41 via the center device 43, and 47 is sent from the computer 41 to the terminal 45 via the center device 43, and is further sent from the terminal 45 to the computer 41. This is Do data that is output externally. Although the configuration of the transmission path 44 is shown in a multi-drop format in FIG. 3, it may be connected in a loop, so the format of the transmission path is not particularly important. Next, in the dual port RAM 42 shown in FIG. 4, the left side of the figure is a bus for the computer 41, and the right side is a bus for the center device 43. This dual port RAM 42 has two ports on the computer 41 side and the center device 43 side, and has two ports on the computer 41 side and the center device 43 side.
Writing or reading is performed from either one of the RAM1. Since the common RAM 1 has an address space of 2K bytes, the address buses 2, 5, and 8 are composed of 11 bits. calculator 4
Since the 1 side has a predetermined address space (for example, 1 Mbyte), addresses of 12 bits or more are given to the address bus 12, and the common RAM
When the address decoder 11 detects that 1 is specified as a memory address, the chip select signal from the decoder 11 is sent to the common RAM selection circuit 1.
Occurs towards 0. Furthermore, since an 8-bit microcomputer is used in this example, data buses 3, 6, and 9 represent 8 bits. The common RAM selection circuit 10 is configured as shown in this figure.
controls so that only either the computer 41 side or the center device 43 side can use the common RAM 1. That is, the selection circuit 10 gives the right to use the common RAM 1 preferentially if either one generates the chip select ( ) signal, and
In addition to giving a signal to bus controller 4 or 7, chip select () is also applied to common RAM 1.
Control is performed so that the signal and read/write (WR/) signal 13 or 17 are provided from the bus side to which usage rights have been granted. In addition, the common RAM selection circuit 10 selects the common RAM 1 on the computer 41 side preferentially.
When using LOCK signal 15, select circuit 1
0, the center device 43 side is placed in a wait state, and conversely, if the center device 43 gives the override signal 19 to the selection circuit 10, the computer 41 side is placed in a wait state, and after the override signal 19 disappears, the computer 41 side is placed in a wait state. By using the common RAM 1 for the first time and generating the XACK signal 14 to the computer 41, it is possible to proceed to the next step. Further, in order to communicate mutual movements between the computer 41 side and the center device 43 side, a system reset signal 21 is given from the computer 41 side, and the center device 43
When data to be transmitted occurs from the side, an interrupt is sent
An iNT signal 16 is provided. Common RAM1 RAM configured in this way
The layout diagram is shown in Figure 1. The common RAM 1 is 2K bytes, and is divided into four areas as shown in a. That is, the upper two MBs, MB1,
MB2 is a communication mailbox (also simply called a mailbox), and the two lower rows are MD, MD1, and MD2.
are dedicated data memories as storage areas for Di data 46 and Do data 47, respectively. b shows an allocation diagram of each address a of the terminal 45 in the dedicated data memory MD. In addition, c is a layout diagram of the mailbox MB, which will be explained in detail later, and MBF
is flag control data, MBP is parameter data, and MBD is data area. FIG. 2 shows the communication order in this data transmission system. Figure a shows an example of cyclic communication T1 that is normally performed. That is, for example, the addresses of the terminal 45 are divided in advance into groups consisting of a predetermined number of addresses (however, each address within this group is ordered in advance), and block addresses B, B1 to B4 are assigned to each group. Assigned to the center device 43
However, block addresses B1 to B4 are changed from B1→B2→
B3→B4→B1...) is periodically repeated, and within the period indicated by each block address B1 to B4 in the figure, the address of each terminal belonging to the block is further specified as necessary. from the center device 43 to the terminal while sequentially specifying the
Do give data 47 or sequentially from each terminal 45
The center device 43 receives Di data and allows communication between terminals. FIG. 2b shows an example in which individual communication T2 is included in cyclic communication T1.
Communication T2 between the three terminals 45 with addresses a, a, am, and an and the center device 43 is performed within the period indicated by each terminal address a, am, and an in the figure, and then cyclic communication T1 is performed again. has returned to. These transmission controls have already been disclosed in the above-mentioned application (1), so a detailed explanation will be omitted. Returning to Figure 1, the dedicated data shown in Figure b
Di data 46 or Do data 47 in MD
are arranged in the order of the address a of the terminal 45, and Di
Data 46, that is, the terminal 45 obtained by the center device 43
The input data is sent to the common RAM by the center device 43 in the cyclic communication T1 shown in FIG.
1, and read out by the computer 41 when necessary. In addition, Do data 4 written to the dedicated data memory MD2 of the common RAM 1 by the computer 41
7 is read by the center device 43 and the second
It is used for terminal output data in the cyclic communication T1 shown in the figure. With this configuration, the Do data 47 or Di data 46 in the dedicated data memory MD can be shared in a common order by the computer 41 or the center device 43 every time it is controlled or every time data is received.
It is written in RAM 1 and pulled out and used when necessary, making it possible to perform extremely simple operations, that is, data exchange in a short time. However, in this cyclic communication T1 method,
If the cyclic cycle is long, even if Do data 47 is written to common RAM 1, it may not be possible to transmit it until the transmission timing of the data in that cycle is reached, or the Di data 4
Even if certain data changes in 6, the calculator 41
In order to detect this on the side, various operations must be performed, which has the disadvantage that detection is delayed. As a method for supplementing these, communication mailboxes MB, MB1, and MB2 shown in FIG. 1 can be used. MB as communication mailbox MB
The reason for preparing two mailboxes, 1 and MB2, is so that if one mailbox is in the process of receiving, the next mail can be written to the other mailbox. This mailbox MB is used in various other ways, but in individual communication T2 (Fig. 2), flag control data is used as shown in Fig. 1c.
The MBF section contains the presence/absence of data (referred to as main data for convenience) in the data area MBD in the mailbox, the data length of the main data, the specified classification of the contents of the main data, and whether the mailbox is in use. Flags and data indicating whether the message was transferred successfully or not are stored. Next, the parameter data MBP stores parameter data for indicating the details of the data format for the designated classification of the main data content. Also data area
The MBD contains main data, that is, from the computer 41 to the terminal 4.
Do data 47 and the address of the terminal to be urgently sent to 5, or urgently sent from the terminal 45 to the computer 41
Di data 46 (however, this data 46 is once received by the center device 43 from the terminal 45 through the above-mentioned cyclic communication T1, etc., and then transferred by the center device 43 to the mailbox MB) and the address of the terminal are stored. Ru. Such mailbox MB is calculated by computer 41→
Center device 43 or center device 43 → computer 4
1 and its contents are analyzed and interpreted. By using such a mailbox, you can, for example, send messages to terminals with addresses a, am, and an.
The computer 41 specifies the center device 43 to transmit the respective Do data 47, or the center device 43 receives a command from the Di data 46 (which is stored in the data memory MD1) obtained from the terminal 45. Di on terminal 45 with address an.
When a change occurs in the data 46 that requires emergency notification, the new Di data 46 is set to be transferred to the mailbox MB, and the interrupt iNT signal 16 shown in FIG. 4 is output to notify the computer 41. This enables high-speed data transmission between the computer 41 and the center device 43. Note that, as mentioned above, the center device 43 is the computer 41.
from address a, via mailbox MB.
When the Do data 47 for the terminals 45 at addresses a, am, and an are received, the cyclic communication T1 is interrupted as shown in FIG. Execute. After this individual communication T2 ends, cyclic communication T1
to return to. In addition to performing this individual communication T2, the center device 43 transfers the relevant Do data 47 to the common RAM
The new Do data is updated and stored in the corresponding address section in the dedicated data memory MD2 in the Do data memory MD2, and is reflected in the next cyclic communication T1. Note that the details of the transmission of the changed Di data 46 to the computer 41 side are described in the above-mentioned application (2). On the other hand, if this communication mailbox MB is used, any kind of control or data transmission is possible, but as shown in Figure 1c, various flag control data and parameter data are added. , because it is necessary to interpret such data, the dedicated data memory shown in Figure 1a is
Di data 46 and Do data 47 in MD1 and MD2
There is a problem in that data transmission takes time compared to direct exchange (however, this comparison excludes the time required for terminals to wait for their turn to update during cyclic communication). According to some calculations, there is a difference between reading Di data directly from the dedicated data memory MD1 and receiving Di data via the mailbox MB.
As an example of the latter procedure, compare the case where the computer puts a command into a mailbox, transmits the requested command to the center device, and then the center device writes Di data to the mailbox, which is then read out by the computer. Then it would take 10 times as long. This will reduce the processing power of the computer, and it is not desirable to use the mailbox MB extensively. However, as mentioned above, when transmitting change Di data 46 on the terminal side or urgently transmitting Do data 46 to a certain terminal,
7, it is more rational to use a mailbox, since using only the cyclic communication procedure will delay the final data transmission, which is not preferable. Dedicated data memory with cyclic communication
Di data 46 and Do data 47 in MD1 and MD2
can be used as is when displaying the operating status of a terminal, so it has the advantage of making programming extremely easy.

【Effect of the invention】

As is clear from the above explanation, according to the present invention, the computer and the center device can be connected to dual port RAM.
This common RAM is equipped with a communication mailbox for individual communication with terminals, and a dedicated data memory that allows direct access to Di and Do data for cyclic communication for each terminal. When it is necessary to transmit data at high speed using the communication mailbox and the dedicated data memory, the communication mailbox is used to preferentially transmit data in an individual communication method, and when high-speed transmission is not required, the dedicated data Using the cyclic communication method using memory, change Di data and fault Di data are sent from the terminal to the computer side via the center device, and Do data for control output is similarly sent from the computer side to the terminal side via the center device. As a result, flexible data transmission can be realized.

[Brief explanation of the drawing]

Figure 1 shows a common example as an embodiment of the present invention.
Similarly, FIG. 2 is an explanatory diagram of the communication order, FIG. 3 is a configuration diagram of the data transmission system, and FIG. 4 is a diagram of the configuration of the dual port RAM. 1... Common RAM, 41... Host computer (computer), 42... Dual port RAM, 43...
...Center device, 44...Transmission line, 45, 45-
1, 45-2...terminal, 46...Di data, 4
7...Do data, MB, MB1, MB2... Communication mailbox (mailbox), MD,
MD1, MD2...dedicated data memory, B...block address, a, a, am, an...terminal address, T1...cyclic communication, T2...individual communication.

Claims (1)

[Claims] 1. A center device, a plurality of address-specific terminals connected from the center device via a transmission path, and a host computer connected to the center device via a common RAM, and the center device is configured to perform data transmission. It performs control and exchanges data with the terminal, and the host computer is a common
A data transmission system in which data written in RAM is sent to a terminal via a center device, and the center device reads the data received from the terminal and written to the common RAM, thereby exchanging data with the terminal. In the common RAM, there is a data storage area for normal communication,
A data storage area (hereinafter referred to as a mailbox) used for emergency communication, etc. is provided, and the data storage area for normal communication is provided for each address of each terminal, and is provided for each address where the host computer sends and receives data from and to the terminal. The center device is configured to have a data area, and the mailbox is configured to store at least the address of a terminal related to emergency communication and the data to be sent to the terminal by the host computer. While reading and writing the communication data storage area, the address of each terminal or the corresponding address is repeatedly specified in a predetermined order to send and receive data, and at least the mailbox is read and the data is Prioritize giving and receiving,
A data transmission system characterized in that data transmission is performed by specifying a terminal having an address related to the emergency communication.