JPH0531971A - Image processing controller - Google Patents

Abstract

PURPOSE:To shorten time for inputting and clearing data common to each address in a memory means in an image processing controller such as page buffer memory. CONSTITUTION:A memory means having a plurality of memory elements, a memory element selection means for selecting any memory elements, and a memory means operation control means for operating the memory element selection means at all address divisions of each memory element simultaneously when a data common to each address of each memory element is to be inputted or when the whole data stored in the memory means are to be deleted are provided. When each memory element of the memory means is selected simultaneously, address areas common to each memory element can be accessed simultaneously, so that operation time of the memory means can be shorter comparing with the case where all addresses are to be accessed in sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus using a page buffer memory, and more particularly to a method of operating the page buffer memory.

[0002]

2. Description of the Related Art Conventionally, image data such as characters and graphic images from a data input device such as a computer or a word processor (hereinafter sometimes referred to as a host) is temporarily stored in a page buffer memory having a large storage capacity, and this data is stored at any time. The stored data is transferred to an image output terminal (hereinafter also referred to as IOT) such as a printer body or a CRT.

[0003]

By the way, the transfer of data from the host to the conventional page buffer memory and the erasing of the data stored in the page buffer memory are sequentially performed for each address.

However, it takes a long time to write data in the page buffer memory having a large storage capacity or to erase the data written in the page buffer memory. For example, with a 1 Mbyte page buffer memory, about 600 m
Seconds are required. Therefore, there is a problem that the total data processing time of the image processing apparatus becomes long.

Therefore, an object of the present invention is to shorten the time for inputting and clearing data common to each address of the storage means in the image processing control device such as a page buffer memory.

Another object of the present invention is to shorten the processing time of the image processing apparatus.

[0007]

The above objects of the present invention can be achieved by the following constitutions. That is, in an image processing apparatus that outputs input data from a data input device to an image processing apparatus main body via an image processing control device, a memory element selection for selecting one of storage means having a plurality of memory elements and each memory element. Means and memory means for simultaneously operating the memory element selecting means in all address sections of each memory element when inputting data common to each address of each memory element or when erasing all data stored in the memory means An image processing control device having an operation control means.

[0008]

When each memory element of the storage means is selected at the same time, the address part common to each memory element can be accessed at the same time. Therefore, the operation time of the storage means can be shortened as compared with the case of sequentially accessing all the addresses. You can

[0009]

Embodiments of the present invention will be described with reference to the drawings. An example of the image processing apparatus applied to the present invention is the printer shown in FIG. As shown in FIG. 1, the printer according to the present embodiment includes a host computer or word processor (hereinafter, also referred to as a data input device or host) 21 to a printer control device (hereinafter, also referred to as ESS) 2.
Image data is output to an image output terminal (hereinafter, also referred to as IOT) 4 of a printer main body (hereinafter, sometimes referred to as base machine) 1 via 0.

In the printer, as shown in FIG. 1, an information signal input by printing or image input from the data input device 21 is sent to a fluorescent display tube (not shown) of the IOT 4, and the information signal is sent to the fluorescent display tube. Is used to write on the photosensitive drum 2, and after being subjected to a series of processes, transferred onto a sheet. An outline of a base machine 1 using this fluorescent display tube will be described with reference to FIG.

A photosensitive drum 2 is arranged in the base machine 1. In the figure, the photoconductor 3 is formed in layers on the outer peripheral surface of the photoconductor drum 2. The photosensitive drum 2 is connected to a driving device (not shown) so as to rotate in the arrow direction. On the outer circumference of the photosensitive drum 2, a charge corotron 5, a fluorescent display tube built-in writing device 6, a condenser lens 7, a developing device 9, a transfer corotron 10, and a cleaning device 1.
1 is arranged.

In this image processing apparatus, as the photosensitive drum 2 rotates in the direction of the arrow, the photosensitive member 3 is uniformly charged by the charge corotron 5, and then is irradiated with light by the writing device 6 to generate an electrostatic latent image. An image is formed. The condenser lens 7 is an array of a large number of converging rod lenses for condensing light emitted from a large number of light emitting elements constituting the writing device 6 onto the photoconductor 3.

The photoconductor 3 on which the electrostatic latent image is formed is then developed by the developing device 9. Here, the toner image formed on the photoconductor 3 is transferred onto the paper by the transfer corotron 10, and the heat roll 18 and the pressure roll 19 are transferred.
It is heat-fixed between and carried out. On the other hand, the photoconductor 3 is cleaned by the cleaning device 11 and used again.

When this printer is used as a copying machine, the photoconductor 3 on the surface of the charged photosensitive drum 2 is exposed at the exposure location 13. Exposure location 13
A light image of an original document (not shown) placed on the platen glass 12 arranged on the upper surface of the base machine 1 is incident on the. For this purpose, the exposure lamp 15 and
A plurality of mirrors 16 and an optical lens 17 for transmitting the reflected light of the illuminated original surface are arranged, and a predetermined one of them is scanned for reading the original.

The circuit configuration of the ESS 20 of this embodiment is shown in FIG. The ESS 20 is controlled by the CPU 68000. The information input from the data input device 21 is temporarily stored in the RAM 23A of the memory 23 in the ESS 20 via the interface 22 of the Centro system or the like, and the bit map of the page buffer memory 25 having a capacity of 1M bytes from the RAM 23A in the memory 23. Be deployed to. Information in the page buffer memory 25 is stored in the video interface 26.
The video data 27 is sent to the IOT 4 via. When the printing of the data in the page buffer memory 25 is completed, the next input data from the data input device 21 is transferred from the RAM 23A of the memory 23 to the page buffer memory 25. In addition, based on the input information from the data input device 21, the ESS 20 uses the interface 2 such as RS232C.
The IOT 4 is instructed via the 9 to start the print operation, output tray to be used, which bin of the output tray to carry out or selection of the paper size, and the current operating mode of IOT 4 to IOT 4 is in the copy state. Information such as whether or not the printer is in a printing state or the number of used bins of the print paper output tray is received.

Therefore, for example, if the IOT 4 is in the copy state, the ESS 20 outputs an output standby signal for the printer to the data input device 21 via the interface 22 of the Centro system or the like. Data is transferred from the data input device 21 to the RAM 23A, is expanded into a bitmap in the page buffer memory 25, and after the expansion is completed, the data in the page buffer memory 25 is transferred to the IOT 4 according to the command 30, and a print operation is performed. It

The ROM 23B of the memory 23 has an ES
The S20 operating program and printer font information are stored. In addition, a non-volatile memory (NVM) 2
3C is also connected so that necessary data can be stored even when the power of the ESS 20 is turned off.

The ESS 20 is provided with an IC card insertion opening (not shown), and when an IC card is set in this IC card insertion opening, an appropriate ROM (within the IC card 62) is determined by the ID number of the IC card 62. (Not shown) is read out and output to the ESS 20 as print work information.

Since the ESS has the above circuit configuration, the IOT is operated based on a command from the operation panel of the data input device 21.
4 operation control is possible.

The ESS 20 also has an operation panel 39 similar to the console panel 8 of the base machine 1.
Is provided. That is, the ESS 20 is also provided with keys for setting the print density and the like in addition to keys for setting the number of sheets to be printed and magnification.

Although not shown, the base machine 1 adopts a distributed CPU architecture using serial communication centered on the main CPU. That is, in addition to the main CPU, the following CPU is prepared and connected to the communication line. Main CPU
Also plays a role of controlling these CPUs.

That is, the sorter CPU is used to display various information in Chinese characters on the liquid crystal display unit attached to the console panel 8 (FIG. 1) of the base machine 1 and to display an area for editing. A display CPU, a card CPU used when an IC card is used to specify the coordinates of an original, and a slave CPU for the interface between the base machine 1 and the data input device 21 are connected.

RAM of the main CPU (not shown)
Is connected to a data backup battery and is NVM-ized so that necessary data can be saved even when the power of the base machine 1 is turned off. Further, a well-known D / is provided in a driver circuit (not shown) of the main CPU.
It is equipped with an A (digital-analog) converter and a PWM (pulse width converter) and is connected to a high voltage power supply (HVPS) (not shown) to set the debeer bias of the developing device 9 shown in FIG. Setting of light emission amount of the lamp 15 The voltage value of the charge corotron 5 and the like is set.

Although not shown, the main CPU also controls a tray control section, a sorter, a paper size sensor, a temperature sensor, a light quantity sensor, a liquid crystal display section of the console panel, and the like.

4 and 8 are detailed views of the main part of the printer control apparatus shown in FIG. 4 and 8 are page buffer operation control circuits 3 not shown in FIG.
1, a memory element selection signal generation circuit 32, an address buffer 33, and a data buffer 35. Under the control of the CPU 68000, the page buffer operation control circuit 31 specifies an instruction to read / write data in the page buffer memory 25 and an operation mode of the memory element selection signal generation circuit 32 via an operation mode register (not shown). . The operation mode is, for example, CPU read /
A write operation mode, an output operation mode to the IOT 4, and a hege buffer memory all clear operation mode.

The memory element selection signal generating circuit 32 selects a memory element according to the designation of the operation mode register. Addressing of each page buffer memory 25 is CP
Address buffer 3 from the address signal from U68000
3 through 3.

The page buffer memory 25 used in this embodiment has a memory capacity of 1 Mbyte. The capacity of 1 Mbyte is configured by using a memory having a capacity of 256 K bits and 256 K × 1 bit as shown in FIG. 5A, and a capacity of 256 K bits and 32 K × 8 as shown in FIG. 5B. It may be configured using a bit-structured memory.

The capacity shown in FIG. 5A is 256 bits, 25 bits.
The ESS 20 using the page buffer memory 25 of 6K × 1 bit structure constitutes a circuit of a main part as shown in FIG.
A memory device having a capacity of 256K bits and 256K × 1 bit has eight memory devices each having a capacity of 256K × 1 bit as shown in the figure.
A 1M byte page buffer memory is formed by arranging the individual pieces into four rows. The operation of each memory element column is controlled by the memory element selection signal from the memory element selection signal generation circuit 32. This selection signal is composed of two address buffer signals. The eight memory elements in the uppermost row are selected by the CS ₀ signal, and the eight memory elements in the second, third, and lowermost rows are selected by the CS _{1 to} CS ₃ signals. Then, addressing of each memory element is performed by 18 address signals from the address buffer. FIG. 6 shows a time chart of the address signal and the memory selection signal to each memory element at the time of accessing the page buffer memory 25 during the normal write operation when the page buffer memory 25 is used. That is, for each address, an address is sequentially designated from the uppermost memory element group, and the data from the host 21 is written to the designated address of the memory when the write signal rises.

In the case of clearing all the written data, it takes a long time to sequentially perform the clearing operation while designating the address at the timing shown in FIG. The contents written to the memory 25 in the data clear operation are common to all addresses. Addressing is also common to all the lower 18 digits of each memory element column other than the memory element selection signals of the memory element select CS _{0 to} CS ₃ .

Therefore, by outputting the memory element selection signal at the same timing as the address designating signal of each memory element as shown in FIG. 7, a quarter of the normal page buffer memory 25 shown in FIG. 6 is accessed. Clear operation can be performed in time. If the time required for accessing the page buffer memory 25 in the normal write operation is 608 ms, the clear operation time is 152 ms.

Next, the page buffer memory 25 having a capacity of 256 Kbits and 32 K × 8 bits shown in FIG.
The case of using will be described.

FIG. 8 shows an E when the page buffer memory 25 having a capacity of 256 K bits and a structure of 32 K × 8 bits is used.
The circuit structure of the main part of SS20 is shown.

In this case, since 32K × 8-bit memory elements are composed of 32 memory elements, each 32K × 8-bit memory element has 32 (CS _{0 to} CS ₃₁ ) memories from the memory element selection signal generating circuit 32. The operation is controlled by the element selection signal. This memory element selection signal is composed of four address buffer signals. The address in each memory element is designated by 16 address buffer signals. A time chart of a normal write operation using the page buffer memory 25 is as shown in FIG. At this time, the selection signal of the memory selection element is 3
Two will be sequentially output. Therefore, in the clear operation, as shown in FIG.
If the memory element selection signal is output at the same timing as each address signal of, the time required for the normal page buffer memory 25 is 1/32. If the normal write operation time is 608 ms, the clear operation ends in 19 ms. That is, time of about 0.6 seconds can be saved for each print sheet.

In the above embodiment, the clearing operation of the data stored in the page buffer memory 25 has been described. However, the present invention is not limited to the clearing operation, but may be applied to a plurality of memory elements forming the page buffer memory 25. It can be applied when writing common data.
For example, the present invention can be applied to a read / write check for checking whether or not the memory operation is normally performed when the operation of the ESS 20 is started, and for writing a trademark or the like. It should be noted that writing of a trademark or the like can be performed at high speed by using a DMA (Direct Memory Access) capable of accessing the page buffer memory 25 without going through the CPU 68000. Further, it can be applied not only to the printer of the present invention but also to an image processing apparatus using a wide range page buffer memory such as a CRT.

[0035]

According to the present invention, the clear operation time of data written in a storage means such as a large-capacity page buffer memory, the read / write check time, the writing time of a trademark, etc. can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an embodiment of an image processing control device of the present invention.

FIG. 2 is a schematic diagram of an image processing control device main body according to an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of an image processing control device according to an embodiment of the present invention.

FIG. 4 is a detailed view of a main part of the image processing control device according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a page buffer memory according to an embodiment of the present invention.

FIG. 6 is a time chart of an address signal to a memory element and a memory element selection signal when a normal page buffer memory is accessed.

FIG. 7 is a time chart of an address signal to a memory element and a memory element selection signal when accessing a page buffer memory according to an embodiment of the present invention.

FIG. 8 is a detailed view of a main part of the image processing control apparatus according to the embodiment of the present invention.

FIG. 9 is a time chart of an address signal to a memory element and a memory element selection signal when a normal page buffer memory is accessed.

FIG. 10 is a time chart of an address signal to a memory element and a memory element selection signal when accessing a page buffer memory according to an embodiment of the present invention.

[Explanation of symbols]

 1 base machine 4 IOT 20 ESS 21 host 25 page buffer memory

Claims (1)

Claim: What is claimed is: 1. An image processing apparatus for outputting input data from a data input device to a main body of the image processing apparatus via an image processing control apparatus, the storage means having a plurality of memory elements, and each memory. A memory element selecting means for selecting any one of the elements and a memory element selecting means for inputting data common to each address of each memory element or for erasing all the data stored in the storage means. An image processing control device, comprising: storage means operation control means that operates simultaneously in all the address sections.