JPH053196A - Semiconductor integrated circuit element and mounting thereof on wiring board - Google Patents

Semiconductor integrated circuit element and mounting thereof on wiring board

Info

Publication number
JPH053196A
JPH053196A JP3152969A JP15296991A JPH053196A JP H053196 A JPH053196 A JP H053196A JP 3152969 A JP3152969 A JP 3152969A JP 15296991 A JP15296991 A JP 15296991A JP H053196 A JPH053196 A JP H053196A
Authority
JP
Japan
Prior art keywords
wiring board
integrated circuit
solder
semiconductor integrated
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3152969A
Other languages
Japanese (ja)
Inventor
Kazuo Ikenaga
和夫 池永
Mutsusada Itou
睦禎 伊藤
Katsuya Kosuge
克也 小菅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3152969A priority Critical patent/JPH053196A/en
Publication of JPH053196A publication Critical patent/JPH053196A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable semiconductor integrated circuit elements different in weight or the like to be well mounted on the same wiring board. CONSTITUTION:Solder bumps 2, which are formed on the electrodes of semiconductor integrated circuit elements 1a, 1b, and 1c that are mounted on a common wiring board 3 by soldering and different from each other in number of electrodes solder, are formed of material of the same composition. The wiring board 3 is so constituted as to make a load imposed on each electrode of the semiconductor elements 1a, 1b, and 1c equal or nearly equal, and these semiconductor integrated circuit elements 1a, 1b, and 1c are mounted on the common wiring board 3 coated with solder 5 lower than the solder bump 2 in melting point by soldering through a reflow method. By this setup, a short circuit is prevented from occurring between electrodes or wirings even if they are arranged fine in pitch, so that semiconductor circuit elements can be well mounted by soldering.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、複数の半導体集積回
路素子(以下、「IC」と記す)を同一の配線基板に確
実に半田付けできる実装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method capable of reliably soldering a plurality of semiconductor integrated circuit elements (hereinafter referred to as "IC") to the same wiring board.

【0002】[0002]

【従来の技術】従来のこの種実装方法について、図4乃
至図6を用いて説明する。図4において、IC1(この
場合はフリップチップで表しているが)の表面の複数の
各電極に形成された半田バンプ2と、配線基板3の表面
に形成した電気回路配線4に被着されたそれぞれの半田
5とをリフローにより溶着して、IC1を配線基板3に
実装するようにしている。しかし、それぞれの半田バン
プ2の高さにはばらつきがあり、不揃いであり、また、
配線基板3の方の半田5の盛り具合には一層不揃いが生
じていて、このような状態で両者を半田付けした場合に
は、ある半田バンプ2は配線基板3に接続されないこと
がしばしば生じた。このため、図5に示したように、I
C1の背面(上面)全面に重り6を載せてリフローし、
半田付けして、このような不良接続が生じないようにし
ている。
2. Description of the Related Art A conventional mounting method of this type will be described with reference to FIGS. In FIG. 4, the solder bumps 2 are formed on each of a plurality of electrodes on the surface of the IC 1 (in this case, represented by a flip chip) and the electric circuit wiring 4 formed on the surface of the wiring board 3. The respective solders 5 are welded by reflow to mount the IC 1 on the wiring board 3. However, the heights of the solder bumps 2 are not uniform, and are different,
When the solder 5 on the wiring board 3 is more uneven, the solder bumps 2 are often not connected to the wiring board 3 when both are soldered in such a state. . Therefore, as shown in FIG.
Place the weight 6 on the entire back surface (upper surface) of C1 and reflow,
It is soldered to prevent such a bad connection.

【0003】しかし、このような実装方法では、ICの
種類によっては必要以上の荷重が掛かり、半田バンプ2
及び半田5がリフローで溶融し、形成された接続部分7
は半田がはみ出して、ICの電極ピッチが150μm程
度或いはそれ以下のようなファインピッチである場合に
は、電極間或いは相隣る配線を短絡してしまい、実装不
良が発生する。また、このように配線基板3にIC1を
実装する度に、IC1の背面に重り6を載せることは、
実装作業を煩雑化し、非能率的である。
However, in such a mounting method, an excessive load is applied depending on the type of IC, and the solder bump 2
And the connection portion 7 formed by melting the solder 5 by reflow
In the case where the solder squeezes out and the electrode pitch of the IC is a fine pitch of about 150 μm or less, the wiring between the electrodes or adjacent wiring is short-circuited, and a mounting defect occurs. In addition, the weight 6 is placed on the back surface of the IC 1 each time the IC 1 is mounted on the wiring board 3 as described above.
Mounting work is complicated and inefficient.

【0004】[0004]

【発明が解決しようとする課題】従って、この発明は、
前述のような重りを用いることなく、しかし、配線基板
上に配置される各種ICが相隣る電極間或いは相隣る配
線を短絡しないように、しかも確実に実装しようとする
ものである。
Therefore, the present invention is
It is an object of the present invention to mount the ICs without using the weight as described above, but surely so that various ICs arranged on the wiring board do not short-circuit between adjacent electrodes or adjacent wirings.

【0005】[0005]

【課題を解決するための手段】そのためこの発明は、共
通の配線基板に半田付け実装する、電極数が異なる複数
の半導体集積回路素子の電極に形成した半田を同一の組
成で構成し、そして各半導体集積回路素子の1電極当た
りの荷重を同等又は略々同等に構成した。そしてこれら
の半導体集積回路素子を前記共通の配線基板に半田付け
実装する場合に、前記電極に形成した半田の融点より低
い融点の半田が予め被着されている前記共通の配線基板
に前記複数の半導体集積回路素子を半田付け実装するよ
うにして前述の課題を解決した。
Therefore, according to the present invention, the solder formed on the electrodes of a plurality of semiconductor integrated circuit devices having different numbers of electrodes, which are mounted by soldering on a common wiring board, has the same composition, and The load per electrode of the semiconductor integrated circuit element was configured to be equal or almost equal. When these semiconductor integrated circuit elements are mounted by soldering on the common wiring board, the plurality of the plurality of wiring patterns are attached to the common wiring board to which a solder having a melting point lower than that of the solder formed on the electrodes is previously applied. The above-mentioned problems were solved by mounting the semiconductor integrated circuit element by soldering.

【0006】[0006]

【作用】従って、この発明のIC及びそれらのICの配
線基板への実装方法によれば、たとえファインピッチで
電極が形成されたICでも、また大きさ、重さが異なる
ICでも、それらを混在させて同一配線基板にリフロー
で実装しても、そのICの相隣る電極間、或いはまた相
隣る配線間を短絡させるような事象が生じることがな
い。
Therefore, according to the IC of the present invention and the method of mounting these ICs on the wiring board, both ICs having electrodes formed at a fine pitch and ICs having different sizes and weights are mixed. Even if the ICs are mounted on the same wiring board by reflow, there is no occurrence of a short circuit between adjacent electrodes of the IC or between adjacent wirings.

【0007】[0007]

【実施例】以下、この発明のICの配線基板への実装方
法を図1乃至図3を用いて説明する。図1は複数のIC
が実装された共通の配線基板を示す一部平面図であり、
図2は図1のA−A線上における断面図であり、図3は
図2の状態でリフローした結果、ICと電気回路配線が
接続された状態を示す断面図である。なお、図4乃至図
6と同一部分には同一の符号を付した。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of mounting an IC of the present invention on a wiring board will be described below with reference to FIGS. Figure 1 shows multiple ICs
Is a partial plan view showing a common wiring board mounted with,
2 is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 3 is a cross-sectional view showing a state where the IC and the electric circuit wiring are connected as a result of the reflow in the state of FIG. The same parts as those in FIGS. 4 to 6 are designated by the same reference numerals.

【0008】例えば、ガラスエポキシ樹脂からできてい
る共通の配線基板3は、これらの図では、極一部だけ表
していて、その表面には複数の電気回路配線4が、例え
ば、150μmのピッチで形成されている。これらの電
気回路配線4には半田5が被着されている。このような
配線基板3には、大きさ、重量、電極数或いは電極ピッ
チ等が異なる複数のIC1a、1b、1cが、他の電気
回路を構成する電気部品と共に高密度実装されるのであ
るが、図1ではICを3個だけ搭載した状態を示した。
For example, a common wiring board 3 made of glass epoxy resin shows only a part of these figures, and a plurality of electric circuit wirings 4 are formed on the surface thereof at a pitch of, for example, 150 μm. Has been formed. Solder 5 is attached to these electric circuit wirings 4. On such a wiring board 3, a plurality of ICs 1a, 1b, 1c having different sizes, weights, numbers of electrodes, electrode pitches, etc. are mounted with high density together with other electric components constituting other electric circuits. FIG. 1 shows a state in which only three ICs are mounted.

【0009】図では、これらのIC1a、1b、1cを
フリップチップ型半導体素子で表した。IC1aは10
個の電極を、IC1bは6個の電極を、そしてIC1c
は16個の電極を有し、それぞれの電極には半田バンプ
2が形成されている。また、電気回路配線4上の半田5
及び半田バンプ2の半田には、後述のような鉛と錫の割
合の組成の半田を用いた。
In the figure, these ICs 1a, 1b, 1c are represented by flip-chip type semiconductor devices. IC1a is 10
6 electrodes for IC1b and IC1c for IC1b
Has 16 electrodes, and the solder bumps 2 are formed on the respective electrodes. Also, the solder 5 on the electrical circuit wiring 4
As the solder of the solder bump 2, a solder having a composition of lead and tin as described below was used.

【0010】このような共通の配線基板3の電気回路配
線4及びまたは半田バンプ2にフラックスを塗布し、そ
れらの電気回路配線4上に各半田バンプ2が正確に載る
ようにIC1a、1b、1cを搭載し、加熱炉に通し、
例えば、約216°Cで加熱(リフロー)する。そうす
ると、半田5が完全に溶融し、半田バンプ2の半田は半
溶融の状態で、両者が溶着する。
Flux is applied to the electric circuit wirings 4 and / or the solder bumps 2 of the common wiring board 3 as described above, and the ICs 1a, 1b, 1c are mounted so that the solder bumps 2 are accurately mounted on the electric circuit wirings 4. Equipped with, through a heating furnace,
For example, heating (reflow) is performed at about 216 ° C. Then, the solder 5 is completely melted, and the solder of the solder bump 2 is welded in a semi-molten state.

【0011】この実装方法において、図6で指摘した不
都合な短絡を防止するために最も重要な要件は、1電極
当たりの荷重である。この発明者等は、IC1aとし
て、6mm角のシリコンチップで80個の電極を有する
ICで電気回路配線4と半田バンプ2との接続状態を確
かめた。この場合の電気回路配線4上の半田5には、例
えば、鉛と錫との比が6:4の割合の組成の半田を用
い、また半田バンプ2の半田には、例えば、鉛と錫との
比が1:9の割合の組成の半田を用い、例えば、約21
6°Cで加熱したところ、図3に示したように、半田5
及び半田バンプ2は良好な状態で溶着し、電極間及び電
気回路配線間を短絡しないことを確認した。そこでこの
IC1aの1電極当たりの荷重を計ったところ、約0.
48mgであった。
In this mounting method, the most important requirement for preventing the inconvenient short circuit pointed out in FIG. 6 is the load per electrode. The present inventors confirmed the connection state between the electric circuit wiring 4 and the solder bump 2 with an IC having a 80 mm electrode as a 6 mm square silicon chip as the IC 1 a. In this case, for the solder 5 on the electric circuit wiring 4, for example, a solder having a composition of a ratio of lead and tin of 6: 4 is used, and for the solder of the solder bump 2, for example, lead and tin are used. The solder having the composition of the ratio of 1: 9 is used, for example, about 21
When heated at 6 ° C, solder 5
It was also confirmed that the solder bumps 2 were welded in a good state and did not short-circuit between the electrodes and between the electric circuit wirings. Then, when the load per electrode of this IC 1a was measured, it was about 0.
It was 48 mg.

【0012】また、IC1bとして、3mm角のシリコ
ンチップで40個の電極を有するICを、前記IC1a
と同一の各半田の組成にして、同一の温度で加熱し、両
者の溶着状態を確認したところ、一部分に接続されてい
ない電極があることが認められた。そこで、このIC1
bの1電極当たりの荷重を計ったところ、約0.26m
gであった。それ故に、発明者等はこのICの背面に銅
をメッキし、1電極当たりの荷重を、IC1aと略々同
等の0.5mgに増量して、再度、前記の条件と同一条
件で実験したところ、図3に示したように、半田5及び
半田バンプ2は良好な状態で溶着していることが確認で
きた。
As the IC 1b, an IC having 40 electrodes on a 3 mm square silicon chip is referred to as the IC 1a.
When the same solder composition was used and the same temperature was applied and the welding state of both was confirmed, it was found that some electrodes were not connected. Therefore, this IC1
When the load per electrode of b was measured, it was about 0.26 m
It was g. Therefore, the inventors plated copper on the back surface of this IC, increased the load per electrode to 0.5 mg, which is almost equal to that of IC1a, and conducted an experiment again under the same conditions as described above. As shown in FIG. 3, it was confirmed that the solder 5 and the solder bump 2 were welded in a good state.

【0013】更にまた、IC1cとして、9mm角のシ
リコンチップで120個の電極を有するICを、前記I
C1aと同一の各半田の組成にして、同一の温度で加熱
し、両者の溶着状態を確認したところ、一部分の電極間
及び電気回路配線間が短絡されている状態が認められ
た。そこで、このIC1cの1電極当たりの荷重を計っ
たところ、約0.65mgであった。それ故に、発明者
等はこのICの背面を研削し、1電極当たりの荷重を、
IC1aと略々同等の0.5mgに減量して、再度、前
記の条件と同一条件で実験したところ、半田5及び半田
バンプ2は良好な状態で溶着していることが確認でき
た。
Further, as the IC 1c, an IC having 120 electrodes on a 9 mm square silicon chip is
When the composition of each solder was the same as that of C1a, heating was performed at the same temperature, and the welding state of both was confirmed, it was found that a part of the electrodes and the electric circuit wiring were short-circuited. Then, when the load per electrode of this IC1c was measured, it was about 0.65 mg. Therefore, the present inventors ground the back surface of this IC to reduce the load per electrode,
When the amount was reduced to 0.5 mg, which is almost the same as that of IC1a, and an experiment was conducted again under the same conditions as described above, it was confirmed that the solder 5 and the solder bump 2 were welded in a good state.

【0014】従って、これらの大きさ、重さ、電極数等
の外観が異なるIC1a、1b、1cでも、1電極当た
りの荷重を同等又は略々同等に構成し、同一の半田組成
にしておけば、これらのICを共通の配線基板3に同時
に実装しても、良好な接続状態が得られることが確認で
きた。
Therefore, even in the ICs 1a, 1b, 1c having different appearances such as size, weight, number of electrodes, etc., if the load per electrode is configured to be equal or substantially equal and have the same solder composition. It has been confirmed that even if these ICs are simultaneously mounted on the common wiring board 3, a good connection state can be obtained.

【0015】前記の実験では、3mm角のシリコンチッ
プに銅を付着して重量を増し、9mm角のシリコンチッ
プは研磨して減量させたが、このような作業は個々のシ
リコンチップについて行うには、非能率であるので、共
通の配線基板に実装するICの種類が判っていれば、そ
れぞれのICの元になる集積回路が形成されているシリ
コンウエハの裏面に重量物をメッキ、蒸着等の手段で被
着し、或いはその裏面を研削して、それらのウエハをダ
イシングすれば、個々のチップの1電極当たりの荷重が
所定の荷重にすることができる。
In the above experiment, the weight was increased by adhering copper to a 3 mm square silicon chip, and the 9 mm square silicon chip was polished to reduce the weight. However, since it is inefficient, if the type of IC to be mounted on a common wiring board is known, plating, vapor deposition, etc. of a heavy object on the back surface of the silicon wafer on which the integrated circuit that is the basis of each IC is formed. If the wafer is adhered by means or the back surface thereof is ground and the wafers are diced, the load per electrode of each chip can be set to a predetermined load.

【0016】また前記の実施例では、ICとしてフリッ
プチップ型ICを例に挙げて説明したが、この発明はこ
の他、例えば、QFJ型のような表面実装型ICにも適
用できる。
Further, in the above-mentioned embodiment, the flip-chip type IC has been described as an example of the IC, but the present invention can also be applied to a surface mounting type IC such as the QFJ type.

【0017】[0017]

【発明の効果】以上の説明から明らかなように、この発
明のIC及びそれらのICの配線基板への実装方法によ
れば、たとえファインピッチで電極が形成されたICで
も、また大きさ、重さ等が異なるICでも、それらを混
在させて同一配線基板にリフローで実装しても、そのI
Cの相隣る電極間、或いはまた相隣る配線間を短絡させ
るような事象が生じることがない。また同一の温度で一
括リフローできるので、作業能率が上がる。そして又、
全てのICが最適条件でリフローされているため、信頼
性、歩留りも向上する等数々の優れた効果が得られる。
As is apparent from the above description, according to the IC of the present invention and the method of mounting those ICs on the wiring board, even if the ICs have electrodes formed at a fine pitch, the size, weight and Even if ICs with different sizes are mixed and mounted on the same wiring board by reflow, the I
An event that short-circuits the electrodes adjacent to each other or the wires adjacent to each other does not occur. Moreover, since the batch reflow can be performed at the same temperature, the work efficiency is improved. And again
Since all the ICs are reflowed under the optimum conditions, various excellent effects such as improvement in reliability and yield can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】複数のICが実装された共通の配線基板を示す
一部平面図である。
FIG. 1 is a partial plan view showing a common wiring board on which a plurality of ICs are mounted.

【図2】図1のA−A線上における断面図である。FIG. 2 is a cross-sectional view taken along the line AA of FIG.

【図3】図2の状態でリフローした結果、半導体集積回
路素子と電気回路配線が接続された状態を示す断面図で
ある。
FIG. 3 is a cross-sectional view showing a state where the semiconductor integrated circuit element and the electric circuit wiring are connected as a result of reflowing in the state of FIG.

【図4】半導体集積回路素子と配線基板の状態を説明す
るための断面図である。
FIG. 4 is a sectional view for explaining a state of a semiconductor integrated circuit element and a wiring board.

【図5】従来技術の半導体集積回路素子の配線基板への
実装方法を説明するための断面図である。
FIG. 5 is a cross-sectional view for explaining a method for mounting a semiconductor integrated circuit element of a conventional technique on a wiring board.

【図6】図5の実装方法で半導体集積回路素子を配線基
板に実装した状態を示す断面図である。
6 is a cross-sectional view showing a state in which a semiconductor integrated circuit element is mounted on a wiring board by the mounting method of FIG.

【符号の説明】[Explanation of symbols]

1 半導体集積回路素子(IC) 2 半田バンプ 3 配線基板 4 電気回路配線 5 半田 6 重り 7 接続部分 1 Semiconductor integrated circuit element (IC) 2 Solder bump 3 wiring board 4 electrical circuit wiring 5 solder 6 weights 7 connection

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/34 H 9154−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/34 H 9154-4E

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】共通の配線基板に半田付け実装する、電極
数が異なる複数の半導体集積回路素子の電極に形成した
半田を同一の組成で構成し、そして各半導体集積回路素
子の1電極当たりの荷重を同等又は略々同等に構成した
ことを特徴とする半導体集積回路素子。
1. A solder formed on electrodes of a plurality of semiconductor integrated circuit elements having different numbers of electrodes to be mounted by soldering on a common wiring substrate, and having the same composition, and one electrode of each semiconductor integrated circuit element A semiconductor integrated circuit device having a load which is equal or substantially equal.
【請求項2】電極数が異なる複数の半導体集積回路素子
を共通の配線基板に半田付け実装する場合に、これらの
各半導体集積回路素子の1電極当たりの荷重が同等又は
略々同等であり、そして各電極に形成した半田の組成が
同一であるように構成し、一方前記配線基板に予め被着
した半田の融点が前記電極に形成した半田の融点より低
く設定し、このような配線基板に前記複数の半導体集積
回路素子を半田付け実装することを特徴とする半導体集
積回路素子の配線基板への実装方法。
2. When a plurality of semiconductor integrated circuit elements having different numbers of electrodes are mounted by soldering on a common wiring board, the load per electrode of each of these semiconductor integrated circuit elements is equal or substantially equal, Then, the composition of the solder formed on each electrode is configured to be the same, while the melting point of the solder previously deposited on the wiring board is set lower than the melting point of the solder formed on the electrode. A method for mounting a semiconductor integrated circuit device on a wiring board, comprising mounting the plurality of semiconductor integrated circuit devices by soldering.
JP3152969A 1991-06-25 1991-06-25 Semiconductor integrated circuit element and mounting thereof on wiring board Pending JPH053196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3152969A JPH053196A (en) 1991-06-25 1991-06-25 Semiconductor integrated circuit element and mounting thereof on wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3152969A JPH053196A (en) 1991-06-25 1991-06-25 Semiconductor integrated circuit element and mounting thereof on wiring board

Publications (1)

Publication Number Publication Date
JPH053196A true JPH053196A (en) 1993-01-08

Family

ID=15552112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3152969A Pending JPH053196A (en) 1991-06-25 1991-06-25 Semiconductor integrated circuit element and mounting thereof on wiring board

Country Status (1)

Country Link
JP (1) JPH053196A (en)

Similar Documents

Publication Publication Date Title
US6259608B1 (en) Conductor pattern for surface mount devices and method therefor
JP2682807B2 (en) Soldering method and solder bump forming method
KR970005526B1 (en) Method for forming solder bump interconnections to a solder plated circuit trace
US5564617A (en) Method and apparatus for assembling multichip modules
US5705858A (en) Packaging structure for a hermetically sealed flip chip semiconductor device
US6657124B2 (en) Advanced electronic package
US5926731A (en) Method for controlling solder bump shape and stand-off height
US20090289360A1 (en) Workpiece contact pads with elevated ring for restricting horizontal movement of terminals of ic during pressing
US20030030149A1 (en) Semiconductor device having solder bumps reliably reflow solderable
US7923125B2 (en) Apparatus for solder crack deflection
JP2003007960A5 (en)
US20020076910A1 (en) High density electronic interconnection
KR101421907B1 (en) Electronic-component mounted body, electronic component, and circuit board
JP3143441B2 (en) Solder bump input / output pads for surface mount circuit devices
JP3364266B2 (en) Bump formation method
US6402012B1 (en) Method for forming solder bumps using a solder jetting device
JPH053196A (en) Semiconductor integrated circuit element and mounting thereof on wiring board
JP2002076605A (en) Semiconductor module and circuit board for connecting semiconductor device
US6531664B1 (en) Surface mount devices with solder
JP3257011B2 (en) Method of assembling semiconductor device
JP3544439B2 (en) Connection pins and board mounting method
JPH053197A (en) Mounting method of semiconductor integrated circuit element on wiring board
JPH05136201A (en) Electrode for semiconductor device and mounting body
JP3006957B2 (en) Semiconductor device package
JP2011216813A (en) Solder joint method, semiconductor device and method of manufacturing the same