JPH053197A - Mounting method of semiconductor integrated circuit element on wiring board - Google Patents

Mounting method of semiconductor integrated circuit element on wiring board

Info

Publication number
JPH053197A
JPH053197A JP3152970A JP15297091A JPH053197A JP H053197 A JPH053197 A JP H053197A JP 3152970 A JP3152970 A JP 3152970A JP 15297091 A JP15297091 A JP 15297091A JP H053197 A JPH053197 A JP H053197A
Authority
JP
Japan
Prior art keywords
solder
wiring board
semiconductor integrated
integrated circuit
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3152970A
Other languages
Japanese (ja)
Inventor
Kazuo Ikenaga
和夫 池永
Mutsusada Itou
睦禎 伊藤
Katsuya Kosuge
克也 小菅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3152970A priority Critical patent/JPH053197A/en
Publication of JPH053197A publication Critical patent/JPH053197A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To enable semiconductor integrated circuit elements different from each other in weight to be well mounted on the same wiring board. CONSTITUTION:Solder bumps, which are formed on the electrodes of ICs 1a, 1b, and 1c different from each other in weight, are made to change in solder composition corresponding to a load imposed on each of the electrodes, and these ICs are mounted on a common wiring board 3 by soldering through a reflow method. By this setup, a short circuit is prevented from occurring between electrodes or wirings even if they are arranged fine in pitch, so that semiconductor integrated circuit elements can be well mounted by soldering.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、複数の半導体集積回
路素子(以下、「IC」と記す)を同一の配線基板に確
実に半田付けできる実装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method capable of reliably soldering a plurality of semiconductor integrated circuit elements (hereinafter referred to as "IC") to the same wiring board.

【0002】[0002]

【従来の技術】従来のこの種実装方法について、図5乃
至図7を用いて説明する。図5において、IC1(この
場合はフリップチップで表しているが)の表面の複数の
各電極に形成された半田バンプ2と、配線基板3の表面
に形成した電気回路配線4に被着されたそれぞれの半田
5とをリフローにより溶着して、IC1を配線基板3に
実装するようにしている。しかし、それぞれの半田バン
プ2の高さにはばらつきがあり、不揃いであり、また、
配線基板3の方の半田5の盛り具合には一層不揃いが生
じていて、このような状態で両者を半田付けした場合に
は、ある半田バンプ2は配線基板3に接続されないこと
がしばしば生じた。このため、図7に示したように、I
C1の背面(上面)全面に重り6を載せてリフローし、
半田付けして、このような不良接続が生じないようにし
ている。
2. Description of the Related Art A conventional mounting method of this type will be described with reference to FIGS. In FIG. 5, the solder bumps 2 are formed on each of the plurality of electrodes on the surface of the IC 1 (in this case, represented by a flip chip) and the electric circuit wiring 4 formed on the surface of the wiring board 3. The respective solders 5 are welded by reflow to mount the IC 1 on the wiring board 3. However, the heights of the solder bumps 2 are uneven and uneven, and
When the solder 5 on the wiring board 3 is more uneven, the solder bumps 2 are often not connected to the wiring board 3 when both are soldered in such a state. .. Therefore, as shown in FIG.
Place the weight 6 on the entire back surface (upper surface) of C1 and reflow.
It is soldered to prevent such a bad connection.

【0003】しかし、このような実装方法では、ICの
種類によっては必要以上の荷重が掛かり、半田バンプ2
及び半田5がリフローで溶融し、形成された接続部分7
は半田がはみ出して、ICの電極ピッチが150μm程
度或いはそれ以下のようなファインピッチである場合に
は、電極間或いは相隣る配線を短絡してしまい、実装不
良が発生する。また、このように配線基板3にIC1を
実装する度に、IC1の背面に重り6を載せることは、
実装作業を煩雑化し、非能率的である。
However, in such a mounting method, an excessive load is applied depending on the type of IC, and the solder bump 2
And the connection portion 7 formed by melting the solder 5 by reflow
When the solder is squeezed out and the IC electrode pitch is a fine pitch such as about 150 μm or less, the wiring between the electrodes or adjacent wiring is short-circuited, and a mounting defect occurs. In addition, the weight 6 is placed on the back surface of the IC 1 each time the IC 1 is mounted on the wiring board 3 as described above.
It makes mounting work complicated and inefficient.

【0004】[0004]

【発明が解決しようとする課題】従って、この発明は、
前述のような重りを用いることなく、しかし、配線基板
上に配置される各種ICが相隣る電極間或いは相隣る配
線を短絡しないように、しかも確実に実装しようとする
ものである。
Therefore, the present invention is
The above-described weight is not used, but various ICs arranged on the wiring board are mounted surely so that adjacent electrodes or adjacent wirings are not short-circuited.

【0005】[0005]

【課題を解決するための手段】そのためこの発明は、重
量が異なる複数のICを共通の配線基板に半田付け実装
する場合に、これらの各IC毎に、そのICの1電極当
たりの荷重に応じて、各ICの電極に形成する半田バン
プの半田組成を変え、そして実装しようとする全てのI
Cの半田バンプの半田の融点を、配線基板に被着した半
田の融点よりも高く調整して、これら複数のICを前記
配線基板に半田付け実装するようにして前述の課題を解
決した。
Therefore, according to the present invention, when a plurality of ICs having different weights are mounted on a common wiring board by soldering, each of the ICs is loaded with a load per electrode of the IC. By changing the solder composition of the solder bumps formed on the electrodes of each IC, and
The melting point of the solder of the C solder bump is adjusted to be higher than the melting point of the solder adhered to the wiring board, and the plurality of ICs are soldered and mounted on the wiring board to solve the above-mentioned problems.

【0006】[0006]

【作用】従って、この発明のICの配線基板への実装方
法によれば、たとえファインピッチで電極が形成された
ICでも、また大きさ、重さが異なるICでも、それら
を混在させて同一配線基板にリフローで実装しても、そ
のICの相隣る電極間、或いはまた相隣る配線間を短絡
させるような事象が生じることがない。
Therefore, according to the method of mounting an IC on a wiring board of the present invention, even if the ICs have electrodes formed at a fine pitch, or ICs having different sizes and weights, they are mixed and the same wiring is provided. Even if the IC is mounted on the substrate by reflow, an event that short-circuits between adjacent electrodes of the IC or between adjacent wirings does not occur.

【0007】[0007]

【実施例】以下、この発明のICの配線基板への実装方
法を図1乃至図3を用いて説明する。図1は複数のIC
が実装された共通の配線基板を示す一部平面図であり、
図2は図1のA−A線上における断面図であり、図3は
図2の状態でリフローした結果、ICと電気回路配線が
接続された状態を示す断面図であり、図4は鉛・錫半田
の状態図である。なお、図5乃至図7と同一部分には同
一の符号を付した。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for mounting an IC of the present invention on a wiring board will be described below with reference to FIGS. Figure 1 shows multiple ICs
Is a partial plan view showing a common wiring board mounted with,
2 is a cross-sectional view taken along the line AA of FIG. 1, FIG. 3 is a cross-sectional view showing a state where the IC and the electric circuit wiring are connected as a result of reflowing in the state of FIG. 2, and FIG. It is a state diagram of tin solder. The same parts as those in FIGS. 5 to 7 are designated by the same reference numerals.

【0008】例えば、ガラスエポキシ樹脂からできてい
る共通の配線基板3は、これらの図では、極一部だけ表
していて、その表面には複数の電気回路配線4が、例え
ば、150μmのピッチで形成されている。これらの電
気回路配線4には半田5が被着されている。このような
配線基板3には、大きさ、重量、電極数或いは電極ピッ
チ等が異なる複数のIC1a、1b、1cが、他の電気
回路を構成する電気部品と共に高密度実装されるのであ
るが、図1ではICを3個だけ搭載した状態を示した。
For example, a common wiring board 3 made of glass epoxy resin shows only a part of these figures, and a plurality of electric circuit wirings 4 are formed on the surface thereof at a pitch of, for example, 150 μm. Has been formed. Solder 5 is attached to these electric circuit wirings 4. On such a wiring board 3, a plurality of ICs 1a, 1b, 1c having different sizes, weights, numbers of electrodes, electrode pitches, etc. are mounted at high density together with electric components constituting other electric circuits. FIG. 1 shows a state where only three ICs are mounted.

【0009】図では、これらのIC1a、1b、1cを
フリップチップ型半導体素子で表した。IC1aは10
個の電極を、IC1bは6個の電極を、そしてIC1c
は16個の電極を有し、それぞれの電極には半田バンプ
2が形成されている。また、電気回路配線4上の半田5
及び半田バンプ2の半田には、後述のような鉛と錫の割
合の組成の半田を用いた。
In the figure, these ICs 1a, 1b, 1c are represented by flip-chip type semiconductor devices. IC1a is 10
6 electrodes for IC1b, and IC1c for IC1b
Has 16 electrodes, and the solder bumps 2 are formed on the respective electrodes. Also, the solder 5 on the electrical circuit wiring 4
As the solder of the solder bump 2, a solder having a composition of lead and tin as described below was used.

【0010】このような共通の配線基板3の電気回路配
線4及びまたは半田バンプ2にフラックスを塗布し、そ
れらの電気回路配線4上に各半田バンプ2が正確に載る
ようにIC1a、1b、1cを搭載し、加熱炉に通し、
183°C〜230°Cの範囲の温度、例えば、約21
6°Cで加熱(リフロー)する。そうすると、半田5が
完全に溶融し、半田バンプ2の半田は半溶融の状態で、
両者が溶着する。
Flux is applied to the electric circuit wirings 4 and / or the solder bumps 2 of the common wiring board 3 as described above, and the ICs 1a, 1b, 1c are mounted so that the solder bumps 2 are accurately mounted on the electric circuit wirings 4. Equipped with, through a heating furnace,
A temperature in the range of 183 ° C to 230 ° C, for example about 21
Heat (reflow) at 6 ° C. Then, the solder 5 is completely melted, and the solder of the solder bump 2 is semi-molten,
Both are welded.

【0011】この実装方法において、図6で指摘した不
都合な短絡を防止するために最も重要な要件は、1電極
当たりの荷重である。この発明者等は、IC1aとし
て、6mm角のシリコンチップで80個の電極を有する
ICで電気回路配線4と半田バンプ2との接続状態を確
かめた。この場合の電気回路配線4上の半田5には、例
えば、鉛と錫との比が6:4の割合の組成の共晶半田を
用い、また半田バンプ2の半田には、例えば、鉛と錫と
の比が1:9の割合の組成の半田を用い、例えば、約2
16°Cで加熱した。
In this mounting method, the most important requirement for preventing the inconvenient short circuit pointed out in FIG. 6 is the load per electrode. The present inventors have confirmed the connection state between the electric circuit wiring 4 and the solder bump 2 by using an IC having a 80 mm electrode on a 6 mm square silicon chip as the IC 1 a. In this case, the solder 5 on the electric circuit wiring 4 is, for example, eutectic solder having a composition of lead and tin in a ratio of 6: 4, and the solder of the solder bump 2 is, for example, lead. Use solder with a composition of the ratio of tin to 1: 9, for example, about 2
Heated at 16 ° C.

【0012】図4の鉛=錫半田の状態図から明らかなよ
うに、錫6・鉛4の組成の半田は略々183°Cの一定
の溶融点を持つが、錫9・鉛1の組成の半田は略々18
3°C〜230°Cの温度範囲では固体と液体の共存状
態をなしている。
As is clear from the phase diagram of lead = tin solder in FIG. 4, the solder having the composition of tin 6 and lead 4 has a constant melting point of approximately 183 ° C., but the composition of tin 9 and lead 1 is The solder is about 18
In the temperature range of 3 ° C to 230 ° C, solid and liquid coexist.

【0013】従って、前記の216°Cの一定温度でリ
フローすると、配線基板3の半田5は溶融し、IC1a
の半田バンプ2の半田は固溶状態になる。この固溶状態
になっている所にIC1aの自重が掛かり、半田バンプ
2の高さのばらつきを吸収して、図3に示したように、
半田5及び半田バンプ2は良好な状態で溶着し、電極間
及び電気回路配線間を短絡しないことが確認できた。そ
こでこのIC1aの1電極当たりの荷重を計ったとこ
ろ、約0.48mgであった。
Therefore, when the reflow is performed at the constant temperature of 216 ° C., the solder 5 of the wiring board 3 is melted and the IC 1a
The solder of the solder bump 2 is in a solid solution state. The self-weight of the IC 1a is applied to the place in the solid solution state to absorb the height variation of the solder bump 2 and, as shown in FIG.
It was confirmed that the solder 5 and the solder bump 2 were welded in a good condition, and that no short circuit occurred between the electrodes and between the electric circuit wirings. Then, when the load per electrode of this IC 1a was measured, it was about 0.48 mg.

【0014】また、IC1bとして、3mm角のシリコ
ンチップで40個の電極を有するICを、前記IC1a
と同一の各半田の組成にして、同一の温度で加熱し、両
者の溶着状態を確認したところ、一部分に接続されてい
ない電極があることが認められた。そこで、このIC1
bの1電極当たりの荷重を計ったところ、約0.26m
gであった。それ故に、発明者等はこのICの半田バン
プ2の半田に、錫8・鉛2の組成の半田を使用し、再
度、前記の条件と同一条件で溶着状態を実験したとこ
ろ、図3に示したように、半田5及び半田バンプ2は良
好な状態で溶着していることが確認できた。
As the IC 1b, an IC having 40 electrodes on a 3 mm square silicon chip is referred to as the IC 1a.
When the same solder composition was used and heating was performed at the same temperature and the welding state of both was confirmed, it was found that some electrodes were not connected. Therefore, this IC1
When the load per electrode of b was measured, it was about 0.26 m
It was g. Therefore, the inventors of the present invention used a solder having a composition of tin 8 and lead 2 as the solder of the solder bump 2 of this IC, and once again tested the welded state under the same conditions as those described above. As described above, it was confirmed that the solder 5 and the solder bump 2 were welded in a good state.

【0015】更にまた、IC1cとして、9mm角のシ
リコンチップで120個の電極を有するICを、前記I
C1aと同一の各半田の組成にして、同一の温度で加熱
し、両者の溶着状態を確認したところ、一部分の電極間
及び電気回路配線間が短絡されている状態が認められ
た。そこで、このIC1cの1電極当たりの荷重を計っ
たところ、約0.65mgであった。それ故に、発明者
等はこのICの半田バンプ2の半田に、錫9.5・鉛
0.5の組成の半田を使用し、再度、前記の条件と同一
条件で実験したところ、半田5及び半田バンプ2は良好
な状態で溶着していることが確認できた。
Further, as the IC 1c, an IC having 120 electrodes on a 9 mm square silicon chip is
When each solder was made to have the same composition as that of C1a and heated at the same temperature to confirm the welding state of both, it was confirmed that a part of the electrodes and the electric circuit wiring were short-circuited. Then, when the load per electrode of this IC1c was measured, it was about 0.65 mg. Therefore, the inventors of the present invention used solder having a composition of tin 9.5 and lead 0.5 as the solder of the solder bump 2 of this IC, and conducted an experiment again under the same conditions as described above, and found that the solder 5 and It was confirmed that the solder bumps 2 were welded in good condition.

【0016】従って、これらの大きさ、重さ、電極数等
の外観が異なるIC1a、1b、1cでも、それらの半
田バンプ2に、電気回路配線4に被着した半田の溶融点
より高い組成の半田を用い、かつ1電極当たりの荷重に
応じて、即ち、荷重が軽いICには溶融点の比較的低い
組成の半田を、荷重が重いICには溶融点の比較的高い
組成の半田を用いれば、これらのICを共通の配線基板
3に同時に実装しても、良好な接続状態が得られること
が確認できた。
Therefore, even in the ICs 1a, 1b, and 1c having different appearances such as size, weight, and number of electrodes, their solder bumps 2 have a composition higher than the melting point of the solder applied to the electric circuit wiring 4. Depending on the load per electrode, that is, depending on the load per electrode, that is, for the IC with a light load, the solder with a relatively low melting point may be used, and for the IC with a heavy load, the solder with a relatively high melting point may be used. For example, it has been confirmed that a good connection state can be obtained even when these ICs are simultaneously mounted on the common wiring board 3.

【0017】なお、前記の実施例には、半田として鉛・
錫半田を例に挙げて説明したが、半田はインジューム・
錫等のものでもよく、またICとしてはフリップチップ
型ICを例に挙げて説明したが、この発明はこの他、例
えば、QFJ型のような表面実装型ICにも適応でき
る。
In the above embodiment, lead / solder
I explained tin solder as an example.
It may be made of tin or the like, and the IC has been described by taking the flip-chip type IC as an example, but the present invention is also applicable to a surface mounting type IC such as a QFJ type.

【0018】[0018]

【発明の効果】以上の説明から明らかなように、この発
明の配線基板への実装方法によれば、たとえファインピ
ッチで電極が形成されたICでも、また大きさ、重さ等
が異なるICでも、それらを混在させて同一配線基板に
リフローで実装しても、そのICの相隣る電極間、或い
はまた相隣る配線間を短絡させるような事象が生じるこ
とがない。また同一の温度で一括リフローできるので、
作業能率が上がる。そして又、全てのICが最適条件で
リフローされているため、信頼性、歩留りも向上する等
数々の優れた効果が得られる。
As is apparent from the above description, according to the method of mounting on a wiring board of the present invention, even an IC having electrodes formed at a fine pitch or an IC having a different size, weight, etc. Even if they are mixed and mounted on the same wiring board by reflow, an event that short-circuits between adjacent electrodes of the IC or between adjacent wirings does not occur. Also, since batch reflow can be done at the same temperature,
Work efficiency increases. Further, since all the ICs are reflowed under the optimum conditions, various excellent effects such as improvement in reliability and yield can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】複数のICが実装された共通の配線基板を示す
一部平面図である。
FIG. 1 is a partial plan view showing a common wiring board on which a plurality of ICs are mounted.

【図2】図1のA−A線上における断面図である。FIG. 2 is a cross-sectional view taken along the line AA of FIG.

【図3】図2の状態でリフローした結果、半導体集積回
路素子と電気回路配線が接続された状態を示す断面図で
ある。
FIG. 3 is a cross-sectional view showing a state where the semiconductor integrated circuit element and the electric circuit wiring are connected as a result of reflowing in the state of FIG.

【図4】鉛・錫半田の状態図である。FIG. 4 is a state diagram of lead / tin solder.

【図5】半導体集積回路素子と配線基板の状態を説明す
るための断面図である。
FIG. 5 is a sectional view for explaining a state of a semiconductor integrated circuit element and a wiring board.

【図6】従来技術の半導体集積回路素子の配線基板への
実装方法を説明するための断面図である。
FIG. 6 is a cross-sectional view for explaining a method for mounting a semiconductor integrated circuit device of the related art on a wiring board.

【図7】図6の実装方法で半導体集積回路素子を配線基
板に実装した状態を示す断面図である。
7 is a sectional view showing a state in which a semiconductor integrated circuit element is mounted on a wiring board by the mounting method of FIG.

【符号の説明】[Explanation of symbols]

1 半導体集積回路素子(IC) 2 半田バンプ 3 配線基板 4 電気回路配線 5 半田 6 重り 7 接続部分 1 Semiconductor Integrated Circuit Element (IC) 2 Solder Bump 3 Wiring Board 4 Electric Circuit Wiring 5 Solder 6 Weight 7 Connection Part

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/34 H 9154−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/34 H 9154-4E

Claims (1)

【特許請求の範囲】 【請求項1】重量が異なる複数の半導体集積回路素子を
共通の配線基板に半田付け実装する場合に、これらの各
半導体集積回路素子毎に、その半導体集積回路素子の1
電極当たりの荷重に応じて、各半導体集積回路素子の電
極に形成する半田バンプの半田組成を変え、そして実装
しようとする全ての半導体集積回路素子の半田バンプの
半田の融点を、配線基板に被着した半田の融点よりも高
く調整して、これら複数の半導体集積回路素子を前記配
線基板に半田付け実装することを特徴とする半導体集積
回路素子の配線基板への実装方法。
Claims: 1. When a plurality of semiconductor integrated circuit elements having different weights are mounted on a common wiring board by soldering, one semiconductor integrated circuit element is provided for each semiconductor integrated circuit element.
The solder composition of the solder bumps formed on the electrodes of each semiconductor integrated circuit element is changed according to the load per electrode, and the melting points of the solder bumps of all the semiconductor integrated circuit elements to be mounted are measured on the wiring board. A method for mounting a semiconductor integrated circuit element on a wiring board, which comprises adjusting the melting point of the deposited solder to be higher than the melting point and soldering the plurality of semiconductor integrated circuit elements to the wiring board.
JP3152970A 1991-06-25 1991-06-25 Mounting method of semiconductor integrated circuit element on wiring board Pending JPH053197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3152970A JPH053197A (en) 1991-06-25 1991-06-25 Mounting method of semiconductor integrated circuit element on wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3152970A JPH053197A (en) 1991-06-25 1991-06-25 Mounting method of semiconductor integrated circuit element on wiring board

Publications (1)

Publication Number Publication Date
JPH053197A true JPH053197A (en) 1993-01-08

Family

ID=15552130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3152970A Pending JPH053197A (en) 1991-06-25 1991-06-25 Mounting method of semiconductor integrated circuit element on wiring board

Country Status (1)

Country Link
JP (1) JPH053197A (en)

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