JPH05315528A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH05315528A
JPH05315528A JP11865192A JP11865192A JPH05315528A JP H05315528 A JPH05315528 A JP H05315528A JP 11865192 A JP11865192 A JP 11865192A JP 11865192 A JP11865192 A JP 11865192A JP H05315528 A JPH05315528 A JP H05315528A
Authority
JP
Japan
Prior art keywords
lead
lead frame
island portion
semiconductor chip
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11865192A
Other languages
Japanese (ja)
Inventor
Masao Ueda
正夫 植田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP11865192A priority Critical patent/JPH05315528A/en
Publication of JPH05315528A publication Critical patent/JPH05315528A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize a high reliability against the thermal stress of a semiconductor chip mounted on an island part as well as to provide the title lead frame having easily bendable outer lead. CONSTITUTION:An island part 11 is formed of an iron-nickel alloy containing nickel 42% in almost the same thermal expansion coefficient as that of the material of a semiconductor element. On the other hand, an inner lead 12 and an outer lead 13 are formed of copper alloy having excellent shaping property.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はリードフレームに関し、
特に樹脂封止型の半導体装置に用いるリードフレームに
関する。
FIELD OF THE INVENTION The present invention relates to a lead frame,
In particular, the present invention relates to a lead frame used for a resin-sealed semiconductor device.

【0002】[0002]

【従来の技術】従来のこの種のリードフレームは、図3
に示すように、半導体チップ2を搭載するアイランド部
14と、半導体チップ2とボンディングワイヤ3で接続
された封止樹脂4の内部の内部リード15と、外部接続
用の外部リード16とを備えて構成されていた。
2. Description of the Related Art A conventional lead frame of this type is shown in FIG.
As shown in FIG. 3, the semiconductor chip 2 is mounted on the island portion 14, the internal lead 15 inside the sealing resin 4 connected to the semiconductor chip 2 by the bonding wire 3, and the external lead 16 for external connection. Was configured.

【0003】従来のリードフレームのアイランド部14
と内部リード15と外部リード16とは、ニッケル42
%の鉄ニッケル合金か、あるいは銅合金の板材からプレ
ス打抜き加工により形成され、したがって、一種類の材
料から構成されているというものであった。
The island portion 14 of the conventional lead frame
The inner lead 15 and the outer lead 16 are made of nickel 42
% Iron-nickel alloy or copper alloy plate material, which was formed by press punching, and thus was composed of one kind of material.

【0004】鉄ニッケル合金は、半導体素子の材料であ
るシリコンとほぼ同等の熱膨張係数を有しているので、
アイランド部14に半導体チップを搭載したときの樹脂
封止工程や使用時における熱ストレスによる信頼性低下
を防止できるという利点があるが、外部リード16等に
おける折曲げ加工が困難であるという欠点がある。一
方、銅合金は、整形性が優れているので、外部リード1
6等における折曲げ加工が容易にできるという利点があ
るが、熱膨張係数がシリコンと大幅に異なるのでアイラ
ンド部14に半導体チップを搭載したときの樹脂封止工
程や使用時における熱ストレスによりクラックの発生等
の恐れがあるというものであった。
The iron-nickel alloy has a coefficient of thermal expansion almost equal to that of silicon, which is a material of the semiconductor element.
There is an advantage that it is possible to prevent deterioration of reliability due to thermal stress during a resin sealing process when a semiconductor chip is mounted on the island portion 14 and during use, but there is a drawback that bending of the external leads 16 is difficult. .. On the other hand, since the copper alloy is excellent in shapeability, the external lead 1
6 has an advantage that it can be easily bent, but since the coefficient of thermal expansion is significantly different from that of silicon, cracks may occur due to thermal stress during the resin sealing process when the semiconductor chip is mounted on the island portion 14 and during use. There was a fear of occurrence.

【0005】[0005]

【発明が解決しようとする課題】上述した従来のリード
フレームは、要求特性が異なるアイランド部と内部ある
いは外部リード部とに対し、同一の金属材料を用いてい
たため、アイランド部の要求特性であるシリコンと同等
の年膨張係数を満足するものを用いると、リード部の折
曲げ加工が困難となり、整形性の良いものを用いると、
半導体チップに対する熱ストレスによる信頼性低下が発
生するという欠点があった。
In the above-mentioned conventional lead frame, the same metal material is used for the island portion and the internal or external lead portions having different required characteristics, and therefore, the silicon having the required characteristic of the island portion is used. If the one that satisfies the annual expansion coefficient equivalent to is used, it becomes difficult to bend the lead part, and if the one with good formability is used,
There is a drawback that reliability is reduced due to thermal stress on the semiconductor chip.

【0006】[0006]

【課題を解決するための手段】本発明のリードフレーム
は、半導体素子の材料とほぼ同様な熱膨張係数を有する
第一の金属材料から成るアイランド部と、整形性の良好
な第二の金属材料から成る内部リードおよび外部リード
とを備えて構成されている。
The lead frame of the present invention comprises an island portion made of a first metal material having a thermal expansion coefficient substantially similar to that of the semiconductor element, and a second metal material having a good shaping property. And an internal lead and an external lead.

【0007】[0007]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0008】図1は本発明のリードフレームの一実施例
を示す模式断面図である。
FIG. 1 is a schematic sectional view showing an embodiment of the lead frame of the present invention.

【0009】本実施例のリードフレームは、図1に示す
ように、半導体チップ2を搭載するアイランド部11
と、半導体チップ2とボンディングワイヤ3で接続され
た封止樹脂4の内部の内部リード12と、外部接続用の
外部リード13とを備えて構成されている。
As shown in FIG. 1, the lead frame of this embodiment has an island portion 11 on which a semiconductor chip 2 is mounted.
And an internal lead 12 inside the sealing resin 4 connected to the semiconductor chip 2 by the bonding wire 3 and an external lead 13 for external connection.

【0010】アイランド部11は、シリコンとほぼ同等
の熱膨張係数を有するニッケル42%の鉄ニッケル合金
により形成されている。内部リード12と外部リード1
3とは、整形性がよい銅合金により形成されている。
The island portion 11 is formed of a 42% nickel iron-nickel alloy having a thermal expansion coefficient substantially equal to that of silicon. Internal lead 12 and external lead 1
3 is formed of a copper alloy having a good shaping property.

【0011】このような構成とすることにより、アイラ
ンド部11と半導体チップ2との熱膨張係数の差による
熱ストレスの発生を防止し、半導体チップ2のクラック
発生等の事故を防止することができるとともに、外部リ
ードの曲げ加工が容易なリードフレームを実現すること
ができる。
With such a structure, it is possible to prevent the occurrence of thermal stress due to the difference in thermal expansion coefficient between the island portion 11 and the semiconductor chip 2, and prevent accidents such as cracks in the semiconductor chip 2. At the same time, it is possible to realize a lead frame in which bending of the external leads is easy.

【0012】図2は、本実施例のリードフレームの製造
方法の一例を示す図である。
FIG. 2 is a diagram showing an example of a method of manufacturing the lead frame of this embodiment.

【0013】帯状の銅合金板5のアイランド部11を形
成する位置にニッケル42%の鉄ニッケル合金板6を張
合わせた板材のプレス打抜き加工またはエッチング加工
により容易に形成することが可能である。
The strip-shaped copper alloy plate 5 can be easily formed by press punching or etching a plate material in which the iron-nickel alloy plate 6 of 42% nickel is attached to the position where the island portion 11 is formed.

【0014】[0014]

【発明の効果】以上説明したように、本発明のリードフ
レームは、アイランド部を半導体素子の材料とほぼ同様
な熱膨張係数の金属材料で形成し、内部リードおよび外
部リードを整形性の良好な金属材料で形成しているの
で、アイランド部に搭載する半導体チップの熱ストレス
に対する高信頼度化を実現するとともに、外部リードの
曲げ加工が容易なリードフレームを実現することができ
るという効果がある。
As described above, in the lead frame of the present invention, the island portion is formed of a metal material having a thermal expansion coefficient substantially similar to that of the semiconductor element material, and the inner lead and the outer lead have good shaping characteristics. Since it is formed of a metal material, there is an effect that it is possible to realize a highly reliable semiconductor chip mounted on the island portion against thermal stress and to realize a lead frame in which the external leads can be easily bent.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のリードフレームの一実施例を示す模式
断面図である。
FIG. 1 is a schematic cross-sectional view showing an embodiment of a lead frame of the present invention.

【図2】本実施例のリードフレームの製造法の一例を示
す図である。
FIG. 2 is a diagram showing an example of a method for manufacturing the lead frame of the present embodiment.

【図3】従来のリードフレームの一例を示す模式断面図
である。
FIG. 3 is a schematic cross-sectional view showing an example of a conventional lead frame.

【符号の説明】[Explanation of symbols]

2 半導体チップ 3 ボンディングワイヤ 4 封止樹脂 11,14 アイランド部 12,15 内部リード 13,16 外部リード 2 Semiconductor chip 3 Bonding wire 4 Sealing resin 11,14 Island part 12,15 Internal lead 13,16 External lead

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体素子の材料とほぼ同様な熱膨張係数
を有する第一の金属材料から成るアイランド部と、 整形性の良好な第二の金属材料から成る内部リードおよ
び外部リードとを備えることを特徴とするリードフレー
ム。
1. An island portion made of a first metal material having a thermal expansion coefficient substantially similar to that of a semiconductor element material, and an inner lead and an outer lead made of a second metal material having a good shaping property. Lead frame characterized by.
【請求項2】 前記第一の金属材料がニッケルを42%
含む鉄ニッケル合金であり、前記第二の合金が銅合金で
あることを特徴とする請求項1記載のリードフレーム。
2. The first metal material contains 42% nickel.
The lead frame according to claim 1, wherein the lead frame is an iron-nickel alloy containing the second alloy is a copper alloy.
JP11865192A 1992-05-12 1992-05-12 Lead frame Pending JPH05315528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11865192A JPH05315528A (en) 1992-05-12 1992-05-12 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11865192A JPH05315528A (en) 1992-05-12 1992-05-12 Lead frame

Publications (1)

Publication Number Publication Date
JPH05315528A true JPH05315528A (en) 1993-11-26

Family

ID=14741841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11865192A Pending JPH05315528A (en) 1992-05-12 1992-05-12 Lead frame

Country Status (1)

Country Link
JP (1) JPH05315528A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8125063B2 (en) * 2010-03-08 2012-02-28 Powertech Technology, Inc. COL package having small chip hidden between leads

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213270A (en) * 1986-03-14 1987-09-19 Sumitomo Electric Ind Ltd Lead frame for semiconductor device
JPH02152267A (en) * 1988-12-02 1990-06-12 Hitachi Cable Ltd Lead frame parallel-connected by cu alloy/fe-ni alloy
JPH03290957A (en) * 1990-04-06 1991-12-20 Sumitomo Special Metals Co Ltd Lead frame material for plastic package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213270A (en) * 1986-03-14 1987-09-19 Sumitomo Electric Ind Ltd Lead frame for semiconductor device
JPH02152267A (en) * 1988-12-02 1990-06-12 Hitachi Cable Ltd Lead frame parallel-connected by cu alloy/fe-ni alloy
JPH03290957A (en) * 1990-04-06 1991-12-20 Sumitomo Special Metals Co Ltd Lead frame material for plastic package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8125063B2 (en) * 2010-03-08 2012-02-28 Powertech Technology, Inc. COL package having small chip hidden between leads

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Effective date: 19971111