JPH05315348A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce junction capacities between an emitter.base and a collector.base and to improve transistor characteristics by forming a collector, a base and an emitter in a self-alignment manner by using a selectively epitaxial method. CONSTITUTION:An insulating film 25 is formed on a predetermined part on a first conductivity type collector 6, a second conductivity type first epitaxial layer 7 surrounding it is formed, and the film 25 is then removed to form an opening 8 in the layer 7. Then, a sidewall 9 of an insulating film is formed on a sidewall of the opening 8 except its lower part, a second conductivity type second epitaxial layer 12 to be connected to the layer 7 is formed, and then a semiconductor layer 11 including a first conductivity type impurity is formed in contact with an upper surface of the layer 12. Thereafter, the impurity is implanted in the layer 12 to form a first conductivity type impurity region 13 in the opening 8, and a bipolar transistor in which the layer 7 is used as an outer base, the layer 12 is used as an intrinsic base and the region 13 is used as an emitter is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an ultra high speed bipolar transistor.

[0002]

2. Description of the Related Art A conventional method for manufacturing an NPN transistor will be described. 4 and 5 are vertical sectional views of the prior art. First, with the thermal oxide film as a mask, the P-type silicon substrate 41 is N-doped by ion implantation or spin-on diffusion.
^{A +} type impurity buried diffusion layer 44 is formed. Then, after removing all the silicon oxide film on the surface, a low impurity concentration N ⁻ -type epitaxial layer 4 is formed by a low pressure epitaxial device.
6 is formed (FIG. 4A). Next, boron diffusion for insulation is performed to form a P ⁺ -type diffusion layer 48. continue,
Using the patterned silicon nitride film 45 as a mask, the element isolation region 42 (hereinafter referred to as LOC) is formed by a pressure oxidation method.
OS) is formed (FIG. 4B). Then, by introducing a phosphorus (P) by an ion implantation apparatus with the photoresist 61 is patterned as a mask to form the N ⁺ buried layer N ⁺ -type collector lead-out region 43 reaching at 44 by heat treatment ( FIG. 4 (c)). Next, in order to reduce the base resistance and form a high-concentration P ⁺ -type external base region 47, boron is introduced by the ion implantation method using the patterned photoresist 62 as a mask, or patterned silicon is used. Oxide film (not shown)
A high concentration of boron is introduced by a thermal diffusion method using the mask as a mask (FIG. 4D). Next, using the same method as the above external base forming method (however, the introduction conditions are different), P having a predetermined concentration profile (for example, junction depth 0.1 μm, concentration 1 × 10 ¹⁸ cm ⁻³ ) is formed. The mold intrinsic base region 52 is formed using the photoresist 63 as a mask (FIG. 4).
(E)). Next, by the chemical vapor deposition method (CVD method),
Silicon oxide film 49 and silicon nitride film 51 on the wafer surface
Are sequentially formed. Next, using the photoresist (not shown) patterned by the lithography technique as a mask, the silicon nitride film 51 and the silicon oxide film 49 on the collector, base and emitter regions are sequentially removed by the dry etching method. A contact opening portion 50 that simultaneously opens the regions is formed (FIG. 5A). Then C
After depositing a polycrystalline silicon film 54 on the wafer surface by the VD method, arsenic (As) having a predetermined concentration is introduced into the polysilicon on the entire surface of the wafer by the ion implantation method (FIG. 5).
(B)). Subsequently, the arsenic-doped polysilicon 54 other than on the emitter and collector regions is removed by a dry etching method and then heat-treated in a nitrogen atmosphere to form an N ⁺ -type emitter diffusion region 53 (FIG. 5).
(C)). Finally, a metal such as aluminum (Al) is formed on the wafer surface by a sputtering method, an electrode wiring pattern is formed by a photoresist, and the metal in other regions is removed by a dry etching method to form a metal wiring. Apply, base metal electrode 14, emitter metal electrode 1
5, The collector metal electrode 16 is formed (FIG. 5D).

[0003]

In order to improve the performance of a bipolar transistor, it is necessary to reduce the planar size in order to reduce various parasitic capacitances such as emitter-base junction capacitance and collector-base junction capacitance. Furthermore, in order to increase the speed, it is necessary to make the base layer a shallow junction while suppressing an increase in the base resistance. For the shallow junction of the base layer, it is possible to stably form a junction depth of 0.03 μm by a silicon molecular beam epitaxy (MBE) method or the like.

On the other hand, in order to reduce the parasitic capacitance, the photolithography technique is exclusively used, and there is a limit to miniaturization depending on the exposure apparatus used. Therefore, although progress has been made, it is not possible to meet the demand for miniaturization of devices. , Which limits the device characteristics. Therefore, in order to achieve further miniaturization, it is necessary to introduce a new type of equipment by a large amount of equipment investment. Also, especially for emitter-base capacitance, arsenic-doped
In an emitter formed by arsenic diffusion from polysilicon, even if a very small emitter is formed, the side wall area of the diffusion layer due to arsenic diffusion may increase and the parasitic capacitance may not be reduced.

On the other hand, when the base junction is made shallow, the base resistance becomes high. Therefore, in general, an external base region is provided to reduce the base resistance. However, in the conventional method, the breakdown voltage of the base-collector is determined by the external base, and the breakdown voltage is lowered. This is because the bond of the external base is deeper than that of the intrinsic base.

[0006]

A feature of the present invention is to form a first insulating film on a predetermined portion of an upper surface of a first conductivity type collector, and to surround the first insulating film and to collect the first insulating film. Forming a first conductive type second epitaxial layer in contact with the region, and forming an opening in the first epitaxial layer to expose a predetermined portion of the collector region by removing the first insulating film. And the side wall of the opening is formed with a side wall of the second insulating film except the lower part thereof, whereby the lower part of the side wall is exposed and the other part of the side wall is covered with the side wall. A step of forming a second conductive type second epitaxial layer connected to the first epitaxial layer in the lower portion of the side wall in the opening, and a semiconductor layer containing a first conductive type impurity Forming in contact with an upper surface of the second epitaxial layer, said first conductivity type impurity,
Introducing into the second epitaxial layer by, for example, lamp annealing or furnace annealing to form an impurity region of the first conductivity type in the opening, whereby the first epitaxial layer is formed into an external base, It is a method of manufacturing a semiconductor device in which a bipolar transistor having the second epitaxial layer of the second conductivity type in the opening as an intrinsic base and the impurity region as an emitter is formed. The first insulating film is a silicon oxide film, the first epitaxial layer is a P-type silicon epitaxial layer containing boron, and the sidewall of the second insulating film is a silicon nitride film on the silicon oxide film. And a second epitaxial layer is a P-type silicon epitaxial layer containing boron, and the semiconductor layer is a polycrystalline silicon layer containing arsenic. NPN bipolar transistors can be formed.

The collector has a first-conductivity-type collector active region including the upper surface, a high-impurity-concentration first-conductivity-type collector lead portion, and a high-impurity-concentration first-conductivity-type buried diffusion layer. Then, the second conductivity type semiconductor substrate is selectively removed to form a flat surface and a protrusion protruding from the flat surface, and impurities of the first conductivity type are introduced from a predetermined portion of the flat surface to fill the buried portion. At the same time when the buried diffusion layer is formed, impurities of the first conductivity type are introduced into the protruding portion to form the collector extraction portion, and thereafter, an epitaxial layer is selectively grown on the buried diffusion layer to perform the collector activation. It is preferable to form a region. The growth of the epitaxial layer on the buried diffusion layer can be performed by using a device isolation insulating layer obtained by oxidizing polycrystalline silicon as a mask. By forming the emitter in a self-aligned manner by such a manufacturing method, the base resistance can be reduced without lowering the breakdown voltage between the base and the collector, and the parasitic capacitance between the base and the emitter can be reduced. I can. Therefore, a high speed bipolar transistor can be formed.

[0008]

The present invention will be described below with reference to the drawings. 1 and 2 are sectional views showing an embodiment of the present invention in the order of steps, and FIG. 3 is an enlarged sectional view showing an emitter and its vicinity in the embodiment.

First, the patterned photoresist 6
Using 0 as a mask, dry etching is performed to form the underlying P
The protrusion 2 is formed by etching at the location where the collector lead-out region of the mold silicon substrate 1 is formed. The etching amount H at this time is a predetermined value within the range of 0.5 to 2.0 μm (FIG. 1A). Then, the photoresist 60 of the mask is removed by plasma stripping or the like, and then a silicon oxide film 21 having a film thickness of about 500 nm (nanometer) is formed on the wafer surface by steam oxidation. Next, after removing the silicon oxide film 21 in the portion where the N ⁺ type buried diffusion layer region is formed, a silicon oxide film 23 containing phosphorus or arsenic is formed by the CVD method or the spin-on diffusion method, and then 10
The N ⁺ type buried diffusion layer 4 is formed by diffusing in an atmosphere containing several% of O ₂ at 00 to 1250 ° C. At the same time, phosphorus or arsenic is introduced also into the protrusion 2 to form an N ⁺ type collector. The drawing area 3 is used. Here, the width Wc of the protruding portion 2 and the collector extraction region 3 is set to a value smaller than twice the diffusion depth Xj, so that the collector extraction region 3 has N ^+.
It can be formed as a mold. Then, after removing the entire silicon oxide film 21, a film thickness of 5 is obtained by steam oxidation.
A silicon oxide film 23 having a thickness of about 0 nm is formed, and subsequently, polysilicon 5 having a film thickness half the etching amount H is deposited by the CVD method (FIG. 1C). Next, after removing the polysilicon 5 on the transistor active region (emitter / base formation region and collector extraction region) by dry etching, the remaining polysilicon 5 is formed by a pressure oxidation method.
Is oxidized and converted into a silicon oxide film 24. Next, using the patterned photoresist as a mask,
After removing the silicon oxide films 24 and 23 under the emitter region by wet etching (FIG. 1D), an N ⁻ type epitaxial layer 6 is formed in the same region by the silicon selective epitaxial method (FIG. 1E). ). Next, the silicon oxide film 25 having a film thickness of 50 to 200 nm is formed by steam oxidation, and then the silicon oxide film 25 other than the portion where the emitter region is formed is removed by the photolithography technique. Here, the width of the remaining silicon oxide film 25 becomes the emitter contact size. Then 1 × 10 ¹⁹ cm ^-3
The P ⁺ type epitaxial layer 7 containing boron is formed on the wafer surface. At this time, polysilicon (not shown) is formed on the silicon oxide film 25 without epitaxial growth. Subsequently, the P ⁺ epitaxial layer 7 other than the base region is removed. Further, the polysilicon above the emitter region forming portion is also removed (FIG. 2A). Next, the silicon oxide film 25 is removed to form the opening 8. Then, a silicon oxide film 26 having a film thickness of several tens nm is formed by steam oxidation. Here, since this film thickness determines the base width in the depth direction, a predetermined value is set for each transistor.
Then, the silicon nitride film 31 having a thickness of 100 to 200 nm is removed by C
It is deposited by the VD method (FIG. 2B). Next, the silicon nitride film 31 is removed by anisotropic dry etching. At this time, the silicon nitride film 31 is formed on the sidewall of the opening 8.
Are not removed and remain to form sidewalls 9.
The emitter contact width can be reduced by this thickness.
Then, the silicon oxide film 26 exposed in the opening 8, that is, the sidewall 9 is formed by photolithography.
The silicon oxide film 26 at the bottom of the opening 8 including the bottom is removed by wet etching to form the cavity 10. Then, a photoresist (not shown) used as a mask at this time
Is peeled off with an organic solvent (FIG. 2 (c)). Next 10 ⁴
The silicon epitaxial layer 12 doped with 1 × 10 ¹⁸ to 10 ¹⁹ cm ⁻³ of boron is selectively formed under a high vacuum of not more than torr. The P-type epitaxial layer 12 that serves as the intrinsic base region is connected to the P ⁺ -type epitaxial layer 7 that serves as an external base below the sidewall of the opening 8 below the sidewall 9. By setting the epi thickness at this time to about 100 nm, the arsenic diffusion depth (Xje) from the arsenic-doped polysilicon in the formation of the emitters described in the following paragraph is 50 n.
The optimum value is within m, and the base width in this case is around 50 nm. Subsequently, polysilicon 11 containing arsenic of 1 × 10 ²⁰ cm ⁻³ or more is selectively deposited under the same conditions (FIG. 2D). Next, arsenic is diffused into the base by lamp annealing and furnace annealing to form an emitter region 1
3 is formed. Subsequently, after depositing a silicon nitride film 32 by a CVD method, the silicon nitride film 32 and the silicon oxide film 26 in the emitter, collector and base contact portions,
23 is sequentially removed. After that, a metal layer such as aluminum (Al) is formed on the entire surface of the wafer by a sputtering method, and a base metal electrode 14, an emitter metal electrode 15, and a collector metal electrode 16 are formed by a dry etching method using a patterned photoresist. (FIG. 2 (e) and FIG. 3).

[0010]

As described above, according to the present invention, the collector,
Since the base and the emitter are formed in a self-aligned manner using the selective epitaxial method, it is possible to form the emitter and the base requiring a small area without requiring a special capital investment. It is possible to reduce the capacitance and dramatically structure the characteristics of the bipolar transistor.

Further, since the collector extraction portion is formed at the same time as the N ⁺ type collector buried diffusion layer, the collector resistance can be reduced. In addition, since the external base region is formed by the epitaxial method, the base resistance can be reduced, so that the transistor characteristics can be improved. In addition, the conventional external base region
It is possible to prevent the collector-base breakdown voltage from decreasing by determining the breakdown voltage between bases that has been reduced by the intrinsic base.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing an NPN bipolar transistor according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing an NPN bipolar transistor of one embodiment of the present invention in the order of steps.

FIG. 3 is an enlarged sectional view showing an emitter of an NPN bipolar transistor according to an embodiment of the present invention and its vicinity.

FIG. 4 is a cross-sectional view showing a method of manufacturing a conventional NPN bipolar transistor in process order.

FIG. 5 is a cross-sectional view showing a method of manufacturing a conventional NPN bipolar transistor in the order of steps.

[Explanation of symbols]

1,41 P-type silicon substrate 2 Projection part 3,43 N ⁺ type collector extraction region 4,44 N ⁺ type buried diffusion layer 5,11,54 Polycrystalline silicon 6,46 N ⁻ type epitaxial layer 7 P ⁺ type epitaxial layer Layer (External Base Region) 8 Opening 9 Sidewall 10 Cavity 12 P-type Epitaxial Layer (Intrinsic Base Region) 13,53 Emitter Region 14 Base Metal Electrode 15 Emitter Metal Electrode 16 Collector Metal Electrode 21,23,24,25,26 , 42, 49 silicon oxide film 22 N-type impurity-containing silicon oxide film 31,32,45,51 silicon nitride film 47 P ⁺ type external base region 48 P ⁺ -type diffusion layer 50 contact openings 52 P-type intrinsic base region 60 , 61, 62, 63 Photoresist

Claims (4)

[Claims] 1. A step of forming a first insulating film on a predetermined portion of an upper surface of a collector of the first conductivity type, and a first conductivity type of a second conductivity type surrounding the first insulating film and in contact with the collector region. Forming an epitaxial layer, forming an opening for exposing a predetermined portion of the collector region in the first epitaxial layer by removing the first insulating film, and forming a side wall on the sidewall of the opening. Second except the lower part
A side wall of the insulating film is formed, thereby exposing the lower part of the side wall and covering the other part of the side wall with the side wall, and connecting to the first epitaxial layer in the lower part of the side wall. Forming a second epitaxial layer of a second conductivity type in the opening; forming a semiconductor layer containing an impurity of the first conductivity type in contact with the upper surface of the second epitaxial layer; Introducing a conductivity type impurity into the second epitaxial layer to form a first conductivity type impurity region in the opening, whereby the first epitaxial layer is formed as an external base in the opening. Of the second conductivity type second epitaxial layer as an intrinsic base, and the impurity region as an emitter, forming a bipolar transistor. Production method. 2. The first insulating film is a silicon oxide film, the first epitaxial layer is a P-type silicon epitaxial layer containing boron, and the sidewall of the second insulating film is a silicon oxide film. It is formed by stacking a silicon nitride film on top and performing anisotropic etching on it.
2. The second epitaxial layer is a P-type silicon epitaxial layer containing boron, and the semiconductor layer is a polycrystalline silicon layer containing arsenic to form an NPN bipolar transistor. Of manufacturing a semiconductor device of. 3. The collector has a first conductive type collector active region including the upper surface, a high impurity concentration first conductive type collector lead portion, and a high impurity concentration first conductive type buried diffusion layer. The semiconductor substrate of the second conductivity type is selectively removed to form a flat surface and a protrusion protruding from the flat surface, and impurities of the first conductivity type are introduced from a predetermined portion of the flat surface. At the same time that the buried diffusion layer is formed, impurities of the first conductivity type are introduced into the protrusion to form the collector extraction portion, and then an epitaxial layer is selectively grown on the buried diffusion layer to form the collector. The method of manufacturing a semiconductor device according to claim 1, wherein an active region is formed. 4. The semiconductor device according to claim 3, wherein the growth of the epitaxial layer on the buried diffusion layer is performed by using an element isolation insulating layer obtained by oxidizing polycrystalline silicon as a mask. Manufacturing method.