JPH05315325A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form minute patterns with high precision by a method wherein a first insulating film for level-matching is selectively formed in a lower region of a step like a non-memory cell region of DRAM and a second insulating film is further formed so as to cover the entire surface. CONSTITUTION:A nitrogen silicon film 2 is first formed as an etching stopper on the surface of a silicon substrate 1 having a large step of 1mum or so and for instance an oxidized silicon film 3 is further deposited on its upper layer as a first layer insulating film. After only the oxidized silicon film 3 on a large recess is selectively left by a photolithography, a second layer insulating film is further formed on the entire substrate surface to flat it. Thus, even on the substrate surface having a large step patterns can be formed with high precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to formation of an interlayer insulating film on a surface having a large step in the millimeter range region and pattern formation on the surface.

[0002]

2. Description of the Related Art In recent years, with the high integration of semiconductor devices, miniaturization of circuits has been progressing, and miniaturization and multi-layering of wiring have been rapidly promoted.

Under such circumstances, the surface of the interlayer insulating film needs to be smooth. This is because if there is a steep step, it becomes difficult to pattern the wiring and the like thereafter. Therefore, using phosphorus glass or the like as the interlayer insulating film,
A method has been conventionally used in which phosphorous glass is made to have fluidity by a heat step after being deposited to flatten the surface (phosphorus glass flow).

However, when the conventional phosphorus glass flow method is used, the lithography technique on the interlayer insulating film becomes extremely difficult. For example, in the case of a laminated DRAM, even if a capacitor and a transistor are formed, then an interlayer insulating film is formed and planarized by a phosphorus glass flow,
There is a large step between the memory cell region and the non-memory cell region. This is because a capacitor, which does not exist in the non-memory cell region, is formed in the memory cell region so as to protrude from the surface. When a resist is deposited on the surface of a substrate having such a shape, as shown in FIG. 10, the film thickness of the resist becomes thicker in the lower part of the step than in the flat part, so that the resolution of lithography is lowered and it becomes difficult to perform fine patterning. Secondly, even in the non-memory cell region below the step portion, the resist film thickness becomes a normal film thickness if it is separated from the step portion by several tens to several thousands of microns. Therefore, the height of the resist surface above the step portion and the surface below the step portion There is a large level difference between the height and the height. Therefore, if the light of photolithography is focused on one of the resist film thicknesses, it will not be focused on the other, and the focus will be out of focus, making it difficult to perform fine patterning.

Further, if the interlayer insulating film is flattened, the pattern accuracy of the resist pattern is improved, but as shown in FIG. 11, the film thickness of the interlayer insulating film is large between the lower part and the upper part of the step. Therefore, the contact depth is very different, and if it is matched with a deep contact, over-etching occurs in the shallow contact region, while if it is matched with a shallow contact, it is not possible to make a contact in the deep contact portion, and good contact etching should be performed. There is a problem that you can not.

[0006]

As described above, according to the conventional method, when there is a large step on the surface in the resist pattern forming step by exposure, the film thickness of the resist is increased below the step and an unexposed portion is formed. In addition, when there is a large level difference, when the distance from the level difference portion is increased, a level difference corresponding to the large level difference is also generated on the resist surface, and the focus of light in optical lithography is defocused. There was a problem that accuracy could not be obtained.

Further, even if the interlayer insulating film can be formed on the large step so that the surface becomes flat, there is a large difference in the film thickness of the interlayer insulating film, and the contact etching cannot be performed well. There is.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a highly precise fine pattern.

[0009]

Therefore, in the present invention, when forming an interlayer insulating film on the surface of a substrate having a step, DR
A first insulating film for level matching is selectively formed in a lower region of a step such as a non-memory cell region of AM, and a second insulating film is further formed so as to cover the entire surface. ..

According to the second aspect of the present invention, when patterning a stepped substrate surface or a film formed on a stepped substrate surface, the first resist is applied and the resist in the upper region of the step is subjected to photolithography or the like. The first resist for level adjustment is selectively removed only in the lower region of the step, and the second resist is formed so as to cover the entire surface, and at least the second resist is formed by photolithography. And the film formed on the substrate surface or the substrate surface is patterned using this as a mask.

[0011]

According to the first aspect, since the lower portion of the step is filled with the first interlayer insulating film and the second interlayer insulating film is formed on the upper portion, the surface can be flattened. The pattern accuracy can be improved also in photolithography.

Desirably, the first interlayer insulating film is filled by selectively removing the upper portion of the step by photolithography or polishing after forming the first interlayer insulating film. As a result, it is possible to satisfactorily fill only the deep step region.

According to the second aspect of the present invention, the first resist is applied and the resist in the upper region of the step is selectively removed by photolithography, polishing or the like, and the level is selectively adjusted only in the lower region of the step. Since the second resist is formed so as to remain the first resist and cover the entire surface, the surface can be flattened and high-precision pattern formation can be performed. Further, the original surface level can be restored by removing the resist.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Here, a silicon nitride film 2 as an etching stopper is first formed on a surface of a silicon substrate 1 having a large step of about 1 μm, and a silicon oxide film 3 as a first interlayer insulating film is further deposited on the silicon nitride film 2. Silicon oxide film 3 on a large recess by photolithography
After selectively leaving only the above, a second interlayer insulating film is further formed on the entire surface of the substrate to flatten the surface.

First, as shown in FIG. 1 (a), a silicon nitride film 2 as an etching stopper is deposited to a thickness of about 20 nm on the surface of a silicon substrate 1 having a large step, and a first interlayer insulating film is further formed thereon. As a silicon oxide film 3
Is further deposited, and a photoresist R is applied to the upper layer, and the resist pattern R is left only on the large concave portion by photolithography. Silicon oxide film 3
The film thickness can be freely changed, and the same film thickness (1 μm) is required to eliminate all large steps.

Then, using the resist pattern R as a mask, an ammonium fluoride solution (NH ₄ OH) or a hydrofluoric acid (HF) solution is used to selectively etch away the silicon oxide film 3 in the region exposed from the resist pattern R. (Fig. 1 (b)). In this way, the silicon oxide film 3 is selectively left only in the recesses. Since the silicon nitride film acts as an etching stopper during this etching, there is no risk of affecting the base even if the etching is overetched. Although isotropic etching is used here, anisotropic etching may be used.

After removing the resist pattern R by peeling, as shown in FIG. 1 (c), for example, phosphorus glass is formed as a second interlayer insulating film by the CVD method, and is heated to about 850 ° C. to be melted. Is flattened. As a result, the large step is eliminated, and only the smooth small step is provided, and the accuracy of lithography on the step can be considerably improved. However, since small irregularities on the surface still remain, resist R2 is applied to the entire surface of the substrate as shown in FIG. 1 (c), and etch back is performed.

As a result, the surface is completely flattened. The lithography technique may be performed in this manner. This method is performed by a normal lithography technique or as shown in FIG. 1 (d). That is, a carbon film 5 as an antireflection film is deposited, and a resist film R3 having a film thickness of about 0.5 μm
To form. Here, since the substrate surface is completely flattened, the film thickness of the resist can be thin. However, when the resist is thin, the reflection on the substrate surface becomes remarkable, and thus the antireflection film is provided in this manner to further improve the pattern accuracy.

The resist film R3 thus formed is subjected to pattern exposure to form a resist pattern,
The interlayer insulating film is etched using this resist pattern as a mask. Alternatively, the interlayer insulating film may be etched by first patterning the carbon film using the resist pattern as a mask, removing the resist pattern if necessary.

As described above, according to the present invention, since the resist thinned to the limit is formed on the flat surface, the accuracy of photolithography becomes extremely high, and it is possible to form the contact hole or wiring with extremely high pattern accuracy. Becomes

Although carbon is used as the antireflection film in the above-mentioned embodiment, since carbon has an etching selection ratio of about 5 times with silicon, silicide or Al film, it also effectively acts as an etching resistant film, Even if the resist film is thin, it can sufficiently withstand etching.

The antireflection film is not limited to carbon, and a metal film such as titanium nitride may be used, or the antireflection film may not be provided.

Further, although this carbon film also acts as an etching resistant film, it is also possible to adopt a method of enhancing the etching resistance of the resist itself, such as incorporating silicon into the resist.

Next, a second embodiment of the present invention will be described.

In this example, the film used as the etching stopper during the formation of the self-aligned contact in the normal device formation without using a new film as the etching stopper was also used as the etching stopper for planarization. To do.

2A to 2C are process diagrams showing the pattern forming process.

First, a silicon oxide film as a gate oxide film 12 and a polycrystalline silicon film as a gate electrode 13 are sequentially deposited on the surface of a silicon substrate 11 having a specific resistance of 4 to 6 Ω / cm, and these are patterned by photolithography. The periphery of the gate electrode is covered with a protective insulating film 14 made of a silicon oxide film or a silicon nitride film, and ion implantation is performed to form a desired element region (not shown) such as a source / drain. Then, the surface is lightly oxidized to form a thin silicon oxide film 15, and a silicon nitride film 16 as an etching stopper is formed thereon. Then, as a first interlayer insulating film, B is formed by a CVD method.
The PSG film 17 is formed. Here, the surface of the substrate projects due to the presence of the gate electrode to form a large step. Here, reflow or etch back may be performed if necessary. Further, similarly to the first embodiment, a photoresist R is applied to this upper layer, and the resist pattern R is left only on the large concave portion by photolithography (FIG. 2 (a)).

Then, using the resist pattern R as a mask, the BPSG film 17 in the region exposed from the resist pattern R is selectively removed by etching using an ammonium fluoride solution (NH ₄ OH) or a hydrofluoric acid (HF) solution. Then, the BPSG film 17 is selectively left only in the recess. Since the silicon nitride film acts as an etching stopper during this etching, there is no risk of affecting the base even if the etching is overetched.

Then, after removing the resist pattern R by peeling, as shown in FIG. 2 (b), a second interlayer insulating film B is formed.
The PSG film 18 is formed by the CVD method. Here, flattening is also performed if necessary. Then, a resist is applied to the entire surface of the substrate as an upper layer to form a resist pattern for forming a self-aligned contact, and using this resist pattern R3 as a mask, an ammonium fluoride solution (NH ₄ OH) or hydrofluoric acid (HF) is formed. With the solution
The BPSG films 18 and 17 in the contact region are selectively removed by etching. At this time, since the silicon nitride film 16 acts as an etching stopper, there is no risk of etching the base.

After etching the silicon nitride film 16 in the contact region by using the thin silicon oxide film 15 as a stopper, or at the same time with the etching, the thin silicon oxide film 1 is removed by etching to expose the silicon substrate 11 to obtain a desired wiring. A pattern 19 is formed (FIG. 2 (c)). Since the surface is flattened when the wiring pattern is formed, the pattern accuracy is extremely good. Although the silicon nitride film is used as the etching stopper in the second embodiment, a polycrystalline silicon film may be used.

As a third embodiment of the present invention, a polycrystalline silicon film is used as an etching stopper and a stacked type DR is used.
A method of forming the AM will be described with reference to FIGS. 3 (a) to 3 (c).

In this example, the plate electrode 3 of the capacitor is used to form a laminated DRAM of the post-fabrication type of bit line.
2 is used as an etching stopper for the bit line contact 33 and as an etching stopper for flattening the interlayer insulating film.

This DRAM has a p with a specific resistance of about 5 Ω · cm.
Isolation insulating film 2 formed in the silicon substrate 21 of the mold
The n-type diffusion layers 26a and 26b forming the source / drain regions and the gate insulating film 24 are formed between the source / drain regions in the active region separated by 2. A gate electrode 25 and a gate electrode 25 form a MOSFET, and a storage node electrode 30 is formed so as to contact the n--type diffusion layer 26b through a storage node contact 28, and an upper layer plate electrode 32 is formed. The capacitor is formed by interposing the capacitor insulating film 31 between them. Then, a bit line 24 is formed via the bit line contact 23 formed on the interlayer insulating film 27b planarized by the resist. The gate electrodes 25 are continuously arranged in one direction of the memory array to form word lines.

Next, a method of manufacturing this DRAM will be described with reference to the drawings.

First, as shown in FIG. 3 (a), the specific resistance is 5Ω.
・ Normal L on the surface of p-type silicon substrate 21 of about cm
After forming an element isolation insulating film 22 and a p-type diffusion layer (not shown) for a punch through stopper by the OCOS method, a gate insulating film 24 made of a silicon oxide film having a film thickness of about 10 nm is formed by a thermal oxidation method. .. Then, a polycrystalline silicon film as a gate electrode material is deposited on the entire surface to a thickness of about 150 nm, and an insulating film such as a silicon oxide film is deposited to a thickness of about 100 to 300 nm on the upper layer by LPCVD.
The gate electrode 25 and the insulating film 27u on the gate are simultaneously patterned by using the photolithography technique and the anisotropic etching technique. Here, as the insulating film on the gate electrode, a silicon nitride film or a composite film of a silicon nitride film and a silicon oxide film may be used. The silicon nitride film is
Compared with a silicon oxide film, it has a stronger etching resistance against the treatment using a dilute HF solution performed at the time of contact formation and wiring formation, and thus is more effective in preventing a short circuit between the wiring of the gate electrode and the contact. Then, using the gate electrode 25 as a mask, As or P ions are ion-implanted to form the source / drain regions 26a and 26b made of n @-type diffusion layers, thereby forming MOSFETs as switching transistors. The depth of this diffusion layer is, eg, about 150 nm. After this, thermal oxidation is performed if necessary to improve the breakdown voltage of the gate insulating film,
Further, an insulating film consisting of a silicon oxide layer or a silicon nitride layer having a film thickness of about 100 nm or less is deposited on the entire surface by the CVD method, and the entire surface is etched by the reactive ion etching method to self-align with the side surface of the gate electrode 25. The side wall insulating film 27s is left as it is. As the side wall insulating film 27s, a withstand voltage can be further improved by using a silicon nitride film as in the case of the gate insulating film. Then, with the surfaces of the n- diffusion layers 26a and 26b exposed from the sidewall insulating film 27s and the upper insulating film 27u exposed, a polycrystalline silicon film is deposited on the entire surface to a thickness of about 100 to 400 nm, and phosphorus or arsenic is deposited thereon. The storage node electrode 30 is formed by doping and patterning by photolithography and reactive ion etching. Then, a silicon nitride film having a film thickness of about 10 nm is deposited by the CVD method, and then oxidized in a steam atmosphere at about 900 ° C. for about 30 minutes to form a silicon oxide film, which has a two-layer structure of a silicon nitride film and a silicon oxide film. The capacitor insulating film 31 is formed. At this time, the silicon nitride film and the silicon oxide film are also formed on the n @-diffusion layer 26a forming the bit line contact. Further, a polycrystalline silicon film is deposited on this upper layer, and after doping, the plate electrode 32 is patterned by the photolithography technique and the reactive ion etching technique. Here, the plate electrode and the capacitor insulating film are patterned so as to cover the n @-diffusion layer 26a. This is because the plate electrode and the capacitor insulating film are used as an etching stopper. Here, the surface of the substrate projects due to the presence of the gate electrode and the capacitor, forming a large step. In this state, the BPSG film 37 is formed as the first interlayer insulating film by the CVD method similarly to the second embodiment. Here, reflow or etch back may be performed if necessary. Then, a photoresist R is further applied to this upper layer, and a large concave portion, that is, MO
The resist pattern R is left only on the peripheral circuit portion where the SFET and the capacitor are not formed (FIG. 3 (a)).

Next, using the resist pattern R as a mask, the BPSG film 37 in the region exposed from the resist pattern R is selectively removed by etching using an ammonium fluoride solution (NH ₄ OH) or a hydrofluoric acid (HF) solution. Then, the BPSG film 37 is selectively left only in the recess. During this etching, the polycrystalline silicon film serving as the plate electrode 32 functions as an etching stopper, so that there is no risk of affecting the base even if the etching is overetched.

Then, after removing the resist pattern R by peeling, as shown in FIG. 3 (b), a second interlayer insulating film B is formed.
The PSG film 38 is formed by the CVD method. Here, flattening is also performed if necessary. Then, a resist is applied on the entire surface of the substrate as an upper layer to form a resist pattern for forming a self-aligned contact, and using this resist pattern R3 as a mask, a hydrofluoric acid (HF) solution is used to form a BPSG film 38 in the contact region. , 37 are selectively removed by etching. At this time, since the plate electrode 32 acts as an etching stopper, there is no risk of etching the base. Then, using the capacitor insulating film 31 as a stopper, the plate electrode 3 in the contact region is
2 is removed by etching, and then an insulating film for insulating the plate electrode from a bit line to be formed later is formed by oxidation using a water vapor atmosphere or the like, and the capacitor insulating film 31 is removed by etching to remove the silicon substrate. 21
The n-diffusion layer 26a on the surface is exposed to form a bit line pattern 34 made of a polycrystalline silicon layer (FIG. 3 (c)).
). Here, since the surface is flattened when the bit line pattern is formed, the pattern accuracy is extremely good.

According to this method, since the plate electrode is used as the etching stopper, it is possible to provide a highly reliable DRAM without increasing the number of steps.

According to the method described above, the insulating film such as the silicon oxide film or the BPSG film is used to fill the lower region to flatten the surface. In the case of these methods, the resist pattern itself can be formed with high accuracy, but in reality, the contact depth varies, and when it is matched with a deep contact, overetching occurs in the shallow contact region while the shallow contact region is formed. If it is matched with the contact, there arises a problem that the contact cannot be made in the deep contact portion. Therefore, in order to solve this problem, a method will be described in which a resist is used as a filling material for level matching and the surface is flattened by this. In this method, if the resist is removed after the lithography process, the original step is restored and the contact depth is not affected.

First, here, a silicon oxide film 32 as an interlayer insulating film which is not completely flat is formed on the surface of a silicon substrate 31 having a large step, and a first resist film R1 is formed.
Is applied (Fig. 4 (a)).

Then, by photolithography, the first
Of the resist film R1 is selectively exposed and developed to form a first resist pattern R1, and a large step region is filled with the first resist pattern. If necessary, baking may be performed to bring the resist into a molten state, and the resist may be smoothed as indicated by a chain line in FIG. 4 (b).

Then, as shown in FIG. 4C, the original resist is applied as a second resist R2. At this time, the surface is in a flat state.

Then, pattern exposure is performed through a mask and development is performed to form a resist pattern R2 as shown in FIG. 4 (d). Here, since the exposure is performed on the flat substrate surface, it is possible to focus on the entire surface, which enables highly accurate pattern formation.

Finally, as shown in FIG. 4 (e), a highly accurate resist pattern is obtained by etching the second resist by RIE using this resist pattern R2 as a mask.

If the edge of the first resist pattern is sharp at the end, the film thickness of the second resist in the vicinity of the edge becomes large and light cannot reach sufficiently. The pattern is thick in resist (Fig. 4 (d)
However, in the case of the negative type resist, the pattern becomes thin (see FIG. 4).
(D) n1) may occur. This problem can be alleviated by baking as described above.

In this case, the first resist may not have photosensitivity, but if it has photosensitivity, it may be exposed simultaneously with the exposure of the second resist. Further, although the first resist is patterned by photolithography in the above-mentioned embodiment, after the first resist R is applied on the entire surface as shown by the dotted line as shown in FIG.
You may polish and planarize from the top by polishing. After that, the method of the fourth embodiment shown in FIGS. 4 (c) to 4 (e) may be performed.

Further, as shown in FIG. 6, the first resist R1 of FIG. 5 may be left on the entire surface after planarization.

Further, as shown in FIG. 7, a carbon film, a titanium nitride film or the like 40 as an antireflection film may be interposed between the first and second resists.

Further, as shown in FIG. 8, a carbon film, a titanium nitride film or the like 40 as an antireflection film is previously formed on the surface of the substrate (interlayer insulating film), and a first resist R1 is formed thereon. good.

As another embodiment of the present invention, a resist having a three-layer structure will be described.

First, as shown in FIG. 9 (a), a substrate 5 having a large step on which a base film to be patterned is formed.
On the surface of No. 1, the first resist film R1
Is applied, and the first resist film R1 is selectively exposed by photolithography and developed to form a first resist pattern R1, and a large step region is filled with the first resist pattern. Here again, baking may be performed as necessary to bring the resist into a molten state and smooth it. Alternatively, it may be flattened by polishing from above by polishing.

Then, as shown in FIG. 9B, a second resist R2 is applied to smooth small irregularities.

Further, as shown in FIG. 9 (c), as the third resist R3, an image reversal type resist called AZ5214 manufactured by Shipley Co. is used as a third resist R3 at a rotation speed of 3500 rp.
m is spin-coated to form a resist film having a film thickness of 1 μm, and then prebaked at 90 ° C. for 5 minutes.

Then, using an optical stepper, the wavelength is 436 nm.
Light is used to transfer the pattern onto the resist film R3 on the substrate 51 to form a latent image I of the mask pattern. The exposure amount at this time was 20 mJ / cm ² . And 105 ℃,
Post-baking treatment is performed for 90 seconds to accelerate the crosslinking reaction in the exposed area. As a result, the surface blocking layer 55S is formed on the surface of the exposed region 55. After this, the entire surface of the substrate is exposed using a light beam from a mercury lamp. The exposure amount at this time was 200 mJ / cm ² .

Then, this substrate is placed in a vacuum chamber, the inside of the chamber is replaced with nitrogen, and then hexamethyldisilazane vapor is introduced into the chamber while heating the substrate to perform a silylation treatment. By this silylation treatment, the exposed area in the pattern exposure step is not silylated, and the silylated layer 56 is selectively formed in the remaining non-exposed area as shown in FIG. 9 (d).

Then, as shown in FIG. 9 (e), the silylated layer 6 is left by reactive ion etching with oxygen gas, and the region left unsilylated is selectively removed. At this time, the etching conditions are oxygen flow rate 100SCC.
M, pressure 6.0 Pa, power 150 W.

In this way, a highly precise pattern of 0.4 μm could be obtained. This is probably because the three-layer resist was applied and flattened, and then pattern exposure was performed in advance, and the exposure process for silylation was the entire exposure, whereby silylation could be reliably performed. ..

That is, in this case, by heating after the pattern exposure, the substance generated by the reaction between the photosensitizer and the light serves as a catalyst in the pattern exposed region to promote the crosslinking of the resin,
The molecular weight is increased. Then, in the whole surface exposure step, the region other than the pattern exposure region is completely exposed up to a deep region, and the photosensitive agent is exposed to the silylation easily. On the other hand, in the pattern exposure region where the molecular weight has increased, the introduction of silicon is blocked and silylation does not occur. In this way, a pattern with high contrast can be formed.

In this step, if the silicon compound adhering to the surface of the unsilylated region is removed prior to the reactive ion etching with oxygen gas, it is possible to form a highly accurate pattern. ..

Further, in this step, in the pattern exposure step and the exposure step for silylation (entire surface exposure),
The exposure conditions such as wavelength and irradiation energy may be selected independently so as to be optimal for each, and it is possible to further improve the resolution by selecting the optimal conditions.

Using the resist pattern thus obtained as a mask, the second resist film R2 is etched by reactive ion etching, and the first resist film R1 is further etched, whereby a highly accurate and good pattern is obtained. Can be formed. Although the resist has a three-layer structure in the above embodiment, it may have a two-layer structure, and may or may not have photosensitivity except for the third resist. Good. Further, as the third resist, any resist having high etching resistance such as a silicon-containing resist may be used.

Although a silicon substrate was used as the substrate in the above-mentioned embodiments, it goes without saying that a compound semiconductor such as germanium or gallium arsenide, or those having an epitaxial growth layer formed on the surface thereof may be used. Absent.

[0064]

As described above, according to the present invention, it is possible to form a highly accurate pattern even on a substrate surface having a large step.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a modified example of the present invention.

FIG. 6 is a diagram showing a modified example of the present invention.

FIG. 7 is a diagram showing a modified example of the present invention.

FIG. 8 is a diagram showing a modified example of the present invention.

FIG. 9 is a manufacturing process diagram of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a method of a conventional example.

FIG. 11 is a diagram showing a method of a conventional example.

[Explanation of symbols]

 1 silicon substrate 2 silicon nitride film 3 silicon oxide film R1 resist R2 resist R3 resist 11 silicon substrate 12 gate oxide film 13 gate electrode 14 protective insulating film 15 silicon oxide film 16 etching stopper (silicon nitride film) 17 BPSG film 18 BPSG film 19 Wiring pattern 21 Silicon substrate 22 Element isolation insulating film 23 Bit line contact 24 Gate insulating film 25 Gate electrode 26a, 26b n- type diffusion layer 27 Interlayer insulating film 28 Storage node contact 30 Storage node electrode 31 Capacitor insulating film 32 Plate Electrode (etching stopper) 34 Bit line 37 BPSG film 38 BPSG film

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yoshinori Matsubara 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Within Toshiba Research Institute, Inc. (72) Inventor Go Shibata 1 Komu-shi Toshiba-cho, Kawasaki-shi, Kanagawa Inside Toshiba Research Institute, Inc. (72) Inventor Eiji Shiobara 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa 1 Shares within Toshiba Research Institute

Claims (2)

[Claims] 1. A first interlayer insulating film forming step of forming a first interlayer insulating film on the entire surface of the semiconductor substrate when forming an interlayer insulating film on the surface of a semiconductor substrate having a step, and the first interlayer insulating film. A first etching step of patterning the insulating film to selectively leave a first interlayer insulating film for level adjustment in the lower region of the step, and a second interlayer insulating film on this upper layer and further covering the entire surface of the substrate. A second interlayer insulating film forming step of forming a film. 2. When patterning a stepped substrate surface or a film formed on a stepped substrate surface, a first resist is applied onto the stepped substrate surface or the film formed on the stepped substrate surface. Then, the first resist forming step of selectively removing the resist in the upper region of the step and leaving the first resist for level adjustment selectively only in the lower region of the step, and the first resist forming step of covering the entire surface further. 2 resist is formed,
A second resist forming step of patterning at least the second resist by photolithography, and a step of patterning a substrate surface or a film formed on the substrate surface using the second resist as a mask. Method for manufacturing semiconductor device.