JPH05314764A - Dual port memory - Google Patents

Abstract

PURPOSE:To reduce power consumption by separately providing power sources for other circuit and for a shift register or a substrate voltage generator, and automatically stopping the substrate voltage generator when power supply to the shift register is unnecessitated. CONSTITUTION:The shift register 2 transfers an arbitrary row with (n) bits stored in a memory cell array 1 en bloc and a control circuit 4 controls a whole circuits by inputting an address and control signal 5. In such a case, the power source inputs for other circuits 8-1 and for the shift register 8-2 and/or the substrate voltage generator 3 are separately provided. When power supply to the shift register is unnecessary, the other generator 3 is interrupted by the circuit 4. Thus, the leakage in the MOS transistors at the time of standby operation of the memory is decreased and power consumption of the other generator is largely reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port memory used for storing a display image in a computer or the like, and more particularly to reducing the power consumption thereof.

[0002]

2. Description of the Related Art A conventional dual port memory will be described with reference to FIG. In the figure, reference numeral 1 is a memory cell array composed of n bits × m bits and manufactured by the MOS transistor technology, in which information such as a display image is stored. Reading and writing of data to and from the memory cell array 1 is performed via the data signal 6.
Information on an arbitrary row consisting of n bits on the memory cell array 1 can be collectively transferred to the shift register 2.
The transferred information can be sequentially output from the serial data signal 7 bit by bit by the shift register 2. This serial data signal is normally sent to a display device such as a CRT. The above operation is controlled by the control circuit 4 and the address and control signal 5 input to the control circuit 4. In addition to the above, there is a substrate voltage generator 3 for generating a substrate voltage, which is a normally negative voltage required for the power input and the MOS transistor, from the power input by a method such as a charge pump.

[0003]

In recent years, in devices such as personal computers and EWS, when there is no keyboard input for a certain period of time, only the display device and circuits necessary for display are turned off, and immediately after that, keyboard input is made. A low power consumption technology that restores the function of the device immediately after turning on the power, and a so-called suspend / resume function that keeps the data on the memory including the display system in the battery even when the power of the device is turned off is used. It has become so.

In such a case, the dual port memory for storing a display image is in a so-called standby state, or even for a shift register circuit portion which originally does not need to be supplied with power for performing parallel / serial conversion for the display device. It was powered. At this time, the power consumed in the standby state is divided into the channel leak of the MOS transistor and the power consumption of the substrate voltage generator, but there are the following problems. 1) The shift register part is 2 to 2 on the actual silicon chip.
It occupies 30% of the circuit area and wasted power accordingly. 2) Since the substrate voltage is supplied to the unused shift register section, the substrate voltage generator consumes useless power.

[0005]

SUMMARY OF THE INVENTION The present invention is a dual port memory which is composed of a memory cell array and a shift register capable of batch-transferring any row of this array and which is manufactured by MOS transistor technology. And a second power input for supplying power to other circuits.

The present invention comprises a memory array manufactured by MOS transistor technology, a shift register capable of batch-transferring any row of this array, and a substrate voltage generator for generating a substrate voltage required for MOS transistors. In a dual port memory, a first substrate voltage generator for supplying power to the shift register and a second substrate voltage generator for supplying power to other circuits are provided, and it is generated when it is not necessary to supply power to the shift register. The operation of the first substrate voltage generator is stopped by a control signal.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Reference numeral 1 denotes a memory cell array device for storing image information, which is provided with a shift register 2 capable of collectively transferring an arbitrary row of n bits on the memory cell array device. 3 is a substrate voltage generator, 4 is a control circuit for controlling the entire circuit by inputting an address and a control signal 5, and 6 is data for inputting and outputting information of the display image with a graphic controller for changing the display image. 7 is a serial data signal for sending the serial output of the shift register to the display device.

In this embodiment, the power input is provided separately from the power input 8-2 of the shift register section and the other power input 8-1. Figure 1 shows each power input
The range in which power is supplied by 1 and 8-2 is surrounded by a broken line. In an actual dual port memory, the shift register portion occupies 20 to 30% of the circuit area of the chip. Therefore, with the above configuration, 1/2 to 1/3 of the power consumption during the standby operation of the dual port memory is occupied. MOS
The channel leak current of the transistor can be reduced by 20 to 30%.

FIG. 2 is a block diagram of another embodiment of the present invention.

In the description of this embodiment, the description of the parts having the same reference numerals as in FIG. 1 will be omitted.

In this embodiment, a substrate voltage generator 3-2 for feeding the shift register portion and a substrate voltage generator 3-1 for feeding the other portions are separately provided. In addition, a control signal 9 generated by the control circuit 4 and indicating that the shift register portion does not need to be supplied with power is provided, and the control signal 9 causes the substrate voltage generator 3-2 to stop operating.

Usually, these substrate voltage generators are charge pumps composed of an oscillator and a capacitor, and by stopping the oscillation by the control signal 9, the power consumption of the voltage generator can be greatly reduced.

As an example of a concrete generation of the control signal 9, when a specific timing condition is set in a general-purpose DRAM in recent years, a normal read / write operation is not accepted and a refresh operation including generation of a refresh address is internally performed in the chip. Although the self-refresh mode for performing only this is becoming popular, it is possible to realize this self-refresh mode on a dual port memory, and the control signal 9 can be easily generated in combination with this function.

It is also possible to realize a dual port memory by combining the embodiment of FIG. 1 and the embodiment of FIG.

[0016]

As described above, in the present invention, in order to reduce the power consumption of the device, the circuit area on the chip occupies 20 to 30% in the standby operation of the dual port memory, and the power is consumed at the same rate. The power consumption of the consumed shift register portion can be reduced by separating the power source of the shift register portion from the power source of other circuits.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a block diagram of a memory of a conventional dual port memory.

[Explanation of symbols]

 1 memory cell array 2 shift register 3, 3-1 and 3-2 substrate voltage generator 4 control circuit 5 address and control signal 6 data signal 7 serial data 8, 8-1, 8-2 power input 9 substrate voltage generation Control signal

Claims (2)

[Claims] 1. A memory cell array and a shift register capable of collectively transferring any row of this array,
A dual-port memory manufactured by MOS transistor technology, comprising a first power supply input for supplying power to the shift register and a second power supply input for supplying power to other circuits. 2. A memory array manufactured by MOS transistor technology, a shift register capable of collectively transferring an arbitrary row of the array, and a substrate voltage generator for generating a substrate voltage required for the MOS transistors. In a dual port memory, a first substrate voltage generator for supplying power to the shift register and a second substrate voltage generator for supplying power to other circuits are provided, and control is generated when it is not necessary to supply power to the shift register. A dual port memory, characterized in that the operation of the first substrate voltage generator is stopped by a signal.