JPH05313775A - Lookup table and digital filter - Google Patents

Abstract

PURPOSE:To shorten time required to update the lookup table by providing a circuit generating table values according to necessary inputted parameters in the system writing signals into RAM and supplying the same clock required to the real time processing for the lookup table to the circuit. CONSTITUTION:A circuit 1 generating a table value according to the necessary inputted parameter 3 is provided on the system writing signals into RAM 2, and supplies the same clock 4 required to the real time processing of the lookup table to the circuit. A circuit 1 generating table values inputting coefficient values and signals for starting generating table values is provided with a counter starting the operation when the signals starting generating table values are inputted and a circuit taking the counter output as the address signal of a memory and multiplying the counter output by the coefficient value. The output of the circuit is outputted as memory data corresponding to the address signal. Thus, the time required to update the lookup table can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit for performing an operation using a look-up table, and more particularly to a signal processing circuit for rapidly updating the contents of the look-up table.

[0002]

2. Description of the Related Art Conventionally, a digital filter using a look-up table has been realized by the circuit shown in FIG. This circuit is a digital filter in which real-time input data is delayed by different sampling cycle units and multiplied by a predetermined coefficient to obtain the sum of the results.

Random access memory 2 used
(Random Access Memory; hereinafter abbreviated as RAM) is used as a multiplication circuit by previously writing the product of the address value and a predetermined coefficient to all the addresses. The delayed data is input to the address terminal of the memory, and all the products of the data output from the data terminal and the predetermined coefficient are added to obtain the filter output.

[0004]

In the above-mentioned conventional circuit, R
There arises a problem that it takes a huge amount of time to write data to the AM2.

Writing of data to the RAM 2 is performed by the microcomputer 10. The microcomputer 10 calculates a predetermined product while updating the address value 5, and writes it in the RAM 2. Calculation and transfer of data by the microcomputer 10 requires several machine cycles. In addition, the frequency of the operation clock is at most about 10 MHz, which is generally about 1/10 of the operation frequency of the digital filter.

It is assumed that 5 machine cycles are required for the calculation and data transfer by the microcomputer 10, and this is executed with an operating clock of 10 MHz (100 ns cycle). In order to realize an 8-bit input multiplier, it takes 100 ns × 256 × 5 = 128 μs since 256 words of information have to be transferred to the table. Conventionally, in order to shorten this,
A method such as DMA transfer (Direct Memory Access) has been adopted to save the transfer time even if the calculation takes time. However, even with this method,
The transfer frequency is limited by the clock supplied to the microcomputer 10. Even if one data can be transferred in one machine cycle, the time required for the transfer can be reduced to only 1/5 of the above value to 25.6 μs. A digital signal processing circuit that performs an operation using a lookup table is not adopted due to the limitation of the table value generation time as described above, although it is advantageous in terms of power consumption as compared with a parallel multiplication circuit or the like. There were many cases.

Also, the microcomputer 10 has to spend a lot of time for calculating table values and transferring data, which is a major limitation in creating a control program.

[0008]

As shown in FIG. 1, a circuit 1 for generating a table value according to a necessary input parameter 3 is provided in a write signal system to a RAM 2 and a look-up table of the circuit is provided in the circuit. It is solved by supplying the same clock 4 used for real time processing.

[0009]

The operation of the circuit shown in FIG. 1 is as follows. That is, the parameter 3 necessary for calculation and the clock 4 at the time of actual operation of the RAM 2 are input to the table value generation circuit 1, and R
The address 5 to be written to the AM2, the data 6 corresponding to it, and the read / write control signal 7 are output.

After the parameter 3 necessary for the calculation is set from the outside, the table value generating circuit 1 starts the operation in synchronization with the clock 4 supplied to the RAM 2 which is a look-up table. Simultaneously with the start of the operation, the read / write control signal 7 is changed to the write side so that the output of the table value generation circuit 1 is supplied to the RAM 2. The address 5 of the RAM 2 to be written is sequentially
At the same time as the output, the result of performing a predetermined operation on the value is stored in the RAM 2. When the values stored in all the addresses to be updated are updated, the read / write control signal 7 is changed to the read side, and the operation as the lookup table of the RAM is restarted. If necessary, a signal for notifying the restart of the operation as the look-up table, which is easily generated from the read / write control signal 7 is output to the outside.

[0011]

FIG. 1 shows an embodiment of the present invention. A circuit 1 for generating a table value in accordance with the required input parameter 3 is provided in the write signal system to the RAM 2, and the same clock 4 as that used for the real-time processing of the look-up table is supplied to the circuit. The table value generation circuit 1 is supplied with a parameter 3 required for calculation and a clock 4 at the time of actual operation of the RAM 2, and outputs an address 5 to be written in the RAM 2, data 6 corresponding thereto, and a read / write control signal 7. To do.

After setting the parameter 3 required for the calculation from the outside, the table value generating circuit 1 starts the operation in synchronization with the clock 4 supplied to the RAM 2 which is a look-up table. Simultaneously with the start of the operation, the read / write control signal 7 is changed to the write side so that the output of the table value generation circuit 1 is supplied to the RAM 2. The address 5 of the RAM 2 to be written is sequentially
At the same time as the output, the result of performing a predetermined operation on the value is stored in the RAM 2. When the values stored in all the addresses to be updated are updated, the read / write control signal 7 is changed to the read side, and the operation of the RAM 2 as the lookup table is restarted. If necessary, a signal for notifying the restart of the operation as the look-up table, which is easily generated from the read / write control signal 7 is output to the outside.

An embodiment of the present invention is shown in FIG. The table generation circuit 1 includes a counter 101 that gives an address value,
An arithmetic circuit 102 that multiplies the value of the counter 101 by a predetermined coefficient and a circuit 103 that inputs and stores the predetermined coefficient from the outside. Counter 101, arithmetic circuit 10
2 is supplied with the same clock 4 used for real-time processing of the look-up table. From the outside, a signal 8 for instructing the start of update of the look-up table is input after the setting of the coefficient value is completed, and this is input to the set terminal of the set / reset flip-flop 104. Upon receiving this signal, the internal clock 4 is applied to the counter 101 and the arithmetic circuit 102. The counter 101 sequentially updates the address value from 0. The arithmetic circuit 102 outputs the result of multiplying the address value 5 by a predetermined coefficient, and stores the result in the RAM 2. The counter 101 issues a carry signal 9 for detecting the end when counting up by the effective address of the RAM 2. The carry signal 9 is used for resetting the counter 101 itself and for the set / reset flip-flop 104.
Reset. This signal can be output to the outside as the signal 9 indicating that the update of the lookup table is completed. The counter 101 is also reset when the power is turned on. The table update start signal 8 can also be used as a reset signal.

Set / Reset Flip-Flop 10
With the reset of 4, the counter 101 and the arithmetic circuit 1
The supply of the clock to 02 is stopped. As a result, the arithmetic circuit 102 operates only when updating the table value,
Since the operation is stopped during the actual operation, power consumption is saved. Conversely, set / reset flip-flop 1
By using the output signal of 04 to stop the operation of other circuits during the table update, the power consumption during the table update is saved. This effect can be obtained similarly in the other examples.

Although the present embodiment has been described on the assumption that the operation is multiplication by a fixed coefficient, any operation circuit can have the same configuration. Further, when the arithmetic operation is complicated and the arithmetic circuit is constructed by a pipeline, a delay circuit for adjusting the output timing is inserted into the address output and the output of the set / reset flip-flop 104.

An embodiment of the present invention is shown in FIG. The present embodiment is an example in which the arithmetic circuit is simply configured by limiting the arithmetic operation to the multiplication of a fixed coefficient. The desired coefficient is the coefficient register 10
3 and stores the coefficient in synchronism with the counter 101 to obtain a multiplication result corresponding to the output of the counter 101. The integration register 105 is supplied with the same clock 4 as the counter 101, and the counter 10
It is reset by the carry signal 9 of 1, stores the previous output of the adder 106, and supplies it to the input of the same adder 106. The counter 101 and the integration register 105 are reset by the carry signal 9 of the counter 101 generated at the end of the previous table update and the reset signal when the power is turned on. With this configuration, for example, when 3 is given to the coefficient,
As the output of the counter 101 increases to 0, 1, 2, 3, 4, 5, the output of the adder 106 becomes 0, 3, 6, 9,
The number is increased to 12, 15 and the table fixed to the coefficient 3 is updated.

The bit limiting circuit 107 is a circuit for performing operations such as rounding, rounding down, and rounding up, and prevents accumulation of arithmetic errors. For example, if the coefficient is 1.3, the counter 10
As the output of 1 increases to 0, 1, 2, 3, 4, 5, the output of adder 106 becomes 0, 1.3, 2.6, 3.9,
When it is increased to 5.2 and 6.5 and rounded off by the bit limiting circuit 107, 0, 1, 3, 4, 5, and 7 are output. The coefficient is fixed at 1.3, and the table is updated with the output limited to integers.

Set / Reset Flip-Flop 10
4 and the operation of the AND circuit 108 for stopping the clock are shown in FIG.
Is exactly the same as that shown in.

An embodiment of the present invention is shown in FIG. The present embodiment provides a non-linear look-up table that changes the slope between the input and output values depending on the input value. FIG. 5 is an example of a circuit that provides a non-linear look-up table of a polygonal line that changes the gradient twice according to an input value. Such a non-linear look-up table of broken lines is often used when the input / output characteristics of a curve are approximated by broken lines.

In the case of the present embodiment, there are five parameters required for the calculation: the gradients a, b and c and the inflection points ab and bc. The inflection point is an input value at the time of changing the slope. This is realized by changing the way of giving the coefficients in the embodiment of FIG. In the present embodiment, the gradient change determination circuit 109 constantly compares the output value of the counter 101 with the inflection point. According to the determination result of the gradient change determination circuit 109, the selection circuit 110 gives a predetermined gradient value to the integration circuit 111.

An embodiment of the present invention is shown in FIG. In this embodiment, the look-up table is given a square characteristic. The parameter to be given from the outside is only the information that the table has the square characteristic. For square,
The difference between the square of a given integer n and the square of the preceding integer n-1 is 2n-1. The square of n is obtained at the output of the adder 106 by adding twice the counter value n to the output of the accumulation register 105 storing the square of n-1 and subtracting 1.

FIG. 7 shows a configuration example of a digital filter using the lookup table of the present invention as a multiplier. Data to be updated is supplied from one table generation circuit 1 to a plurality of lookup tables 2. The coefficient value of each look-up table is stored in the coefficient memory 103 in advance. As the counter 101, an address value 5 of the lookup table and an extra high-order several bits thereof are used. The upper few bits indicate the particular lookup table being updated. Control circuit 1
The high-order several bits are monitored at 12, and the integration register 105 is reset every time the bits change, and then the corresponding coefficient value is given to the integration circuit 111.

In the table value generating circuit 1, the number of lookup tables that can be updated at one time is determined in consideration of the time allowed for updating the table, and thus the number to be mounted is determined by this.

By applying the lookup table having the input / output characteristic of the broken line shown in FIG. 5 to the digital filter shown in FIG. 7, a digital filter having a nonlinear coefficient can be realized. A digital filter having a non-linear coefficient is effective for equalizing a signal that has been subjected to non-linear distortion or, conversely, for processing a signal that is known to be subjected to non-linear distortion. Particularly, in the case of the present embodiment, the time required to update the lookup table is significantly shortened compared to the conventional case, so that the distortion changes due to some factor, and it is effective when the lookup table is changed accordingly. Is.

An example of application to a waveform equalizing filter of a magnetic disk reader will be described below. in this case,
It is necessary to set an appropriate filter coefficient for each disk or track in which data is stored. Since it takes about 10 μs to change a disk or a track, the use of a look-up table has been hindered in the prior art. Therefore, a parallel multiplier is used, which causes a problem of high power consumption. In the present embodiment, since the problem of the limitation of the table update time is solved, a digital filter which consumes less power and can easily deal with the nonlinear coefficient is realized.

An example used for signal processing of a digital television will be described below. In this case, there is a process that requires setting an appropriate filter coefficient for each scanning line. At this time, the coefficient is updated in the horizontal blanking period 11.
It must be completed within 6 μs. In this example as well, the same effect as the example applied to the waveform equalization filter of the magnetic disk reader was obtained.

[0027]

According to the present invention, the time required to update the look-up table is significantly reduced as compared with the conventional case. In the past, it was assumed that 5 machine cycles were required for calculation and data transfer by a microcomputer,
It is assumed that the operation is performed with an operating clock of z (100 ns cycle). The circuit described in the embodiment of the present invention is 100 MHz.
When operated in z, one data update is completed in one machine cycle. At this time, the time required to update the lookup table is reduced to 1/50. It takes 125 μs to update an 8-bit input look-up table which is generally used, but it can be updated to 2.5 μs by implementing the present invention. For this reason, it has become possible to apply to fields that were conventionally limited by the table update time.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a third embodiment of the present invention.

FIG. 5 is a block diagram of a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a sixth embodiment of the present invention.

[Explanation of symbols]

1 ... table value generation circuit, 2 ... RAM, 3 ... parameters required for operation, 4 ... actual operation clock, 5 ... RAM address signal, 6 ... RAM data signal, 7 ... RAM read / write control signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Yano 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (6)

[Claims] 1. A look-up table configured by using a memory, comprising a table value generation circuit, and the generation circuit operates with a clock having a normal operating frequency of the look-up table. 2. The counter according to claim 1, wherein the table value generation circuit receives a coefficient value and a table value generation start signal, and starts operation when the table value generation start signal is input. A look-up table comprising a circuit for obtaining a product of the counter output and the coefficient value, using a counter output as an address signal of the memory, and outputting an output of the circuit for obtaining the product as data of the memory corresponding to the address signal. 3. The look-up table according to claim 2, wherein the circuit for obtaining the product is constituted by an integrating circuit for obtaining the product by integrating the coefficient values that operate in synchronization with the counter. 4. The method according to claim 3, further comprising a means for storing a plurality of the coefficient values and a means for storing an address value for switching the plurality of coefficient values, the difference of the integrating circuit according to the address value. A look-up table having means for changing to another coefficient value. 5. A digital filter according to any one of claims 1, 2, 3 or 4, wherein the look-up table is used. 6. A digital filter configured by a product-sum operation, wherein the product term is configured using a circuit having a nonlinear input / output characteristic.