JPH05308104A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device excellent in wiring reliability, regarding a manufacturing method of a semiconductor device having a characteristic of a forming method of multilayered wiring. CONSTITUTION:On a semiconductor substrate 1, a first metal film 2 of low resistivity is formed, thereon a second metal layer 3 of high resistance to etching is formed, a first metal wiring 4 is formed by working the films 2 and 3, a first insulating film 5 is formed on the metal wiring 4, a connection hole 6 penetrating the first insulating film 5 and reaching the metal wiring 4 is formed, and metal 7 for connection use is buried in the second metal film 3 contained in the first metal wiring 4 exposed in the bottom surface of the connection hole 6. On the first insulating film, a second metal wiring 8 is formed so as to cover the metal 7 for connection use buried in the connection hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device characterized by a method for forming a multi-layer wiring.

[0002]

2. Description of the Related Art With the recent demand for higher speed computer systems, there is an increasing demand for higher integration and higher speed of semiconductor integrated circuits. Therefore, not only miniaturization of semiconductor elements but also miniaturization of wiring and multi-layering are becoming more and more important. In order to realize such multi-layer wiring, it is particularly important to develop a technique for flattening an interlayer insulating film and a technique for forming a wiring in a fine connection hole that connects wiring layers of the multi-layer wiring. Therefore, it is necessary to improve the reliability of the multilayer wiring.

In the conventional formation of multi-layered wiring, an SOG coating method, an organic resin film coating method, an etch back method and the like are used as a method for flattening an interlayer insulating film. In this
The flattening by an organic resin film coating method such as polysiloxane or silicone resin has a simple process and excellent flatness.

However, the shape of the connection hole between the wiring layers becomes steep with the miniaturization, and the aspect ratio, which is the ratio of the diameter to the depth, becomes large, and the wiring layer formed by the conventional sputtering method has a deep connection hole. Since the wiring metal film has poor coverage,
Poor connection between wires is becoming a serious problem. As a multilayer wiring technology that can solve this problem, a method of selectively embedding metal in fine connection holes is promising. Currently, the mainstream of this technology is WF ₆ as a source gas and H as a reducing gas.
_{This is} a W selective CVD technique using ₂ or SiH ₄ .

[0005]

However, according to the conventional method of flattening the interlayer insulating film by the organic resin film coating method of polysiloxane or silicone resin and the selective CVD method of W,
In the method of combining the wiring formation in the wiring connection hole, the coating film thickness on the lower layer wiring differs depending on the density of the lower layer wiring pattern or the size of the lower layer wiring pattern. Therefore, a reactive ion etching (RIE) method using a fluorocarbon-based reaction gas is used. When the connection hole is opened by, the connection hole in the region where the pattern density is low is over-etched for a long time.

Therefore, the lower layer layout exposed on the bottom surface of the connection hole is
When the uppermost layer of the wire is Al, C, H, F on the Al surface
Residues consisting of atoms etc. remain, and such debris is usually
O ₂This cannot be removed by plasma treatment or chemical treatment.
After the step of burying W in the connection hole by the selective CVD method
In the connection hole on the metal wiring where the residue remains
Had a problem that W did not grow stably.

Further, when Au having a small amount of the residue as described above is used as the uppermost layer of the lower wiring which is exposed on the bottom surface of the connection hole, Au is sputtered and the side wall portion of the connection hole is formed due to the high sputtering rate of Au. When W is selectively grown, the W does not grow on the bottom surface of the connection hole because the W first grows on the upper edge of the connection hole, and the reliability of the wiring is impaired.
There has been a problem that it grows up over the side wall of the connection hole on the surface of the interlayer insulating film to impair the flatness and the reliability of the metal wiring formed thereon.

The present invention has been made in view of the above problems, and in particular ensures the flattening of the interlayer insulating film by the organic resin film coating method and the burying of the metal into the connection hole by the selective CVD method of the metal. It is an object of the present invention to provide a method for manufacturing a semiconductor device including a method for forming a multi-layered wiring, which can improve the reliability of the wiring by carrying out the method.

[0009]

In a method of manufacturing a semiconductor device according to the present invention, a step of forming a first metal film having a low resistivity on a semiconductor substrate, and a step of forming a resist film on the first metal film. A step of forming a second metal film having a high etching property,
A step of processing the first metal film and the second metal film to form a first metal wiring, and forming a first insulating film on the semiconductor substrate so as to cover the first metal wiring. And the first step
Forming a connection hole for metal wiring connection reaching the first metal wiring through the insulating film of the first metal wiring, and the second metal wiring included in the first metal wiring exposed on the bottom surface of the connection hole. The step of selectively embedding the connecting metal in the metal film of 1) and the step of forming the second metal wiring on the first insulating film so as to cover the connection hole are adopted.

In this case, a metal film containing at least Al or Au or an alloy thereof can be used as the first metal film having low resistivity, and Pt is used as the second metal film having high etching resistance. Can also,
A polysiloxane film or a silicone resin can be used as the first insulating film.

[0011]

1 is an explanatory view of the principle of the method of manufacturing a semiconductor device according to the present invention. In this figure, 1 is a semiconductor substrate, 2 is a first metal film, 3 is a second metal film, 4 is a first metal wiring, 5 is a first insulating film, 6 is a connection hole, and 7 is for connection. metal,
Reference numeral 8 is a second metal wiring.

According to the present invention, A
first metal film 2 having a low resistivity such as l and Au, and thin Pt
Etching-resistant second metal film 3 is formed, these two metal films are patterned to form first metal wiring 4, and first insulating film 5 is formed thereon. A connection hole 6 is formed in the first insulating film 5, a connection metal 7 is selectively formed inside the connection hole 6, and a second metal wiring 8 is further formed thereon.

As described above, the second metal film 3 having a high etching resistance such as Pt is thin, and most of the first metal wiring is a metal such as Al, Au or an alloy containing Al, Au or the like. Since it is the lower first metal film having a low resistivity, the wiring resistance of the first metal wiring 4 has no problem.

Since the upper second metal film 3 having a high etching resistance such as Pt is used, the first metal wiring 4 is formed.
In comparison with the prior art in which the upper layer is made of Al, the connection holes 6 are also formed in the regions where the pattern density is low, which is over-etched for a long time when the connection holes 6 are opened by the RIE method.
There is little residue consisting of C, H, F atoms and the like remaining on the bottom surface of the, so that stable growth can be secured when W is embedded in the connection hole 6 by the selective CVD method thereafter.

FIG. 2 is a graph showing the difference in dry etching resistance between Pt and Au. The horizontal axis of this figure represents the etching time and the vertical axis represents the etching depth. It is shown that Pt has a higher dry etching resistance than Au and is less likely to be etched than Au. in this way,
Since Pt has higher dry etching resistance than Au, R
When the connection hole is opened by the IE method, the metal wiring is not sputtered and attached to the side wall portion of the connection hole. For this reason,
In the step of burying W in the connection hole by the selective CVD method, since W does not grow on the side wall portion, stable growth can be secured and the reliability of the wiring can be improved.

[0016]

EXAMPLES Examples of the present invention will be described below. Figure 3
(A) to (E) are for manufacturing a semiconductor device of one embodiment of the present invention.
It is explanatory drawing of a manufacturing method. In this figure, 11 is a semiconductor
Substrate, 12 is the first SiO₂Film, 13 is the first Ti film,
14 is the first Au film, 15 is the first Pt film, and 16 is the first
Ti / Au / Pt film, 17 is the second SiO₂Membrane, 18
Is a PMSS resin film, 19 is a third SiO ₂Membrane, 20 contact
Continuous hole, 21 is a W film, 22 is a second Ti film, and 23 is a second film.
Au film, 24 is second Pt film, 25 is second Ti / Au
/ Pt film.

The method of manufacturing the semiconductor device of this embodiment will be described below with reference to this drawing.

First step (see FIG. 3A) A semiconductor substrate 11 made of silicon (Si) or the like is subjected to plasma CVD.
Method, a first SiO ₂ film 12 having a thickness of 1 μm is formed on the first Ti film 13, a first Ti film 13 having a thickness of 30 nm, a first Au film 14 having a thickness of 700 nm, and a first Au film 14 having a thickness of 50 nm by sputtering. One Pt film 15 is continuously laminated and patterned to form a metal wiring made of the first Ti / Au / Pt film 16. Instead of the first Au film 14, a low resistance material such as Al or a low resistance alloy material containing Al or Au can be used.

The above-mentioned first Pt film 15 is formed as an etching resistant metal. Also, the first
The Ti film 13 is inserted to improve the adhesion between the first SiO ₂ film 12 and the first Au film 14,
Instead of Ti, TiW, Mo or the like can be used.

Second Step (See FIG. 3B) For example, a second SiO ₂ film 17 having a thickness of 150 nm is formed by plasma CVD, and a 1.2 μm thick silicone film is formed thereon. A silylated polymethylsilsesquioxane (PMSS) resin film 18, which is one of the resins, is applied by spin coating and heated at 350 ° C. for 1 hour to cure. Next, for example, a third SiO ₂ film 19 having a thickness of 200 nm is formed by the ion beam assisted vapor deposition method.

The second SiO ₂ film 17 is inserted to improve the adhesion between the first Au film 14 and the PMSS resin film 18. In addition, the third SiO ₂ film 1
In No. 9, the resist film is ashed by oxygen plasma after the connection hole 20 is formed by using the photoresist film in the next third step, but at this time, the organic PMSS resin film 18 is deteriorated by oxygen plasma. It is formed to prevent it.

Third step (see FIG. 3C) CHF is performed by a RIE method using a resist mask.₃, C
₂F₆, SF₆, CF _FourUses mixed gas of system gas and He
And the third SiO₂The film 19 and the PMSS resin film 18,
2 SiO₂The film 17 is etched to open the connection hole 20.
To do. In this case, the first Pt film 15 is formed by the RIE.
Almost 100% over because it is hardly etched
-With the first Pt film 15 exposed even after etching
Etching stops.

Fourth step (see FIG. 3D) The semiconductor substrate 11 is heated to 260 ° C. in a reaction vessel under reduced pressure to obtain tungsten hexafluoride (WF ₆ ) and silane (Si).
Using a mixed gas of H ₄ ) and hydrogen (H ₂ ), the connection hole 20
A W film 21 is selectively deposited inside.

Fifth step (see FIG. 3E) A second Ti film 22 having a thickness of 30 nm, a second Au film 23 having a thickness of 700 nm, and a second Pt film 24 having a thickness of 50 nm are formed by a sputtering method. A second Ti / Au / Pt film 25 is formed by successively stacking vapor deposition and patterning.

By repeating the above process a desired number of times, it is possible to form a multi-layered wiring having three or more layers. Further, in the above-described embodiment, the PMSS resin film 1 is used as the insulating film.
Although the case of using 8 is exemplified, SO such as polysiloxane is used.
A G film can also be applied.

[0026]

As described above, according to the present invention,
The lower layer wiring metal is composed of two layers of metal film, and even if the upper layer metal film of the two layers is over-etched for a long time when the connection hole is opened by the RIE method, C and H remain on the bottom surface of the connection hole. , RI atom is small, and RI
Since the metal wiring is not sputtered when the connection hole is opened by the E method and adhered to the side wall of the connection hole, Pt having high dry etching resistance is used. Even if they are different on the substrate, they do not adversely affect the wiring metal surface.

Therefore, the connecting metal can be stably and reproducibly formed in the connection hole opened in the interlayer insulating film by the selective CVD method, which contributes to the improvement of the reliability of the semiconductor device having the multilayer wiring. However, it is big.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a graph showing the difference in dry etching resistance between Pt and Au.

3A to 3E are explanatory views of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor Substrate 2 First Metal Film 3 Second Metal Film 4 First Metal Wiring 5 First Insulating Film 6 Connection Hole 7 Connection Metal 8 Second Metal Wiring 11 Semiconductor Substrate 12 First SiO ₂ Film 13 First Ti Film 14 First Au Film 15 First Pt Film 16 First Ti / Au / Pt Film 17 Second SiO ₂ Film 18 PMSS Resin Film 19 Third SiO ₂ Film 20 Connection Hole 21 W film 22 Second Ti film 23 Second Au film 24 Second Pt film 25 Second Ti / Au / Pt film

Claims (4)

[Claims] 1. A step of forming a first metal film having low resistivity on a semiconductor substrate, a step of forming a second metal film having high etching resistance on the first metal film, A step of processing the first metal film and the second metal film to form a first metal wiring, and forming a first insulating film on the semiconductor substrate so as to cover the first metal wiring. A step of forming a connection hole for penetrating the first insulating film and connecting to the first metal wiring for metal wiring connection, and the first metal wiring exposed on the bottom surface of the connection hole And a step of selectively burying a connection metal in the second metal film included in the step of forming a second metal wiring on the first insulating film so as to cover the connection hole. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal film having a low resistivity contains at least Al or Au. 3. The second metal film having high etching resistance is P
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device comprises t. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film contains at least a polysiloxane film or a silicone resin.