JPH05307531A - Image processor - Google Patents

Abstract

PURPOSE:To improve a processing speed of the whole image processor by constituting the processor so that an access right arbitrating circuit ranks an access from each part of the device and receives successively from that of high priority, the access to an image memory can be processed without timewise waste and the time property is utilized effectively. CONSTITUTION:The image processor is provided with an image input/output part 20, an image memory part 40 consisting of one or more image memories 35, an image processing processor 31, a high speed bus and an access right arbitrating circuit 39, a host CPU 32, an image input/output bus 38, and a host CPU bus 37, and the access right arbitrating circuit 39 provides priority in the respective access signals RQ to the image processing processor 31, the host CPU 32, and the image memory 35 from the image input/output bus 38 copes with a transform a response, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which performs image processing on a video signal obtained by a video camera or the like to detect a vehicle, extract a license plate portion, and recognize a vehicle registration number.

[0002]

2. Description of the Related Art In recent years, image processing has been used in various industrial fields. For traffic control, for example, the image pickup means obtains a video signal of an area including a road, processes the signal, extracts the license plate portion of the vehicle, appropriately performs image processing to obtain the speed of the vehicle, or records it on the license plate. An image processing device for identifying the registered vehicle registration number is used.

In the image processing described above, for example, as shown in FIG. 4, the road is photographed using a video camera 10 installed approximately 6 m above the road side, and the image is processed by a host device (image processing device). By detecting the traveling vehicle CA and recognizing the registration number of the license plate, it has been successful in grasping traffic volume, calculating travel time, and identifying speeding vehicles.
Such an apparatus is disclosed in, for example, Japanese Patent Application No.
Proposed as No. 18992 (image type vehicle detector).

FIG. 6 is a block diagram showing an example of an image processing apparatus used for vehicle detection and image processing for extracting a license plate and recognizing a registration number. This image processing device (vehicle registration number reading device) is roughly composed of a camera unit 10, an image input / output unit (luminance data conversion unit) 20, a calculation control unit 30, and a night illumination device 50. The camera unit 10 is, for example, a CCD video camera, which captures an image of a detection area of a road and corresponds to the NT.
The SC system video signal is sent to the image input / output unit 20.

The image input / output section 20 is a section for converting a video signal into digital data, and a sync signal extraction circuit 21 for obtaining a horizontal sync signal and a vertical sync signal from the video signal, and a current scanning line based on these sync signals. The horizontal address counter 22 and the vertical address counter 23 for digitizing the scanning position to obtain the corresponding horizontal and vertical coordinates, the output of these and the coordinates sequentially specified by the microprocessor 41 (described later) are compared, and the moment when they coincide with each other. And a video A / D conversion circuit 25 for digitizing the luminance of the video signal at a corresponding moment according to the captured signal to obtain the luminance data and outputting the digitized luminance data. The input section has a video amplifier 27 that amplifies the transmitted video signal to an appropriate level, followed by an A / D
A clamp level fixing circuit 28 for normalizing the video signal to a constant amplitude prior to conversion is also provided.

The operation control unit 30 is a circuit for receiving the brightness data from the video A / D conversion circuit 25 and averaging a plurality of brightness data and calculating the correlation, and is required to operate at high speed. Therefore, the image processing processor (signal processor) 31 is used, and a storage unit (image memory 35) necessary for storing data is also provided.

Further, the arithmetic control unit 30 controls each of the above-mentioned units, receives data from the image processor 31, and further performs arithmetic processing on the data to detect the presence of a vehicle or calculate the speed of the vehicle. In addition, a control command is transmitted to the image processing processor 31, a portion corresponding to a license plate in the image is extracted, and a vehicle registration number written on the license plate is read (recognition of numbers),
The result is output to the subsequent device, and the host CPU3
2. It also has a ROM 33 storing a control program, a RAM 34 for storing data, and an I / O circuit 36 for output.

Reference numeral 37 is a host CPU bus through which the microprocessor 41 exchanges data, addresses, control commands and response signals with other parts, and 38 is an image memory 35.
Is an image bus for exchanging image data with the host CPU 32, the image processor 31, and the image input / output unit 20. The illustrated apparatus further includes a DC power supply 61 and a clock circuit 62.

FIG. 5 is a block diagram for explaining the above-mentioned apparatus for handling image data, mainly with an arithmetic control unit, together with each bus line (bus) required for data transfer and control. As shown in FIG. 5, the host CPU 3 that controls the whole
2 is an image memory unit 4 via the host CPU bus 37.
0, the image input / output unit 20 and the like to control the image input / output bus 38.
Image data is input / output between the image memory unit 40 and the image input / output unit 20 via the.

In addition to the image memory 35, the image memory unit 40 is equipped with the image processing processor 31 as described above, and shares the processing requiring particularly high speed under the control of the host CPU 32. Image memory 35
Write in. The host CPU 32 reads the processed result from the image memory 35 and uses it.

[0011]

In the conventional image processing apparatus described above, the transmission of the request signal (access signal) RQ to the image memory 35, that is, the access, is performed.
It is performed under the control of the host CPU 32. For example, when the host CPU 32 is performing other processing, the image memory 35 is not accessed at all. The image processor 31, which is the other processor, does not perform the process using the image memory during this time. Host CPU 32
It was configured to be accessible from other parts only under the control of. In other words, the host CPU does not access the image memory even in a cycle in which the image memory is not accessed, which naturally results in a time-consuming overall process. However, the demand for speeding up the image processing apparatus is increasing more and more.

The present invention has been made in view of such circumstances, and an opportunity to access the image memory by appropriately arbitrating (timing adjusting) the access to the image memory from each part of the image device. It is an object of the present invention to propose an image processing device capable of speeding up image processing by increasing the number of times and effectively utilizing time.

[0013]

In order to solve the above problems, the present invention provides an image processing apparatus, an image input / output unit (20),
An image memory unit (40), a host CPU (32), an image input / output bus (38), and a host CPU bus (37) are provided, and the host CPU (32) has an image input / output unit (20). ), An image memory unit (40) and the like via the predetermined bus (37, 38), the image input / output unit (20) converts a video signal into brightness data and also outputs predetermined image data. The image memory unit (40) is for converting into a video signal.
(35), an image processor (31), a high-speed bus (31A) and an access right arbitration circuit (39), the image memory (35) stores image data, the image processor (31) Performs input / output to / from the image memory (35) via the high-speed bus (31A), and the access right arbitration circuit (39) controls the image processor (31), the host CPU (32), and the image input / output bus (38). ) To the image memory (35) for each access signal (RQ
n) are passed in a priority order and the corresponding response signal (BSY
n) is transmitted.

[0014]

The access right arbitration circuit 39 prioritizes the accesses (request signals) from the respective parts of the device, accepts the access from the one with the highest priority, and immediately after this access is completed, if there is an access of the next order or later. Since the requests are prioritized and accepted, access to the image memory can be processed without waste, and time resources can be effectively used to improve the processing speed of the entire image processing apparatus.

[0015]

The present invention will be described in detail below with reference to the accompanying drawings. The image processing apparatus is generally a camera unit 1 like the vehicle image processing apparatus shown in FIG.
0, an image input / output unit 20, and a calculation control unit 30. A re-explanation of the already-explained parts will be omitted, and the image processing apparatus of the present invention will be described in detail below mainly on the arithmetic control unit 30.

FIG. 1 is a block diagram showing an embodiment of the image processing apparatus of the present invention. The image input / output unit 20 is A /
The image output bus 38 includes a D conversion unit and a D / A conversion unit.
The image data from B is subjected to a predetermined process and the image input bus 38
An inter-image calculation unit for returning to A is also provided.

The image memory unit 40 prioritizes access signals from n units of the image memories 35 _{1 to} 35n, the image processor 31, and the image memories 35 from each unit of the image processing apparatus and from the image processor 31. It is configured to include an access right arbitration circuit 39 for arbitrating and validating any one of them and sending a busy (BUSY) signal from the image memory 35 to the request source.

The access right arbitration circuit 39 is a gate circuit having multiple input / output terminals and is a PAL? (Programmable gate array?) Can be used to obtain a gate circuit having predetermined input / output characteristics.

Reference numeral 32 is a host CPU which controls each section. A bus 37 is common to the host CPU 32, the image input / output unit 20, and the image memory unit 30A.
It is for transmitting control commands from each unit to each unit and transferring predetermined data between each unit. Reference numeral 38 denotes an image bus (image bus), which includes an image input bus 38A and an image output bus 38.
B and. Image data is transferred at high speed between the image input / output unit 20 and each image memory 35 via the image bus 38. In addition, the image processor 31 and each image memory 3
Image data transfer between 5 is a specially provided high-speed bus 3
1A.

2 and 3 show an access right arbitration circuit 39.
4A and 4B are a block diagram and a timing chart, respectively, for explaining the operation of the embodiment. Access right arbitration circuit 39 of the embodiment
Are request signals (RQ1 to RQ) from the image input bus 38A, the image output bus 38B, the host CPU 32, and the image processor 31 (hereinafter also referred to as a device).
4) is input and the same image input bus 38A as output,
A response signal (BSY) indicating that the request to the image output bus 38B, the host CPU 32, and the image processor 31 has been accepted.
1 to BSY4) are connected.

Priority is set for the request signal from each device, and the request signal is transmitted to the image memory according to the request signal RQn from the device having the highest priority among the requested devices. And the response signal BSYn is returned. Therefore, even if each device outputs the request signal RQ to the image memory 35 at the same time, since the response signal is returned only to the upper device, the device receiving the response signal performs the processing and the other lower devices perform the processing. The device is allowed to wait for execution of the predetermined process until the upper device completes the predetermined process and stops transmitting the request signal RQ. The completion of the upper request signal is immediately detected by the access right arbitration circuit 39, and this time, the response signal BSY is sent to the lower device. In this way, access requests to the image memory 35 are arbitrated,
Only the processing corresponding to one device is always performed while taking priority into consideration.

The access right arbitration circuit 39 according to the embodiment.
Has a priority order of the image input bus 38A, the image output bus 38B, the host CPU 32, and the image processing processor 31, and gives the highest priority to image capture, and requests from other host CPUs 32 The image processing corresponding to the request from the image processor 31 is performed only between the image capturing. On the other hand, this means that the lower processing is effectively performed when the processing with the higher priority is not performed. As a result, a series of image processing operations are performed at high speed as a whole.

FIG. 3 shows an access right arbitration circuit 39 of the embodiment.
Is a timing chart for explaining the action of
_{In 1} , the four devices (the image input bus 38A, the image output bus 38B, the host CPU 32, and the image processing processor 31) simultaneously generate requests for the image memory, and the access right arbitration circuit 39 receives four request signals (RQ1 to RQ4). ) Shows the case of input.

The access right arbitration circuit 39 uses the image input bus 38 having the highest priority among the request signals input at t _1.
In response to the request signal RQ1 from A, first the image input bus 3
The response signal BSY1 is output at t ₂ for 8A. The image input bus 38A that has completed the processing sends the request signal BSY1 to t.
_{When the processing is} terminated at ₃ , the access right arbitration circuit 39 immediately outputs the response signal BSY2 to the image output bus 38B which has the next highest priority and outputs the request signal RQ2 from t _1.
Is sent. Similarly, in response to the request signal RQ4 of the lowest-order image processor 31, the response signal BSY starts only at time t ₅ when all request signals from others have stopped.
4 is issued.

In the above embodiments, the image input bus 38A, the image output bus 38B, the host CPU 32, and the image processor 31 are used as devices for accessing the image memory.
Although the priority order is set in this order, the types and number of devices and the priority order are not limited to this, and the device and the priority order are set according to the purpose of the image processing apparatus. In addition, the devices described in the embodiments have a high versatility using a common bus, and if necessary, an image memory unit similar to the one described above that can be accessed by the host CPU or an image memory unit having no image processor is required. It is possible to add a predetermined number to the same bus.

[0026]

As described in detail above, the image processing apparatus of the present invention includes an image input / output unit, an image memory unit including one or more image memories, an image processing processor, a high-speed bus, and an access right arbitration circuit, and a host. The access right arbitration circuit includes a CPU, an image input / output bus, and a host CPU bus, and the access right arbitration circuit transfers the respective access signals to the image memory from the image processor, the host CPU, and the image input / output bus with priorities. The access right arbitration circuit 39 prioritizes the access from each part of the device, accepts the access from the one with the highest priority, and immediately after the access is completed, the access right arbitration circuit 39 If there is access, it will be prioritized and accepted, so that access to the image memory can be processed without waste, and thus time resources can be effectively used. It is possible to improve the processing speed of the entire image processing apparatus.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus of the present invention.

FIG. 2 is a block diagram showing an embodiment of an access right arbitration circuit according to the present invention.

FIG. 3 is a timing chart illustrating an operation of an access right arbitration circuit.

FIG. 4 is an external perspective view showing an example of an image processing apparatus according to the present invention.

FIG. 5 is a block diagram of an image processing apparatus according to the present invention.

FIG. 6 is a block diagram of an example of an image processing apparatus.

[Explanation of symbols]

 20 ... Image input / output unit, 31 ... Image processing processor, 31A ... High speed bus, 32 ... Host CPU, 35 ... Image memory, 37 ... Host CPU bus, 38 ... Image input / output bus, 39 ... Access right arbitration circuit, 40 ... Image memory unit, RQn ... Access signal (request signal), BSYn ... Response signal.

Claims (1)

[Claims] 1. An image processing apparatus for obtaining brightness data corresponding to a plurality of measurement points from a video signal and processing the brightness data, the image input / output unit (20), an image memory unit (40), It has a host CPU (32), an image input / output bus (38), and a host CPU bus (37). The host CPU (32) includes an image input / output unit (20) and an image memory unit (40). The control is performed via the predetermined bus (37, 38), the image input / output unit (20) converts a video signal into luminance data,
The image memory unit (40) converts predetermined image data into a video signal. The image memory unit (40) includes one or more image memories (35), an image processor (31), a high-speed bus (31A), an access right arbitration circuit (39). ) And the image memory (35) stores image data, and the image processor (31) is a high-speed bus (3
Input / output to / from the image memory (35) via the 1A), and the access right arbitration circuit (39)
1) Pass the respective access signals (RQ n) from the host CPU (32) and the image input / output bus (38) to the image memory (35) in priority order and send the corresponding response signal (BSYn). An image processing device that does.