JPH05304258A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To fabricate a semiconductor device in which 1/f noise can be suppressed even if transistors at I/O stage are made fine by hybridizing CMOSFETs and junction FETs. CONSTITUTION:The semiconductor device comprises a semiconductor substrate 15 having a junction FET region 17, and second MOSFET regions 16a, 16b, a well 18 formed in the second MOSFET region 16a, and a channel region 23 formed in the junction FET region 17. The semiconductor device further comprises a gate oxide 24 deposited on the first MOSFET region 16b and the well 18, and gate electrodes 25a, 25b provided on the gate oxide 24. Furthermore, a first source.drain region 32 and the gate of the junction FET are formed in the first MOSFET region 16b and the channel region 23 while a second source.drain region 36 and a third source.drain region 37 are formed in the well 18 and the channel region 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of suppressing 1 / f noise and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view showing a conventional semiconductor device. N-type impurities are ion-implanted into the P-type silicon substrate 1 to form an N-type well 2 for PMOS. Thereafter, the P-type silicon substrate 1 is provided with first to third element isolation regions 3a to 3c by the LOCOS method. Next, a gate oxide film 4 is provided on the P-type silicon substrate 1 by, for example, thermal oxidation, and gate electrodes 5 and 6 for PMOS and NMOS are formed on the gate oxide film 4. Then, a first resist film (not shown) is provided on the first and second element isolation regions 3a and 3b, the PMOS gate electrode 5 and the P-type silicon substrate 1. By ion implantation using this resist film and the gate electrode 6 of the NMOS as a mask, the diffusion layer 7 in the LDD region of the NMOS is formed on the P-type silicon substrate 1. Next, the first resist film is removed,
Sidewalls 8 are formed on both side surfaces of the gate electrodes 5 and 6 of the PMOS and NMOS, respectively. Next, As is ion-implanted into the P-type silicon substrate 1,
Diffusion layers 9 in the source / drain regions of the OS are formed.
After that, P-type impurities are ion-implanted on the N-type well for the PMOS in the P-type silicon substrate 1,
The diffusion layer 10 in the source / drain region of the PMOS is formed.

[0003]

By the way, the integrated circuit used for communication or voice signal is constituted by the CMOS type FET manufactured as described above.

Recently, C which is used for this audio signal is used.
In the MOS type FET, it is required to lower the power supply voltage. If the power supply voltage is lowered, S (Sign
al) becomes smaller. M used for the audio signal
In case of OS type FET, high S / N (Noise) when converting analog signal which is audio signal of input stage into digital signal
A ratio is needed. Similarly, a high S / N ratio is required when converting a digital signal in the output stage into an analog signal. In order to maintain a high S / N ratio even if S is reduced, N must be reduced as S is reduced. Therefore, it is required to reduce 1 / f noise in the low frequency region.

The 1 / f noise is proportional to 1 / LW and the surface level density, where L is the channel length and W is the channel width. Therefore, in the conventional analog circuit, 1 / f noise is suppressed by increasing the size of the transistor in the input / output stage, that is, by increasing the L and W of the MOS transistor. However, if the size of the MOS transistor is increased, it is against the miniaturization of the transistor, and with the miniaturization of the integrated circuit, there is a limit in increasing the size of the transistor in the input / output stage.

The present invention has been made in consideration of the above circumstances, and an object thereof is to mix a MOS type FET and a junction FET so that even if a transistor in an input / output stage is miniaturized, It is an object of the present invention to provide a semiconductor device capable of reducing f noise and a manufacturing method thereof.

[0007]

In order to solve the above problems, the present invention provides a junction FET region and a first FET,
A semiconductor substrate having a second MOS type FET region, a well formed in the second MOS type FET region, the first MOS type FET region and the junction F.
First and second channel regions formed in each ET region, first and second gate oxide films provided on the first MOS type FET region and the well, and the first and second channel regions. First and second gate electrodes provided on each of the two gate oxide films, first source / drain regions formed in each of the first MOS type FET region and the second channel region, and It is characterized by comprising a gate of a junction FET and a second source / drain region and a third source / drain region formed in the well and the second channel region, respectively.

The semiconductor substrate has a junction FE.
Having a T region and first and second MOS type FET regions,
Forming a well in the second MOS type FET region and introducing a first impurity,
Forming a first channel region in the OS-type FET region and forming a second channel region in the junction FET region, and forming first and second channel regions on the first channel region and the well, respectively. Providing a gate oxide film, providing first and second gate electrodes on the first and second gate oxide films, respectively, and introducing a second impurity to form the first MOS Forming a first source / drain region in the type FET region and forming a gate of the junction FET in the second channel region; and introducing a first impurity into the well. Forming a second source / drain region and forming a third source / drain region in the second channel region. It is characterized in.

The semiconductor substrate has a junction FE.
Having a T region and first and second MOS type FET regions,
Forming a well in the second MOS type FET region; forming a channel stopper region in the semiconductor substrate by introducing a first impurity; and forming a channel region in the junction FET region. A step of providing first and second element isolation regions on each of the channel region and the channel stopper region, a step of removing a part of the first element isolation region, and the first MOS-type FET Providing first and second gate oxide films on the region and the well; providing first and second gate electrodes on the first and second gate oxide films, respectively; The first MOS type FET by introducing the impurities of
Forming a first source / drain region in the region, and forming a junction FE in the second channel region.
By forming a gate of T and introducing a first impurity, a second source / drain region is formed in the well and a third source / drain region is formed in the first channel region. And a step of forming a drain region.

Further, the semiconductor substrate and the first MOS
The type FET region, the first and second channel regions and the second and third source / drain regions are of the first conductivity type or the second conductivity type.

Further, the well, the first source / drain region, and the gate of the junction FET are of the second conductivity type or the first conductivity type. Further, the first impurity is characterized by having a first conductivity type or a second conductivity type. Further, the second impurity is characterized by having a second conductivity type or a first conductivity type. In addition, the channel region has a first
It is characterized by being of a conductive type or a second conductive type.

[0012]

According to the present invention, the junction FET and the MOS type FET are provided on the same semiconductor substrate. For this reason, junction FETs are used where analog / digital mixed mounting requires low noise at the analog input stage, and MOS FETs are used where high-speed digital processing is required.
Can be used. As a result, the transistor whose 1 / f noise needs to be reduced, that is, the junction F
Even if ET is miniaturized, 1 / f noise can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 1
As shown in (b), the P-type silicon substrate 15 has a CMO
S-type FET region 16 and junction FET region 1
7 are formed. A first resist film (not shown) is provided on the surface of the P-type silicon substrate 15. N-type impurities are ion-implanted using this resist film as a mask, whereby the P-type silicon substrate 1 in each of the CMOS FET region 16 and the junction FET region 17 is implanted.
N-type well 18 for PMOS and N-type well 19 for junction FET are formed in 5.

After that, as shown in FIG. 2A, the first resist film is removed, and the P-type silicon substrate 15 is formed with the first to sixth element isolation regions 20a by the LOCOS method.
~ 20f are provided. A PMOS region 16a is formed between the first and second element isolation regions 20a and 20b,
N between the second and third element isolation regions 20b and 20c
It is used as a MOS region 16b.

Next, as shown in FIG. 2B, the P-type silicon substrate 15 and the first, second, fourth, and fifth element isolation regions 20a, 20b, 20d, and 20e are overlaid with a second layer. Two
The resist film 21 is provided. Using the second resist film 21 and the third and sixth element isolation regions 20c and 20f as a mask, P, which is a P-type impurity, is ion-implanted at a dose of 1 × 10 ¹² m ⁻² . As a result, an NMOS channel region 22 is formed on the P-type silicon substrate 15 in the NMOS region 16b, and a junction FET channel region 23 is formed on the P-type silicon substrate 15 in the junction FET region 17.

After that, as shown in FIG. 3A, the second resist film 21 is removed, and the gate oxide film 24 is formed on the surface of the P-type silicon substrate 15 by, for example, thermal oxidation.
Is provided. A polycrystalline silicon layer 25 is deposited on the gate oxide film 24 and the first to sixth element isolation regions 20a to 20f, and a third resist film (not shown) is formed on the polycrystalline silicon layer 25. It is provided. The polycrystalline silicon layer 25 is etched using this resist film as a mask, and the gate electrodes 2 of the PMOS and NMOS are respectively formed.
5a and 25b are formed.

Next, a fourth resist film (not shown) is provided on the PMOS region 16a and the junction FET region 17. By ion implantation using this resist film and the gate electrode 25b of the NMOS as a mask,
A diffusion layer 26 in the LDD region of the NMOS is formed. After that, the fourth resist film is removed, and the PMOS gate electrode 25a, the NMOS gate electrode 25b, the gate oxide film 24, and the first to sixth element isolation regions 20a to 2 are formed.
A SiO ₂ layer 27 is deposited on 0f. This SiO
_{The second} layer 27 is anisotropically etched by RIE, so that sidewalls 28 are formed on both side surfaces of the gate electrodes 25a and 25b of the PMOS and NMOS, respectively.

After that, the first to fifth element isolation regions 20 are formed.
A fifth resist film 29 is provided on the gate electrodes a to 20e, the PMOS and NMOS gate electrodes 25a and 25b, the sidewalls 28, and the gate oxide film 24, respectively. Junction FET using this resist film 29 as a mask
1 × 1 of B, which is a P-type impurity, in the channel region 23 of
Ion implantation is performed with a dose amount of 0 ¹² to 10 ¹³ cm ^-2 . As a result, the channel region 23 of the junction FET is increased to a predetermined B concentration.

Next, as shown in FIG.
The resist film 29 is removed, and the first, second, fifth, and sixth resist films 29 are removed.
Element isolation regions 20a, 20b, 20e, 20f, PM
A sixth resist film 31 is provided on the gate electrode 25a of the OS and the gate oxide film 24. The resist film 31, the NMOS gate electrode 25b, the sidewall 2
As an N-type impurity is ion-implanted using the 8 and the third and fourth element isolation regions 20c and 20d as a mask,
The diffusion layer 32 in the source / drain region of the NMOS, the gate 33 of the junction FET, and the junction FE
A T well contact 34 is formed.

Thereafter, as shown in FIG. 1A, the sixth resist film 31 is removed, and the third and fourth element isolation regions 20c and 20d, the NMOS gate electrode 25b, the sidewall 28 and A seventh resist film (not shown) is provided on the gate oxide film 24. This resist film,
The PMOS gate electrode 25a, the sidewall 28, and the first, second, fifth, and sixth element isolation regions 20a, 20.
P-type impurities are ion-implanted using b, 20e and 20f as masks to form a diffusion layer 36 in the source / drain region of the PMOS and a diffusion layer 37 in the source / drain region of the junction FET. Next, the seventh resist film is removed.

According to the above manufacturing method, the N-type well 19 for the junction FET is formed by ion implantation when forming the N-type well 18 for the PMOS. Further, the junction FET is formed by ion implantation of P-type impurities when forming the channel region 22 of the NMOS.
To form the channel region 23. Further, the gate 33 of the junction FET and the well contact 34 of the junction FET are formed by ion implantation of N-type impurities when forming the diffusion layer 32 of the source / drain region of the NMOS. Further, the diffusion layer 37 in the source / drain region of the junction FET is formed by ion implantation of P-type impurities when the diffusion layer 36 in the source / drain region of the PMOS is formed. Therefore, the CMOS type FET and the junction FET are formed on the same silicon substrate by the conventional CMOS type FET manufacturing process.
Can be formed. In addition, the conventional CMOS FE
Since the manufacturing process of T is used, the manufacturing cost can be kept low.

FIG. 4 is a diagram showing the relationship between the scaling of the design rule and the 1 / f noise voltage in each of the semiconductor device according to the first embodiment of the present invention and the conventional semiconductor device. 38 scales each ×
1 when using a MOS type FET which is a conventional semiconductor device manufactured as 1, × 0.8, × 0.7, × 0.6
/ F is a straight line that plots the results of measuring the noise voltage and shows the tendency. 39 is a point showing the result of measuring the 1 / f noise voltage when using the junction FET in the semiconductor device of the present invention manufactured with the scaling of × 0.7. According to these results, the noise voltage of the junction FET can be reduced by one order or more than that of the MOS FET.

According to the above embodiment, the CMOS type FET and the junction FET are formed on the same P type silicon substrate 15. Therefore, for example, in an analog / digital mixed circuit used for audio signals, a junction FET is used where it is necessary to reduce noise in the analog input stage, and a MOS type is used where high-speed digital processing is required. You can use FET. As a result, the 1 / f noise can be reduced even if the input / output stage transistor, that is, the junction FET is miniaturized.

FIGS. 1, 2 and 3B are sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, in which the same parts as those in the first embodiment are designated by the same reference numerals. Only different parts will be described.

The dose of ion implantation for forming the NMOS channel region 22 shown in FIG. 2B is larger than that in the first embodiment. This is for example CM
This is a measure for increasing the threshold voltage because the threshold voltage is lowered as the OS-type FET is miniaturized, especially as the gate oxide film is made thinner. As a result, the concentration in the channel region 23 of the junction FET also increases, and the channel region 23 of the junction FET is formed to have a predetermined concentration.

After this, as shown in FIG. 3B, the second resist film 21 is removed, and a gate oxide film 24 is provided on the P-type silicon substrate 15. Gate electrodes 25a and 25b for PMOS and NMOS are formed on the gate oxide film 24. Next, NMOS L
The diffusion layer 26 in the DD region is formed. After this, PMOS
Sidewalls 28 are formed on both side surfaces of the gate electrodes 25a and 25b of the NMOS and the NMOS, respectively. Then N
Diffusion layer 32 in source / drain region of MOS, gate 33 of junction FET and junction FET
Well contact 34 is formed.

In the second embodiment, the same effect as that of the first embodiment can be obtained, and the dose of ion implantation for forming the channel region 22 of the NMOS is the same as that of the first embodiment. Since the number is larger than that, it is not necessary to perform ion implantation for increasing the channel region of the junction FET to a predetermined concentration.

1, FIG. 2, FIG. 3 (b) and FIG. 5 are sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention. The same reference numerals are given and only different portions will be described.

As shown in FIG. 2B, in the P-type silicon substrate 15, an NMOS channel region 22 is formed in the PMOS region 16b and a junction FET channel region 23 is formed in the junction FET region 17. ..

Thereafter, as shown in FIG. 5A, a fifth resist film 29 is provided on the first to fifth element isolation regions 20a to 20e and the P-type silicon substrate 15. Using the fifth resist film 29 and the sixth element isolation region 20f as a mask, the P-type impurity B of 1 × 10 ¹² to the channel region 23 of the junction FET.
Ion implantation is performed at a dose of 10 ¹³ cm ^-2 . As a result, the channel region 23 of the junction FET is increased to a predetermined B concentration.

Next, as shown in FIG.
The resist film 29 is removed, and the P-type silicon substrate 1 is removed.
A gate oxide film 24 is provided on the gate electrode 5. The gate oxide film 24 and the first to sixth element isolation regions 20a ...
A polycrystalline silicon layer 25 is deposited on 20f, and a fourth resist film (not shown) is provided on the polycrystalline silicon layer 25. Using the resist film as a mask, the polycrystalline silicon layer 25 is etched to form gate electrodes 25a and 25b for the PMOS and NMOS, respectively. Next, a fourth resist film (not shown) is provided in the PMOS region 16a and the junction FET region 17, and the resist film and the gate electrode 25b of the NMOS are provided.
Is used as a mask to form a diffusion layer 26 in the LDD region of the NMOS.

After this, as shown in FIG. 3B, the fourth resist film is removed, and sidewalls 28 are formed on both side surfaces of the gate electrodes 25a and 25b of the PMOS and NMOS, respectively. Also in the third embodiment, the same effect as that of the first embodiment can be obtained.

FIGS. 6, 7 and 8 show a fourth embodiment of the present invention.
FIG. 11 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the present invention, in which the same parts as those in the first embodiment are designated by the same reference numerals and only different parts will be described.

As shown in FIG. 6A, a CMOS type FET region 16 and a junction FET region 17 are formed on the P type silicon substrate 15. A first resist film (not shown) is provided on the surface of the P-type silicon substrate 15. N-type impurities are ion-implanted into the P-type silicon substrate 15 by using this resist film as a mask to form an N-type well 18 for PMOS and an N-type well 19 for junction FET.

After that, the first resist film is removed, and a pad oxide film (not shown) is deposited on the P-type silicon substrate 15. A nitride film (not shown) is deposited on the pad oxide film, and a second film (not shown) is formed on the nitride film.
Resist film is provided. The pad oxide film and the nitride film are etched using this resist film as a mask. Next, B, which is a P-type impurity, is ion-implanted using the second resist film as a mask, and the channel stopper region 51 and the channel region 2 of the junction FET are formed.
3 is formed.

Next, as shown in FIG. 6B, the second
The resist film is removed, and the P-type silicon substrate 15 is provided with first to fourth and seventh element isolation regions 20a to 20d and 20g by the LOCOS method. Then, the nitride film and the pad oxide film are removed.

Thereafter, as shown in FIG. 7A, the first to fourth and seventh element isolation regions 20a to 20d, 20 are formed.
A third resist film (not shown) is provided on the g and P-type silicon substrate 15. Using the resist film as a mask, the seventh element isolation region 20g is etched to form the eighth and ninth element isolation regions 20h and 20i.
Next, the PMOS region 16a and the junction FET
A fourth resist film (not shown) is provided in each of the regions 17. Ion implantation is performed using this resist film as a mask to form an NMOS channel region 22.

Next, as shown in FIG. 7B, the fourth
The resist film is removed, and a gate oxide film 24 is provided on the P-type silicon substrate 15 by, for example, thermal oxidation. A PMOS and an NM are formed on the gate oxide film 24.
Gate electrodes 25a and 25b for each OS are formed. Next, on the P-type silicon substrate 15, an NMOS L is formed.
The diffusion layer 26 in the DD region is formed. After this, the PM
Gate electrodes 25a and 25 for the OS and NMOS, respectively
Side walls 28 made of a SiO ₂ layer are provided on both sides of b.
Is formed. Next, the first, second, eighth and ninth element isolation regions 20a, 20b, 20h, 20i and the PMOS
A sixth resist film 31 is provided on the gate electrode 25 a and the gate oxide film 24. This resist film 3
1, NMOS gate electrode 25b, sidewall 28
As is ion-implanted by using the third and fourth element isolation regions 20c and 20d as a mask to form the diffusion layer 32 in the source / drain region of the NMOS, the gate 33 of the junction FET, and the well contact 34 of the junction FET.

Thereafter, as shown in FIG. 8, the sixth resist film 31 is removed, and the P-type silicon substrate 15 is provided with a diffusion layer 36 of a source / drain region of a PMOS and a source / drain region of a junction FET. Diffusion layer 37 is formed. Also in the fourth embodiment, the same effect as in the first embodiment can be obtained.

[0041]

As described above, according to the present invention,
Junction FET and MOS on the same semiconductor substrate
A type FET is provided. Therefore, 1 / f noise can be reduced even if the input / output stage transistor is miniaturized.

[Brief description of drawings]

FIG. 1A shows a method of manufacturing a semiconductor device according to first, second and third embodiments of the present invention,
FIG. 1B is a cross-sectional view showing a step of forming a diffusion layer in a source / drain region of a PMOS and a diffusion layer in a source / drain region of a junction FET, and FIG. 1B shows the first, second and third aspects of the present invention. FIG. 10 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment, showing a step of forming an N-type well for a PMOS and an N-type well for a junction FET.

FIG. 2A shows a method of manufacturing a semiconductor device according to first, second and third embodiments of the present invention,
FIG. 2B is a cross-sectional view showing a step of providing first to sixth element isolation regions, and FIG. 2B shows a method of manufacturing a semiconductor device according to the first, second and third embodiments of the present invention. Yes,
FIG. 6 is a cross-sectional view showing a step of forming an NMOS channel region and a junction FET channel region.

FIG. 3A is a sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, showing a step of ion-implanting B into a channel region of a junction FET, FIG. 3 (b) shows a method of manufacturing a semiconductor device according to the first, second and third embodiments of the present invention, which is a diffusion layer of an NMOS source / drain region,
Junction FET gate and junction F
Sectional drawing which shows the process of forming the well contact of ET.

FIG. 4 is a diagram showing a relationship between scaling of a design rule and 1 / f noise voltage in each of the semiconductor device according to the first embodiment of the present invention and the conventional semiconductor device.

FIG. 5A is a sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention, showing a step of ion-implanting B into a channel region of a junction FET; FIG. 5B shows a semiconductor device manufacturing method according to the third embodiment of the present invention.
Gate electrode and NMO of OS and NMOS respectively
FIG. 6 is a cross-sectional view showing a step of forming a diffusion layer in the LDD region of S.

FIG. 6 (a) shows a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention, in which an N type well for PMOS, an N type well for junction FET and a channel region of the junction FET are formed. FIG. 6B is a cross-sectional view showing the step of forming, and FIG. 6B shows a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, in which the first to fourth and seventh element isolation regions are Sectional drawing which shows the process to provide.

7A is a cross-sectional view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, showing a step of forming an NMOS channel region. FIG.
(B) shows a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, which shows a step of forming a diffusion layer of an NMOS source / drain region, a gate of a junction FET and a well contact of a junction FET. Sectional drawing to show.

FIG. 8 shows a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention, showing a step of forming a diffusion layer in a source / drain region of a PMOS and a diffusion layer in a source / drain region of a junction FET. Sectional view.

FIG. 9 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

15 ... P-type silicon substrate, 16 ... CMOS type FET region, 16
a ... PMOS region, 16b ... NMOS region, 17 ... junction FET region, 18 ... N-type well for PMOS,
19 ... N-type well for junction FET, 20a ...
First element isolation region, 20b Second element isolation region, 20c
… Third element isolation region, 20d… Fourth element isolation region, 20d
e ... Fifth element isolation region, 20f ... Sixth element isolation region,
20g ... 7th element isolation region, 20h ... 8th element isolation region, 20i ... 9th element isolation region, 21 ... Second resist film, 22 ... NMOS channel region, 23 ... Junction FET channel region, 24 ... Gate oxide film, 25 ... Polycrystalline silicon layer, 25a ... PMOS gate electrode, 25b ... NM
OS gate electrode, 26 ... NMOS LDD region diffusion layer, 27 ... SiO ₂ layer, 28 ... Side wall, 29 ... Fifth resist film, 31 ... Sixth resist film, 32 ... NMOS source / drain region Diffusion layer, 33 ... Junction FE
T gate, 34 ... Well contact, 36 ... Diffusion layer of PMOS source / drain region, 37 ... Junction FE
Diffusion layer of source / drain region of T, 38 ... Relation between design rule scaling and 1 / f noise voltage in conventional semiconductor device, 39 ... Design rule scaling and 1 / f noise voltage in semiconductor device of the present invention , 41 ... Third resist film, 51 ... Channel stopper region.

Claims (8)

[Claims] 1. A junction FET region and a first,
A semiconductor substrate having a second MOS type FET region, a well formed in the second MOS type FET region, and first and first wells formed in the first MOS type FET region and the junction FET region, respectively. A second channel region, first and second gate oxide films provided on the first MOS type FET region and the well, and first channel oxide films provided on the first and second gate oxide films, respectively. First and second gate electrodes, first source / drain regions and gates of the junction FET formed in the first MOS type FET region and the second channel region, respectively, the well and the second A second source / drain region and a third source / drain region formed in each of the two channel regions. A semiconductor device characterized by. 2. A semiconductor substrate having a junction FET region and first and second MOS type FET regions, a step of forming a well in the second MOS type FET region, and introducing a first impurity. As a result, the first MOS
Forming a first channel region in the type FET region and forming a second channel region in the junction FET region, and first and second gates on the first channel region and the well, respectively. Providing an oxide film, and forming a first layer on each of the first and second gate oxide layers.
And a step of providing a second gate electrode, and by introducing a second impurity, the first MOS
Forming a first source / drain region in the type FET region and forming a gate of the junction FET in the second channel region; and introducing a first impurity into the well. Forming a second source / drain region, and forming a third source / drain region in the second channel region, a method of manufacturing a semiconductor device. 3. A semiconductor substrate having a junction FET region and first and second MOS type FET regions, a step of forming a well in the second MOS type FET region, and introducing a first impurity. Thereby forming a channel stopper region in the semiconductor substrate and forming a channel region in the junction FET region, and forming a first and second element isolation region on each of the channel region and the channel stopper region. A step of providing, a step of removing a part of the first element isolation region, a step of providing first and second gate oxide films on the first MOS FET region and the well, A first on each of the first and second gate oxides
And a step of providing a second gate electrode, and by introducing a second impurity, the first MOS
Forming a first source / drain region in the type FET region and forming a gate of the junction FET in the second channel region; and introducing a first impurity into the well. Forming a second source / drain region, and forming a third source / drain region in the first channel region, a method of manufacturing a semiconductor device. 4. The semiconductor substrate, the first MOS type F
4. The ET region, the first and second channel regions, and the second and third source / drain regions are of the first conductivity type or the second conductivity type, respectively. Semiconductor device and its manufacturing method. 5. The semiconductor according to claim 1, 2 or 3, wherein the well, the first source / drain region and the gate of the junction FET are of the second conductivity type or the first conductivity type. Device and manufacturing method thereof. 6. The method of manufacturing a semiconductor device according to claim 2, wherein the first impurity has a first conductivity type or a second conductivity type. 7. The method of manufacturing a semiconductor device according to claim 2, wherein the second impurity has a second conductivity type or a first conductivity type. 8. The method of manufacturing a semiconductor device according to claim 3, wherein the channel region is of a first conductivity type or a second conductivity type.