JPH0530192Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a power supply device for a microprocessor having a standby function.

[Background technology] Conventional power supply devices for microprocessors reset the microprocessor using a time constant using a resistor and a capacitor, so there is no problem with normal on/off operations, but the capacitor resets during a momentary power outage. Based on the inability to reset due to residual charge of
There were cases where the CPU ran out of control.

[Purpose of the invention] The present invention has been proposed in view of the above-mentioned points, and is capable of reliably resetting the microprocessor (CPU) without running out of control even if the power supply of the microprocessor (CPU) is momentarily interrupted. The present invention provides a power supply device for a microprocessor whose purpose is to enable the CPU to enter STOP mode without malfunctioning in the event of a power outage.

[Disclosure of the invention] Hereinafter, embodiments of the invention will be described with reference to the drawings.
In FIG. 1, 1 is a microprocessor (CPU) with a standby function, and has terminals as shown below. The reset terminal resets the CPU by inputting L level after power is supplied.
Initialize 1 (active low). The power input terminal V _CC is a terminal to which the power of the CPU 1 is input.
The control input terminal V _DD is a so-called standby function control input terminal, and this input terminal V _DD
When set to L level, the clock pulse oscillator inside CPU1 stops, and the reset terminal
RESET is internally pulled down to the ground line. Also, when the control input terminal V _DD is set to H level, the oscillator operates and the reset terminal
RESET is internally pulled up to V _CC .

By the way, to explain the stop mode of the CPU 1, when the CPU 1 enters the stop mode, the oscillator stops and only the contents of the RAM are held, so power consumption is minimized. To set the stop mode, proceed as follows. First, set the reset terminal to L level to protect the RAM, and then set the control input terminal V _DD to L level.
level and stop the oscillator. Also, to cancel stop mode, do the following. Add +2.5 to 6.0V to the power input terminal V _CC and reset the reset terminal.
When the control input terminal V _DD is set to H level while RESET remains at L level, the oscillator starts oscillating. Then, when the reset terminal is set to H level after the oscillation of the oscillator becomes stable, the program starts from address 0.

Now, in FIG. 1, 2 is a memory backup capacitor inside the CPU 1, which is connected to the power input terminal V _CC . The supply voltage V ₀ is supplied to the power supply input terminal V _CC via the diode D ₁ . 3
is a reset circuit, consisting of diodes D ₂ , D ₃ , Zener diode ZD, resistors R ₁ to _{R 3} , and transistors.
It consists of Tr ₁ , Tr ₂ and capacitor C.
Here, the values of the resistors R ₂ and R ₃ and the Zener diode ZD are determined so that the voltage Vb at point b when energized is 1 to 2 V.

Next, the operation will be explained. Here the supply voltage V ₀ is
Set to 5.5V. Therefore, when the current is on, V _CC is approximately
5V, _VDD is 4.5V, and Vb is 1 to 2V. Therefore, transistor Tr ₁ is turned on. Transistor Tr ₁
When turned on, the base of transistor _Tr2 becomes zero and the reset terminal becomes 5V. Next, explaining what happens after time Ta after the power outage shown in FIG. 2, the supply voltage V ₀ decreases, so the voltage Vb at point b also decreases, and the transistor Tr ₁ turns off. Since the voltage of the control input terminal V _DD is still more than 2V,
A voltage is applied from the control input terminal V _DD to the base of the transistor Tr ₂ through the resistor R ₁ and the transistor Tr ₂ is turned on. As a result, capacitor C
The charge is discharged, and the reset terminal becomes L level. In other words, the control input terminal V _DD
is at H level, and the reset terminal is at L level. Next, the operation after time Tb after the power outage will be explained. Since the voltage of the supply voltage V ₀ further decreases, the control input terminal V _DD becomes L level. At this point, the reset terminal is at L level and the control input terminal V _DD is also at L level, so
CPU1 goes into stop mode.

Next, a momentary power outage will be explained. Time Ta
When the power is restored before the power is turned off, the reset terminal has not reached the L level, so it has nothing to do with the power outage.
CPU1 continues executing the program. When returning from time Ta to Tb, the reset terminal
RESET is after reaching L level, so CPU1
is initialized and starts executing the program from the beginning. Also, there is no stopping of the oscillator. When the power is restored after time Tb, the CPU 1 is in the stop mode, so when the power is restored, the power input terminal V _CC goes to about 5V, the control input terminal V _DD goes to H level, and the oscillator starts oscillating. Furthermore, transistor Tr ₁ is on, transistor Tr ₂
is turned off, but after the oscillator oscillation stabilizes due to the charging time of capacitor C, the reset terminal is turned off.
RESET becomes H level. In this way, even in the event of a momentary power outage, the CPU 1 can be reliably reset without going out of control, and in the event of a power outage, it will go into stop mode without malfunctioning, and after the power is restored, the program will start from address 0.
The CPU will not run out of control.

[Effects of the invention] As mentioned above, the present invention has a power input terminal, a reset terminal that initializes the internals when set to L level, and an internal oscillator that stops when set to L level, and the reset terminal is grounded internally. It has a control input terminal that is pulled down to the power supply line, and when set to H level, the oscillator operates and the reset terminal is internally pulled up to the power supply voltage. A CPU that goes out of control unless the reset terminal is set to L level before the other terminals, and the reset terminal is set to H level after the control input terminal is set to H level when the power is turned on.
It is connected to the power input terminal of the CPU and is equipped with a capacitor for memory backup inside the CPU.
The reset terminal is set to the L level before the control input terminal in the process where the power is cut off and the supply voltage decreases, and the control is set to the L level before the reset terminal is set in the process when the power is restored and the supply voltage increases. Since it forms a reset circuit that sets the input terminal to H level,
Even during a power outage, the reset terminal goes to L level before the control input terminal, and even when the power is restored, the control input terminal goes to H level before the reset terminal, so the CPU goes into so-called stop mode during a power outage. Furthermore, after the power is restored, the program that was released from stop mode will be executed from the beginning, so the CPU will not run out of control. Therefore, even in the case of a momentary power outage, the power-off time will be long after the power is restored, as described above. Bye bye
By initializing the CPU and running the program from the beginning, or by putting the CPU in stop mode and then running the CPU, you can prevent the CPU from running out of control. Since there is no need to take this into account, the CPU can operate normally without going out of control even in the event of a power outage of any length.

[Brief explanation of the drawing]

FIG. 1 is a specific circuit diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing the state of the supply voltage during a power outage. 1 is the CPU, 2 is the memory backup capacitor, 3 is the reset circuit, V _CC is the power input terminal,
V _DD is a control input terminal, and V DD is a reset terminal.

Claims (1)

[Scope of utility model registration request] There is a power input terminal, a reset terminal that initializes the internals when set to L level, and a reset terminal that stops the internal oscillator when set to L level and is internally pulled down to the ground line, and a reset terminal that initializes the internals when set to L level, and the oscillator operates when set to H level. The reset terminal has a control input terminal that is internally pulled up to the power supply voltage, and in the relationship between the reset terminal and the control input terminal, when the power is turned off, the reset terminal is brought to L level earlier than the control input terminal, and when the power is turned on, the reset terminal is set to L level before the control input terminal. The CPU is equipped with a CPU that sometimes runs out of control unless the reset terminal is set to an H level after the control input terminal goes to an H level, and a capacitor for backing up the memory in the CPU that is connected to the CPU's power input terminal. The reset terminal is set to the L level before the control input terminal is set in the process where the power supply is cut off and the supply voltage decreases, and the control input terminal is set to the L level before the reset terminal is set in the process when the power is restored and the supply voltage increases. A power supply device for a microprocessor comprising a reset circuit for setting the power to H level.