JPH05299533A - Electronic part mounting board and electronic part device using the same - Google Patents

Electronic part mounting board and electronic part device using the same

Info

Publication number
JPH05299533A
JPH05299533A JP12423992A JP12423992A JPH05299533A JP H05299533 A JPH05299533 A JP H05299533A JP 12423992 A JP12423992 A JP 12423992A JP 12423992 A JP12423992 A JP 12423992A JP H05299533 A JPH05299533 A JP H05299533A
Authority
JP
Japan
Prior art keywords
substrate
conductive wire
insulating
wire rods
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP12423992A
Other languages
Japanese (ja)
Inventor
Naoharu Ohigata
直晴 大日方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP12423992A priority Critical patent/JPH05299533A/en
Publication of JPH05299533A publication Critical patent/JPH05299533A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To enable the title electronic part mounting board requiring quiring no complicated steps at all to be manufactured as well as the thermal effect, etc., during the actual operation of the board mounted with electronic parts to be minimized. CONSTITUTION:Within a substrate 1 comprising multiple conductive wire rods 2 for electrically connecting electrode parts as well as multiple insulating wire rods 3 supporting and insulating these multiple conductive wire rods 2, the conductive wire rods 2 and insulating wire rods 3 are weaved into a wooven stuff in a netty shape to be formed into a textile as a whole. At this time, any complicated steps such as photoresist, etching steps, etc., can be eliminated. Furthermore, the conductive wire rods 2 and the insulating wire rods 3 can be independently expanded and contracted thereby enabling the inner stress upon the conductive wire rods 2 caused by the heat generation of the electronic parts to be avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えば半導体チップ等
の電子部品を実装するための基板、及びこの基板を用い
た半導体装置等の電子部品装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting an electronic component such as a semiconductor chip, and an electronic component device such as a semiconductor device using this substrate.

【0002】[0002]

【従来の技術】従来から、各種の電子部品、例えば半導
体チップを実装するための基板として、ラミネート型の
基板やTAB(Tape Automated Bonding)方式の基板等
が知られている。ラミネート型の基板は、ガラスエポキ
シやセラミック等からなる絶縁性平板基材上に、銅箔等
からなる多数の導電性リードパターンを形成したもので
ある。また、TAB方式の基板は、ポリイミド樹脂等か
らなる絶縁性フィルム基材上に銅箔等からなる多数の導
電性リードパターンを形成した、いわゆるフィルムキャ
リヤと称されるものである。
2. Description of the Related Art Conventionally, a laminate type substrate, a TAB (Tape Automated Bonding) type substrate, and the like have been known as substrates for mounting various electronic components such as semiconductor chips. The laminate type substrate is formed by forming a large number of conductive lead patterns made of copper foil or the like on an insulating flat plate base material made of glass epoxy or ceramic. The TAB substrate is a so-called film carrier in which a large number of conductive lead patterns made of copper foil or the like are formed on an insulating film base made of polyimide resin or the like.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上述し
たような従来の基板は、その製作に際して、何れも導電
性リードパターンを形成するためにフォトレジストやエ
ッチング等、或いはTAB方式においては銅箔の打抜き
や接着等、極めて複雑な工程が必要である。このため、
基板の製作に著しく時間を要するという問題があった。
また、従来の基板は、導電性リードパターンが絶縁性基
材上に固着された構造なので、基板上に実装された半導
体チップ等の発熱による基板の熱膨張収縮に対し、導電
性リードパターンと絶縁性基材とが独立して伸縮するこ
とができない。このため、導電性リードパターンに内部
応力が発生し、そのリードパターンが不測に破断される
等の問題もあった。
However, any of the conventional substrates as described above has a photoresist, an etching or the like for forming a conductive lead pattern, or a copper foil is punched in the TAB method. An extremely complicated process such as bonding and gluing is required. For this reason,
There is a problem that it takes much time to manufacture the substrate.
In addition, since the conventional substrate has a structure in which the conductive lead pattern is fixed on the insulating base material, the conductive lead pattern and the conductive lead pattern are insulated against the thermal expansion and contraction of the substrate due to the heat generated by the semiconductor chip mounted on the substrate. The base material cannot expand and contract independently. Therefore, there is a problem that internal stress is generated in the conductive lead pattern and the lead pattern is unexpectedly broken.

【0004】そこで本発明は、複雑な工程を必要とせず
に製作することができ、実使用時には熱影響等を極めて
少なくすることができる電子部品実装用の基板及びこの
基板を用いた電子部品装置を提供することを目的とす
る。
Therefore, according to the present invention, a substrate for mounting electronic components and an electronic component device using this substrate can be manufactured without requiring complicated steps, and the influence of heat can be extremely reduced during actual use. The purpose is to provide.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明による電子部品実装用の基板は、電子部品を
電気的に接続するための多数の導電性の線材と、これら
多数の導電性線材を支持しかつ絶縁するための多数の絶
縁性の線材とからなり、前記多数の導電性線材と前記多
数の絶縁性線材とを互いに織り込んで織物状に形成して
なるものである。また、本発明による電子部品装置は、
上記基板に電子部品を実装し、この電子部品の端子を前
記導電性線材に接続してなるものである。
In order to achieve the above object, a substrate for mounting electronic parts according to the present invention is provided with a large number of conductive wires for electrically connecting electronic parts and a large number of these conductive wires. And a plurality of insulative wire rods for supporting and insulating the conductive wire rod. The plurality of conductive wire rods and the plurality of insulative wire rods are woven together to form a woven fabric. Further, the electronic component device according to the present invention,
An electronic component is mounted on the substrate, and terminals of the electronic component are connected to the conductive wire.

【0006】[0006]

【作用】上記のように構成された本発明によれば、多数
の導電性線材と多数の絶縁性線材とが互いに織り込まれ
て織物状に形成されるので、従来の基板の製作における
導電性リードパターンのフォトレジストやエッチング等
の複雑な工程が不要となる。また、導電性線材と絶縁性
線材とが互いに独立しているので、基板に実装された半
導体チップ等の電子部品の発熱による基板の熱膨張収縮
に対し、導電性線材は柔軟な伸縮が可能となる。
According to the present invention constructed as described above, a large number of conductive wires and a large number of insulating wires are woven into each other to form a woven fabric. No complicated steps such as pattern photoresist and etching are required. In addition, since the conductive wire and the insulating wire are independent of each other, the conductive wire can be flexibly expanded and contracted against thermal expansion and contraction of the board due to heat generation of electronic components such as semiconductor chips mounted on the board. Become.

【0007】[0007]

【実施例】以下、本発明を半導体チップ実装用の基板及
びこの基板を用いた半導体装置に適用した実施例を図面
を参照して説明する。
Embodiments of the present invention applied to a substrate for mounting a semiconductor chip and a semiconductor device using this substrate will be described below with reference to the drawings.

【0008】まず、この基板の基本的な構成を図1〜図
4に示す。
First, the basic structure of this substrate is shown in FIGS.

【0009】図1に示すように、この基板1は、多数の
導電性の線材2と多数の絶縁性の線材3とからなり、こ
れら導電性線材2と絶縁性線材3とが互いに網目状に織
り込まれ、全体として織物状に形成されている。各々の
導電性線材2は一方向に沿って配設されているが、二方
向に沿って配設することも可能である。
As shown in FIG. 1, the substrate 1 is composed of a large number of conductive wires 2 and a large number of insulating wires 3, and the conductive wires 2 and the insulating wires 3 are meshed with each other. Woven and formed into a woven fabric as a whole. Although each conductive wire 2 is arranged along one direction, it is also possible to arrange it along two directions.

【0010】上記導電性線材2を二方向に沿って配設す
ると、場合によっては、各々の導電性線材2が交差部分
で短絡する可能性がある。そこで、図2に示すような構
成の基板1にすることができる。即ち、導電性線材2の
直径は絶縁性線材3の直径よりも充分に小さく構成さ
れ、この導電性線材2が絶縁性線材3の一側面に沿って
延設されている。導電性線材2は絶縁性の結束糸4によ
って絶縁性線材3に部分的に固定されているが、導電性
線材2を絶縁性線材3に予め固着してもよい。この基板
1によれば、導電性線材2を交差する二方向に沿って配
設しても、各々の導電性線材2どうしが接触することは
なく、短絡を防止することができる。
When the conductive wires 2 are arranged along two directions, there is a possibility that each of the conductive wires 2 may be short-circuited at the intersection. Therefore, the substrate 1 having the structure shown in FIG. 2 can be formed. That is, the diameter of the conductive wire 2 is configured to be sufficiently smaller than the diameter of the insulating wire 3, and the conductive wire 2 extends along one side surface of the insulating wire 3. Although the conductive wire 2 is partially fixed to the insulating wire 3 by the insulating binding yarn 4, the conductive wire 2 may be fixed to the insulating wire 3 in advance. According to this substrate 1, even if the conductive wires 2 are arranged along two intersecting directions, the conductive wires 2 do not come into contact with each other, and a short circuit can be prevented.

【0011】また、図3の基板1においては、導電性線
材2が絶縁性線材3によって被覆され、この絶縁性線材
3が互いに織り込まれている。さらに、図4の基板1に
おいては、複数本の導電性線材2a、2b、2c、導電
性線材2a、2b、2c、2dがそれぞれ絶縁性線材3
よって被覆され、これら絶縁性線材3が互いに織り込ま
れている。
Further, in the substrate 1 of FIG. 3, the conductive wire 2 is covered with the insulating wire 3, and the insulating wire 3 is woven with each other. Further, in the substrate 1 of FIG. 4, the plurality of conductive wire rods 2a, 2b, 2c and the conductive wire rods 2a, 2b, 2c, 2d are respectively insulated wire rods 3.
Therefore, they are covered, and these insulating wires 3 are woven together.

【0012】なお、上記各例において、導電性線材2は
必ずしも各々の絶縁性線材3の間に織り込む必要はな
く、任意の間隔で配設することができる。また、導電性
線材2及び絶縁性線材3の断面形状は、円形状に限ら
ず、矩形状あるいは多角形状等でもよい。さらに、上記
基板1をポリイミド樹脂等からなる薄板によって裏打ち
し、補強することも可能である。
In each of the above examples, the conductive wire 2 does not necessarily have to be woven between the insulating wires 3 and can be arranged at any interval. The cross-sectional shapes of the conductive wire 2 and the insulating wire 3 are not limited to circular shapes, and may be rectangular shapes or polygonal shapes. Further, it is possible to reinforce the substrate 1 by backing it with a thin plate made of polyimide resin or the like.

【0013】上述のように構成された基板1によれば、
多数の導電性線材2と多数の絶縁性線材3とが互いに織
り込まれて織物状に形成されるので、従来の基板の製作
における導電性リードパターンのフォトレジストやエッ
チング等の複雑な工程は必要ない。このため、基板1を
極めて簡単に短時間で製作することができる。
According to the substrate 1 configured as described above,
Since a large number of conductive wires 2 and a large number of insulating wires 3 are woven together to form a woven fabric, complicated steps such as photoresist and etching of the conductive lead pattern in the conventional substrate fabrication are not required. .. Therefore, the substrate 1 can be manufactured very easily in a short time.

【0014】次に、図5及び図6は上述のような基板に
半導体チップを実装した半導体装置を示すものである。
Next, FIGS. 5 and 6 show a semiconductor device in which a semiconductor chip is mounted on the substrate as described above.

【0015】基板1はほぼ正方形状に形成され、その中
央部にデバイス孔5が形成されている。図5においては
所定本数の導電性線材2がデバイス孔5の各辺から外周
へ向かって平行状に織り込まれ、図6においては所定本
数の導電性線材2がデバイス孔5の各辺から外周へ向か
って放射状に織り込まれている。この放射状の場合は、
導電性線材2を絶縁性線材3の網目に対して斜めに織り
込めばよい。
The substrate 1 is formed in a substantially square shape, and a device hole 5 is formed in the center thereof. In FIG. 5, a predetermined number of conductive wire rods 2 are woven in parallel from each side of the device hole 5 toward the outer circumference, and in FIG. 6, a predetermined number of conductive wire rods 2 are wound from each side of the device hole 5 to the outer circumference. It is woven in a radial pattern. In this radial case,
The conductive wire 2 may be woven obliquely with respect to the mesh of the insulating wire 3.

【0016】そして、デバイス孔5内において、半導体
チップ6の多数の電極に各々の導電性線材2の一端が接
合され、その半導体チップ6が各々の導電性線材2に電
気的に接続されかつ機械的に保持される。そして、各々
の導電性線材2の他端が所定の外部回路基板等のパター
ンに接続される。即ち、導電性線材2の一端及び他端
は、TAB方式におけるインナーリード及びアウターリ
ードとして機能することになる。
In the device hole 5, one end of each conductive wire 2 is joined to a large number of electrodes of the semiconductor chip 6, the semiconductor chip 6 is electrically connected to each conductive wire 2, and Retained. Then, the other end of each conductive wire 2 is connected to a predetermined pattern such as an external circuit board. That is, one end and the other end of the conductive wire 2 function as an inner lead and an outer lead in the TAB method.

【0017】上述のように基板1に半導体チップ6を実
装した半導体装置によれば、この基板1は、導電性線材
2と絶縁性線材3とが互いに独立しているので、半導体
チップ6等の発熱による基板1の熱膨張収縮に対し、導
電性線材2は柔軟な伸縮が可能となる。このため、導電
性線材2に内部応力が発生することはなく、その導電性
線材2の不測な破断等を防止することができる。
According to the semiconductor device in which the semiconductor chip 6 is mounted on the substrate 1 as described above, since the conductive wire 2 and the insulating wire 3 are independent of each other in the substrate 1, the semiconductor chip 6 and the like are formed. The conductive wire 2 can flexibly expand and contract with respect to thermal expansion and contraction of the substrate 1 due to heat generation. Therefore, no internal stress is generated in the conductive wire 2 and it is possible to prevent the conductive wire 2 from being unexpectedly broken.

【0018】また、この基板1においては、多数の絶縁
性線材3により多数の導電性線材2が絶縁されかつ支持
されるが、換言すると、導電性線材2と絶縁性線材3と
を織り込むことによって、導電性線材2は、絶縁性線材
3により形成される空間内に配設されることになる。従
って、この空間を満たす絶縁性及び比誘電率に優れた気
体(通常は空気)そのものの物性により、基板1の電磁
気特性を向上させることができる。
In addition, in this substrate 1, a large number of conductive wires 2 are insulated and supported by a large number of insulating wires 3. In other words, by weaving the conductive wires 2 and the insulating wires 3 together, The conductive wire 2 is arranged in the space formed by the insulating wire 3. Therefore, the electromagnetic characteristics of the substrate 1 can be improved by the physical properties of the gas (usually air) which is excellent in the insulating property and the relative dielectric constant that fill this space.

【0019】次に、基板1には放熱用の線状部材を織り
込むことができる。例えば図5に示すように、半導体チ
ップ6や抵抗等の発熱し易い部品の近傍には、熱媒体を
流動させる細管7が織り込まれ、この細管7の両端は基
板1の外周部に延出されている。この細管7内に熱媒体
を流動させることによって、半導体チップ6や抵抗等か
ら発生する熱を効率よく外部へ運び去ることができる。
Next, a linear member for heat dissipation can be woven into the substrate 1. For example, as shown in FIG. 5, a thin tube 7 for flowing a heat medium is woven in the vicinity of the semiconductor chip 6 and a component such as a resistor that easily generates heat, and both ends of this thin tube 7 are extended to the outer peripheral portion of the substrate 1. ing. By causing the heat medium to flow in the thin tube 7, the heat generated from the semiconductor chip 6 and the resistor can be efficiently carried away to the outside.

【0020】次に、図7は複数枚の基板を相互に積層す
るようにしたものである。即ち、基板1には複数個のデ
バイス孔5が設けられ、これら各デバイス孔5の間及び
外周部との間に多数の導電性線材2が織り込まれてい
る。また、基板1′にはデバイス孔5′が設けられ、こ
のデバイス孔5′から外周部へ向かって多数の導電性線
材2′が織り込まれている。なお、基板1、1′におい
て互いに対向する導電性線材2、2′は、ほぼ直交する
方向に配設されている。
Next, FIG. 7 shows a structure in which a plurality of substrates are laminated on each other. That is, a plurality of device holes 5 are provided in the substrate 1, and a large number of conductive wires 2 are woven between these device holes 5 and the outer peripheral portion. Further, the substrate 1'is provided with a device hole 5 ', and a large number of conductive wires 2'weave from the device hole 5'to the outer peripheral portion. The conductive wires 2 and 2'opposing each other on the substrates 1 and 1'are arranged in directions substantially orthogonal to each other.

【0021】そして、基板1の各デバイス孔5内におい
て導電性線材2に半導体チップ6が接合されると共に、
基板1′のデバイス孔5′内において導電性線材2′に
半導体チップ6′が接合され、基板1′上に基板1が積
層される。そして、この積層により対向する所定の導電
性線材2と所定の導電性線材2′とが、A−A、B−
B、C−C、D−Dで示すように選択的に接合される。
これによって、各々の半導体チップ6及び6′どうしの
接続が、コンパクトな基板1、1′によって可能とな
る。
Then, the semiconductor chip 6 is bonded to the conductive wire 2 in each device hole 5 of the substrate 1, and
The semiconductor chip 6'is bonded to the conductive wire 2'in the device hole 5'of the substrate 1 ', and the substrate 1 is laminated on the substrate 1'. Then, the predetermined conductive wire 2 and the predetermined conductive wire 2'which are opposed to each other by this lamination are AA and B-.
As shown by B, C-C, and D-D, they are selectively joined.
As a result, the respective semiconductor chips 6 and 6'can be connected to each other by the compact substrates 1 and 1 '.

【0022】なお、上述したような基板1、1′は、プ
ログラマブルコントローラ付きの紡織機により製作する
ことができ、この紡織機のソフトプログラムの変更のみ
で、導電性線材2、2′及び絶縁性線材3、3′を様々
な形状に織り込むことができる。従って、多品種の基板
の生産を、設備を変更することなく行うことができる。
The above-mentioned substrates 1, 1'can be manufactured by a weaving machine with a programmable controller, and the conductive wire 2, 2'and the insulating material can be produced only by changing the soft program of the weaving machine. The wire rods 3, 3'can be woven into various shapes. Therefore, it is possible to produce a wide variety of substrates without changing the equipment.

【0023】以上、本発明の実施例に付き説明したが、
本発明は上記実施例に限定されることなく、本発明の技
術的思想に基づいて各種の有効な変更並びに応用が可能
である。例えば、この基板には半導体チップ以外に各種
の電子部品を実装することができ、基板の形状も任意に
変更することができる。また、基板を積層する場合、本
発明による基板と従来の基板とを積層してもよく、さら
に積層を部分的に行うことも可能である。
The embodiments of the present invention have been described above.
The present invention is not limited to the above embodiments, and various effective modifications and applications are possible based on the technical idea of the present invention. For example, various electronic components other than semiconductor chips can be mounted on this substrate, and the shape of the substrate can be changed arbitrarily. When laminating the substrates, the substrate according to the present invention and the conventional substrate may be laminated, or the laminating may be partially performed.

【0024】[0024]

【発明の効果】以上説明したように、本発明によれば、
多数の導電性の線材と多数の絶縁性の線材とを織り込ん
で織物状に形成することによって、基板の製作に際して
従来の基板におけるフォトレジストやエッチング等の複
雑な工程が不要となるので、基板の製作に要する時間を
大幅に削減することができ、作業効率の向上並びに低コ
スト化を図ることができる。また、導電性線材と絶縁性
線材とが独立して伸縮可能なので、半導体チップ等の発
熱に起因する基板の熱膨張収縮に対し、導電性線材と絶
縁性線材との熱膨張係数の差による内部応力が発生する
ことはなく、その導電性線材の不測な破断等を未然に防
止することができ、信頼性を大幅に高めることができ
る。
As described above, according to the present invention,
By forming a woven fabric by weaving a large number of conductive wires and a large number of insulating wires, complicated steps such as photoresist and etching in a conventional board are not required when manufacturing a board. The time required for manufacturing can be significantly reduced, and the working efficiency can be improved and the cost can be reduced. In addition, since the conductive wire and the insulating wire can expand and contract independently, the internal expansion due to the difference in the thermal expansion coefficient between the conductive wire and the insulating wire against the thermal expansion and contraction of the substrate caused by the heat generation of the semiconductor chip, etc. No stress is generated, unexpected breakage of the conductive wire can be prevented, and reliability can be significantly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における基板の基本的な構成を
示す要部の斜視図である。
FIG. 1 is a perspective view of a main part showing a basic configuration of a substrate according to an embodiment of the present invention.

【図2】基板の基本的な構成を示す要部の斜視図であ
る。
FIG. 2 is a perspective view of a main part showing a basic configuration of a substrate.

【図3】基板の基本的な構成を示す要部の斜視図であ
る。
FIG. 3 is a perspective view of a main part showing a basic configuration of a substrate.

【図4】基板の基本的な構成を示す要部の斜視図であ
る。
FIG. 4 is a perspective view of a main part showing a basic configuration of a substrate.

【図5】本発明の実施例において基板に半導体チップを
実装した半導体装置の平面図である。
FIG. 5 is a plan view of a semiconductor device having a semiconductor chip mounted on a substrate according to an embodiment of the present invention.

【図6】基板に半導体チップを実装した半導体装置の平
面図である。
FIG. 6 is a plan view of a semiconductor device in which a semiconductor chip is mounted on a substrate.

【図7】本発明の実施例において2枚の基板を積層する
際の斜視図である。
FIG. 7 is a perspective view when stacking two substrates in an example of the present invention.

【符号の説明】[Explanation of symbols]

1、1′ 基板 2、2′、2a〜2d 導電性の線材 3、3′ 絶縁性の線材 4 結束糸 5、5′ デバイス孔 6、6′ 半導体チップ 7 熱媒体流動用の細管 1, 1'Substrate 2, 2 ', 2a to 2d Conductive wire rod 3, 3'Insulating wire rod 4 Bundling yarn 5, 5'Device hole 6, 6'Semiconductor chip 7 Heat medium flow thin tube

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 電子部品を電気的に接続するための多数
の導電性の線材と、これら多数の導電性線材を支持しか
つ絶縁するための多数の絶縁性の線材とからなり、前記
多数の導電性線材と前記多数の絶縁性線材とを互いに織
り込んで織物状に形成してなる電子部品実装用の基板。
1. A large number of conductive wire rods for electrically connecting electronic parts and a large number of insulating wire rods for supporting and insulating the large number of conductive wire rods. A substrate for mounting an electronic component, which is formed by weaving a conductive wire and a large number of insulating wires into a woven fabric.
【請求項2】 前記導電性線材を前記絶縁性線材よりも
小径に構成し、この導電性線材を前記絶縁性線材の一側
面に沿って延設したことを特徴とする請求項1記載の電
子部品実装用の基板。
2. The electronic wire according to claim 1, wherein the conductive wire is formed to have a diameter smaller than that of the insulating wire, and the conductive wire is extended along one side surface of the insulating wire. Substrate for mounting components.
【請求項3】 前記導電性線材を前記絶縁性線材によっ
て被覆したことを特徴とする請求項1記載の電子部品実
装用の基板。
3. The board for mounting electronic components according to claim 1, wherein the conductive wire is covered with the insulating wire.
【請求項4】 放熱用の線状部材を織り込んだことを特
徴とする請求項1記載の電子部品実装用の基板。
4. The board for mounting electronic components according to claim 1, wherein a linear member for heat dissipation is woven.
【請求項5】 請求項1記載の基板を複数枚相互に積層
し、これら複数枚の基板の所定の導電性線材どうしを相
互に接合してなる電子部品実装用の基板。
5. A substrate for mounting an electronic component, which is obtained by laminating a plurality of the substrates according to claim 1 and bonding predetermined conductive wires of the plurality of substrates to each other.
【請求項6】 請求項1または5記載の基板に電子部品
を実装し、この電子部品の端子を前記導電性線材に接続
してなる電子部品装置。
6. An electronic component device in which an electronic component is mounted on the substrate according to claim 1 or 5, and terminals of the electronic component are connected to the conductive wire.
JP12423992A 1992-04-17 1992-04-17 Electronic part mounting board and electronic part device using the same Withdrawn JPH05299533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12423992A JPH05299533A (en) 1992-04-17 1992-04-17 Electronic part mounting board and electronic part device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12423992A JPH05299533A (en) 1992-04-17 1992-04-17 Electronic part mounting board and electronic part device using the same

Publications (1)

Publication Number Publication Date
JPH05299533A true JPH05299533A (en) 1993-11-12

Family

ID=14880415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12423992A Withdrawn JPH05299533A (en) 1992-04-17 1992-04-17 Electronic part mounting board and electronic part device using the same

Country Status (1)

Country Link
JP (1) JPH05299533A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003161844A (en) * 2001-11-26 2003-06-06 Japan Science & Technology Corp Hybrid integrated circuit by fabric structure, and electronic and optical integrated device thereof
JP2003309225A (en) * 2003-05-12 2003-10-31 Oki Electric Ind Co Ltd Cloth substrate and semiconductor device
US6674008B2 (en) 1999-12-16 2004-01-06 Oki Electric Industry Co., Ltd. Cross substrate, method of mounting semiconductor element, and semiconductor device
US6856715B1 (en) 1999-04-30 2005-02-15 Thin Film Electronics Asa Apparatus comprising electronic and/or optoelectronic circuitry and method for realizing said circuitry
JP2006310554A (en) * 2005-04-28 2006-11-09 Katsuya Hiroshige Aligned conductive wiring board
JP2006332647A (en) * 2005-05-13 2006-12-07 Sefar Ag Circuit board and method of manufacturing the same
WO2008069275A1 (en) * 2006-12-07 2008-06-12 Nec Corporation Wiring board and method for manufacturing the same
JP2012511811A (en) * 2008-12-09 2012-05-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Flexible modular assembly
JP2013147767A (en) * 2012-01-19 2013-08-01 Fukui Prefecture Electronic component mounting weave, electronic component mounting body and fabric using the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6856715B1 (en) 1999-04-30 2005-02-15 Thin Film Electronics Asa Apparatus comprising electronic and/or optoelectronic circuitry and method for realizing said circuitry
US7248756B2 (en) 1999-04-30 2007-07-24 Thin Film Electronics Asa Apparatus comprising electronic and/or optoelectronic circuitry and method for realizing said circuitry
US6674008B2 (en) 1999-12-16 2004-01-06 Oki Electric Industry Co., Ltd. Cross substrate, method of mounting semiconductor element, and semiconductor device
US6797881B2 (en) 1999-12-16 2004-09-28 Oki Electric Industry Co., Ltd. Cross substrate, method of mounting semiconductor element, and semiconductor device
JP2003161844A (en) * 2001-11-26 2003-06-06 Japan Science & Technology Corp Hybrid integrated circuit by fabric structure, and electronic and optical integrated device thereof
JP2003309225A (en) * 2003-05-12 2003-10-31 Oki Electric Ind Co Ltd Cloth substrate and semiconductor device
JP2006310554A (en) * 2005-04-28 2006-11-09 Katsuya Hiroshige Aligned conductive wiring board
JP2006332647A (en) * 2005-05-13 2006-12-07 Sefar Ag Circuit board and method of manufacturing the same
WO2008069275A1 (en) * 2006-12-07 2008-06-12 Nec Corporation Wiring board and method for manufacturing the same
JP2012511811A (en) * 2008-12-09 2012-05-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Flexible modular assembly
JP2013147767A (en) * 2012-01-19 2013-08-01 Fukui Prefecture Electronic component mounting weave, electronic component mounting body and fabric using the same

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Effective date: 19990706