JPH0529552A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the difference between drain currents flowing between the sources and drains of field effect transistors connected to pads for power supply by changing the distances between the sources and gates of the transistors by means of the connecting positions of the transistors so that the distances can become longer as going toward the pads for power supply. CONSTITUTION:A plurality of field effect transistors 22b and 24b connected to wiring electrodes 5 and 6 which in turn are connected to pads 8a and 8b for power supply are incorporated in a semiconductor device provided with a logic circuit. The distance between the gate and source of the transistor 22b which is connected to the electrodes 5 and 6 at positions nearer to the pads 8a and 8b is made longer than that of the transistor 24b connected to the electrodes 5 and 6 at positions farther from the pads 8a and 8b. Therefore, even when a plurality of field effect transistors 22b and 24b are connected to the same wiring electrodes 5 and 6, the difference between drain currents flowing to the sources and drains of the transistors 22b and 24b becomes smaller and the fluctuation of the operating voltage can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a logic circuit composed of a plurality of field effect transistors connected to the same power source.

[0002]

2. Description of the Related Art GaAs FETs are characterized by high speed, low power consumption, and high integration, and therefore DCFL (direct cou
pled FET logic) circuit is applied.

As a DCFL circuit, for example, as shown in FIG. 2 (a), an inverter 2, 3 composed of depletion GaAs FETs 2a, 3a and enhancement GaAs FETs 2b, 3b connected in series is directly connected in a plurality of stages. Think The upper surface of the semiconductor chip 7 including such a circuit is shown in FIG.
It becomes as shown in (b).

A plurality of enhancement GaAs FETs formed on the semiconductor chip are Schottky bonded to the upper surface of the n-GaAs active layer 32 in the upper layer of the semi-insulating GaAs substrate 31 as shown in FIG. 3 (a). The gate electrode 33 and the source electrode 34 and the drain electrode 35, which are ohmic-joined on both sides thereof, have the same distance between the source and the gate in all enhancement GaAs FETs.

[0005]

However, this DCFL
The circuit has a large amplification factor but a small noise margin. Therefore, in the semiconductor integrated circuit, as shown in FIG. By comparison, the electrode pads 8a and 8b
The drain currents of the enhancement GaAs FETs 2b and 3b for switching are different due to the voltage drop of the wiring resistance connected to, and the operating voltage changes (FIG. 3 (b)).

Therefore, when signals are exchanged between the cells in the central portion and the peripheral portions, there is a problem that the logic threshold value of the semiconductor integrated circuit changes and an operation error is likely to occur.
On the other hand, it is possible to reduce the resistance by widening the width of the power supply wiring or increasing the thickness thereof, but this is also restricted in terms of layout and process.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of reducing a difference in logic threshold value of a transistor due to a voltage drop of a wiring voltage.

[0008]

[Means for Solving the Problems]
In a semiconductor integrated circuit device having a plurality of field effect transistors 22b and 24b connected to the wiring electrodes 5 and 6 connected to the power supply pads 8a and 8b, as shown in FIG. Supply pad 8a,
The field effect transistor connected to a position near 8b
The semiconductor integrated circuit is characterized in that the gate-source distance of 22b is made larger than the gate-source distance of the field effect transistor 24b connected to a position far from the power supply pads 8a, 8b. Achieved by the device.

[0009]

[Operation] According to the present invention, power supply pads 8a, 8
The distance between the source and the gate is changed depending on the connection position of the field effect transistors 22b and 24b connected to b so that the distance becomes wider toward the power supply pads 8a and 8b.

As a result, even if a plurality of field effect transistors 22b and 24b are connected to the same wiring electrode 5 and 6, the difference between the drain currents flowing between the source and drain thereof is reduced, and fluctuations in operating voltage are suppressed. It

Therefore, the voltage drop due to the power supply wiring electrodes 5 and 6 is compensated by the field effect transistors 22b and 24b themselves, the logic thresholds are equalized, the operation error is reduced, and the semiconductor integrated circuit can be stabilized.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a DCFL of a semiconductor integrated circuit device.
FIG. 3 is a circuit diagram showing a part of a circuit and a plan view of a semiconductor integrated circuit device.

In FIG. 2A, reference numeral 1 is a buffer circuit in which two inverters 2 and 3 are directly connected, and the output terminal thereof is directly connected to one of the input terminals of the NOR circuit 4. The buffer circuit 1 and the NOR circuit 4 are connected in parallel to the same wiring electrodes 5 and 6 for power supply.

Each inverter 2, 3 has a depletion
Source enhancement of GaAs FETs 2a and 3a GaAs F
It is connected to the drains of ETs 2b and 3b. Also,
The NOR circuit 4 connects the drains of two enhancement GaAs FETs 4b connected in parallel to the depletion GaAs FET.
4a connected to the source.

Further, each of the above-mentioned depletion GaAs F
The ETs 2a, 3a, 4a have their gates and sources short-circuited to serve as constant current sources, and their drains are connected to the wiring electrode 5 of voltage Vdd. Further, each of the enhancement GaAs FETs 2b, 3b, 4b described above is connected to the wiring electrode 6 having the voltage Vss.

The semiconductor chip 7 having such a semiconductor circuit as a part has a plane as shown in FIG. 2B, the semiconductor circuit is formed in the central region X, and wiring electrodes 5, 6 are provided. The power supply pads 8a and 8b connected to are arranged along the periphery thereof. The NOR circuit 4 is formed in a region closer to the center of the semiconductor chip 7 than the buffer circuit 1. Further, the inverter 2 at the previous stage forming the buffer circuit 1 has the power supply pads 8 a and 8 b more than the NOR circuit 4.
Is connected to the wiring electrodes 5 and 6 at positions close to, and a voltage drop occurs at the wiring electrodes 5 and 6 between them due to the resistance component R thereof.

FIG. 1 shows two enhancement GaAs FETs 2 which form the respective switching portions of the inverter 2 and the NOR circuit 4 in the preceding stage of the buffer circuit 1 shown in FIG.
b and 4b are shown, and in the present embodiment, those elements are denoted by reference numerals 22b and 24b.

In FIG. 1, reference numeral 11 is a semi-insulating GaAs substrate, and two regions are provided with a first n-GaAs by introducing impurities.
An active layer 12 and a second n-GaAs active layer 16 are formed. A gate electrode 13 is Schottky-junctioned in a region passing through the center of the upper surface of the first n-type GaAs active layer 12, and is formed with a source electrode 14 on both sides thereof at regular intervals L ₁ and L _0. The drain electrode 15 is ohmic-junctioned, so that the enhancement GaAs FET 22b of the front stage inverter 2 of the buffer circuit 1 is configured.

Further, a gate electrode 17 which makes a Schottky junction is also provided on the upper surface of the second n-type GaAs layer 16, and a source electrode 18 and a drain which make an ohmic junction at a constant distance L ₂ and L ₀ on both sides thereof. The electrode 19 is attached, and thereby the enhancement GaAs FET 24b of the NOR circuit 4 is constructed.

In this case, the enhancement GaAs FET22
b, 24b gate electrodes 13, 17 and source electrodes 14, 1
The distances L ₁ and L ₂ from the NOR circuit 8 are NOR than the buffer circuit 1.
The circuit 4 is relatively narrower (L ₁
> L ₂ ), thereby enhancing the NOR circuit 4
It is configured to reduce the resistance between the source and drain of the GaAs FET 24b.

Therefore, even if a plurality of GaAs FETs 22b and 24b are connected to the same wiring electrode 5 and 6, the difference in drain current flowing between the source and drain of them is reduced, and the fluctuation of the operating voltage is suppressed.

In the semiconductor integrated circuit, if the distance between the source and the gate is adjusted as described above, the voltage drop due to the power supply wiring electrodes 5 and 6 will be compensated by the GaAs FET itself, and the logical threshold value will be Equal to reduce operation errors.

It goes without saying that the source-gate distance of the enhancement GaAs FET 3b in the latter stage of the buffer circuit is made smaller than that in the former stage.

[0024]

As described above, according to the present invention, the distance between the source and the gate is changed depending on the connection position of the field effect transistor connected to the power supply pad so that the closer to the power supply pad, the wider. Therefore, even if a plurality of field effect transistors are connected to the same wiring electrode, it is possible to reduce the difference in drain current flowing between the source and drain of the field effect transistors and reduce the fluctuation in operating voltage.

Therefore, the voltage drop due to the power supply wiring electrode is compensated by the field effect transistor itself, the logic thresholds are made equal to reduce the operation error, and the semiconductor integrated circuit can be stabilized.

[Brief description of drawings]

FIG. 1 is a sectional view and a plan view showing an apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a DCFL circuit and a plan view of a semiconductor integrated circuit device.

FIG. 3 is a cross-sectional view showing an example of a GaAs FET and its input / output characteristic diagram.

[Explanation of symbols]

1 Buffer circuit 2, 3 Inverter 2b, 3b, 4b Depletion GaAs FET 2b, 3b, 4b Enhancement GaAs FET 5, 6 Wiring electrode 7 Semiconductor chip 8a, 8b Power supply pad 11 GaAs substrate 12, 17 Active layer 13, 17 Gate Electrodes 14, 18 Source electrodes 15, 19 Drain electrodes 22b, 24b Enhancement GaAs FET (field effect transistor)

Claims (1)

Claim: What is claimed is: 1. A semiconductor integrated circuit device comprising a plurality of field effect transistors (22b, 24b) connected to wiring electrodes (5, 6) connected to power supply pads (8a, 8b). , The power supply pads (8) of the wiring electrodes (5, 6)
a, 8b), the gate-source distance of the field effect transistor (22b) connected to the field effect transistor (22b) is far from the power supply pad (8a, 8b). ) The semiconductor integrated circuit device is characterized in that it is larger than the gate-source distance.