JPH0529482A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0529482A
JPH0529482A JP17862191A JP17862191A JPH0529482A JP H0529482 A JPH0529482 A JP H0529482A JP 17862191 A JP17862191 A JP 17862191A JP 17862191 A JP17862191 A JP 17862191A JP H0529482 A JPH0529482 A JP H0529482A
Authority
JP
Japan
Prior art keywords
film
insulating film
electrode wiring
wiring
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17862191A
Other languages
Japanese (ja)
Other versions
JP3039006B2 (en
Inventor
Shoji Okuda
章二 奥田
Masahiko Toki
雅彦 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP3178621A priority Critical patent/JP3039006B2/en
Publication of JPH0529482A publication Critical patent/JPH0529482A/en
Application granted granted Critical
Publication of JP3039006B2 publication Critical patent/JP3039006B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To form electrode wiring which is free from blowholes and has a high aspect ratio by forming the first insulating film so that the insulating film can cover the side wall of an electrode wiring film and an overhang section below the side wall and second insulating film which covers the first insulating film after the outer edge of the first insulating film is etched with plasma ions. CONSTITUTION:An SiO2 film 18 is formed by isotropic coating so that the film 18 can have a uniform thickness and can fill up the overhang section 17 of an Al-wiring film 16 on an Si substrate 15 by irradiating the overhang section 17 with oxygen plasma under a non-bias condition. Then the corners of the film 18 are rounded by performing sputter etching of oxygen ions 19 by using an oxygen or argon gas. When a PSG film 20 is then formed in a uniform thickness, the overhang section 17 can be filled up and a two-layer covering insulating film can be formed of the SiO2 film 18 having the round corners and PSG film 20. Therefore, wiring having a high aspect ratio can be insulated from another wiring having another high aspect ratio.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,半導体装置の成膜方法
に関し,特にECR−P−CVD装置等において,逆テ
ーパーやオーバーハング部のできた電極配線膜上に絶縁
膜を形成する製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film forming method for a semiconductor device, and more particularly to a manufacturing method for forming an insulating film on an electrode wiring film having an inverse taper or an overhang portion in an ECR-P-CVD device. .

【0002】ますます大集積化するなかで,電極配線膜
の間隔は狭くなり,配線間の高アスペクト比化がプロセ
ス上問題になっている。この高アスペクト比化された配
線間を絶縁膜で埋め込むことが困難なため,大集積化の
妨げとなっている。
With increasing integration, the distance between the electrode wiring films has become narrower, and a higher aspect ratio between wirings has become a problem in the process. Since it is difficult to embed the insulating film between the wirings having the high aspect ratio, this hinders the large scale integration.

【0003】[0003]

【従来の技術】図4は従来例の説明図である。図におい
て,21は半導体基板, 22は電極配線膜, 23はオーバーハ
ング部, 24は絶縁膜, 25は絶縁膜, 26は鬆〔す〕であ
る。
2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example. In the figure, 21 is a semiconductor substrate, 22 is an electrode wiring film, 23 is an overhang portion, 24 is an insulating film, 25 is an insulating film, and 26 is a void.

【0004】従来は,図4(a)に示すように,半導体
基板21上に電極配線膜22を形成後,表面処理を行い,続
いて,図4(b)に示すように,半導体基板21及び電極
配線膜22上に二酸化シリコン(SiO2)膜等の絶縁膜24を成
長してから,電極配線膜22の上縁の部分をアルゴン等で
スパッタして,順テーパー形状を形成していた。
Conventionally, as shown in FIG. 4A, after forming an electrode wiring film 22 on a semiconductor substrate 21, a surface treatment is performed, and subsequently, as shown in FIG. After growing an insulating film 24 such as a silicon dioxide (SiO 2 ) film on the electrode wiring film 22, the upper edge portion of the electrode wiring film 22 was sputtered with argon or the like to form a forward tapered shape. .

【0005】[0005]

【発明が解決しようとする課題】ECR−P−CVD装
置で絶縁膜を形成する場合,異方性が強いため配線上に
は厚く成膜され,側壁には薄く成膜される特徴がある。
When an insulating film is formed by an ECR-P-CVD apparatus, it has a feature that it is formed thick on the wiring and thin on the side wall because of strong anisotropy.

【0006】この特徴を利用して配線上に順テーパー形
状に成膜することができる。しかし,配線自体が逆テー
パーになっていたり,オーバーエッチングにより電極配
線膜22のサイドの下部にオーバーハング部23ができてい
ると,この強い異方性のため, 図4(c)に示すよう
に,いわゆる「鬆(す)」26と称する空洞が入ったまま
成膜してしまい,特性的に好ましくない。
By utilizing this feature, it is possible to form a film in a forward taper shape on the wiring. However, if the wiring itself has a reverse taper, or if the overhanging portion 23 is formed below the side of the electrode wiring film 22 due to overetching, this strong anisotropy causes the formation of an overhang portion 23 as shown in FIG. In addition, the film is formed with a so-called "void" 26 in the cavity, which is not preferable in terms of characteristics.

【0007】本発明は,以上の点を鑑み,ECR−P−
CVD装置等において,逆テーパー, 或いはオーバーハ
ング部のできた電極配線膜上に絶縁膜を形成する場合の
電極膜側壁への鬆の発生を防ぐことを目的として提供さ
れるものである。
In view of the above points, the present invention is ECR-P-
It is provided for the purpose of preventing generation of voids on the side wall of an electrode film when forming an insulating film on an electrode wiring film having an inverse taper or an overhang portion in a CVD device or the like.

【0008】[0008]

【課題を解決するための手段】図1は本発明の原理説明
図である。図において,1は半導体基板,2は電極配線
膜,3は第1の絶縁膜,4はオーバーハング部,5はプ
ラズマイオン,6は第2の絶縁膜である。
FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an electrode wiring film, 3 is a first insulating film, 4 is an overhang portion, 5 is plasma ions, and 6 is a second insulating film.

【0009】上記の問題点を解決する本発明について,
図1により説明する。先ず,図1(a)に示すように,
電極配線膜2が形成された半導体基板1上に, 該電極配
線膜2の側壁及び該電極配線膜2下のオーバーハング部
4にも被覆するように第1の絶縁膜3を形成する。
With respect to the present invention which solves the above problems,
This will be described with reference to FIG. First, as shown in FIG.
On the semiconductor substrate 1 on which the electrode wiring film 2 is formed, the first insulating film 3 is formed so as to cover the side wall of the electrode wiring film 2 and the overhang portion 4 under the electrode wiring film 2.

【0010】次に,図1(b)に示すように,プラズマ
イオン5により, 該第1の絶縁膜3をエッチングして,
該第1の絶縁膜3の外縁をエッチングする。続いて,図
1(c)に示すように,該第1の絶縁膜3を覆って,第
2の絶縁膜6を形成する。
Next, as shown in FIG. 1B, the first insulating film 3 is etched by plasma ions 5,
The outer edge of the first insulating film 3 is etched. Subsequently, as shown in FIG. 1C, a second insulating film 6 is formed so as to cover the first insulating film 3.

【0011】[0011]

【作用】本発明では,最初,オーバーハング部のでき
た,或いは逆テーパーの電極配線膜2に数拾mmTorrから
数Torrの圧力域で, バイアスをかけないで第1の絶縁膜
3を形成する。このように圧力域を高くして,異方性を
少なくし,電極配線膜上に均等に絶縁膜を被覆する。
According to the present invention, first, the first insulating film 3 is formed on the electrode wiring film 2 having an overhang portion or an inverse taper in a pressure range of several mm to Torr to several Torr without biasing. In this way, the pressure range is increased, the anisotropy is reduced, and the insulating film is evenly coated on the electrode wiring film.

【0012】そして,成膜後,酸素プラズマ或いはアル
ゴンプラズマにてバイアスを掛けてスパッタエッチング
して第1の絶縁膜の上縁を削って順テーパーを形成す
る。プラズマイオンはアルゴンプラズマより酸素プラズ
マの方が半導体基板に対するダメージが少ない。
After film formation, a bias is applied with oxygen plasma or argon plasma to carry out sputter etching to scrape the upper edge of the first insulating film to form a forward taper. Regarding plasma ions, oxygen plasma causes less damage to the semiconductor substrate than argon plasma.

【0013】最後に,バイアスを掛けて異方性を強く
し,第2の絶縁膜を順テーパー形状に被覆する。これに
よって,すのない高アスペクト比の電極配線膜が形成で
きる。
Finally, a bias is applied to increase the anisotropy, and the second insulating film is coated in a forward taper shape. As a result, an electrode wiring film having a high aspect ratio can be formed.

【0014】[0014]

【実施例】図2は本発明に用いたECR−P−CVD装
置の断面の概要図,図3は本発明の一実施例の工程順模
式断面図である。
EXAMPLE FIG. 2 is a schematic sectional view of an ECR-P-CVD apparatus used in the present invention, and FIG. 3 is a schematic sectional view in order of steps of an example of the present invention.

【0015】図において, 7は静電チャック,8は反応
室,9はプラズマ生成室,10はソレノイドコイル, 11は
サブソレノイドコイル,12はシランガス供給口, 13は窒
素,酸素ガス供給口, 14は排気口, 15はSi基板, 16はAl
配線膜, 17はオーバーハング部, 18はSiO2膜, 19はOイ
オン,20はPSG 膜である。
In the figure, 7 is an electrostatic chuck, 8 is a reaction chamber, 9 is a plasma generation chamber, 10 is a solenoid coil, 11 is a sub-solenoid coil, 12 is a silane gas supply port, 13 is a nitrogen and oxygen gas supply port, 14 Is an exhaust port, 15 is a Si substrate, 16 is Al
A wiring film, 17 is an overhang portion, 18 is a SiO 2 film, 19 is an O ion, and 20 is a PSG film.

【0016】本発明の一実施例について,工程順に説明
する。図3(a)に示すように,表面の自然酸化膜等を
弗素イオンで軽く除去してできたSi基板15上のAl配線膜
16のオーバーハング部16には,図3に示す装置を用い,
酸素プラズマをノンバイアスでSi基板15に照射し,Si基
板15の表面に吸着している水を飛散させる。
An embodiment of the present invention will be described in the order of steps. As shown in FIG. 3A, an Al wiring film on the Si substrate 15 formed by lightly removing the natural oxide film on the surface with fluorine ions.
For the overhang portion 16 of 16, the device shown in FIG. 3 is used,
The Si substrate 15 is irradiated with oxygen plasma without bias, and the water adsorbed on the surface of the Si substrate 15 is scattered.

【0017】そして,図3(b)に示すように, 245GHz
のマイクロ波の出力 400W,真空度1〜2mmTorrで, シ
ラン(SiH4)20sccm, 酸素(O2)20sccm, 窒素(N2)2sccm の
プロセスガスを用いた等方性被覆により, 成膜時間30秒
で膜厚500 〜1,000 ÅにSiO2膜18を均一な厚さで,しか
もオーバーハング部17を埋めて形成する。
Then, as shown in FIG. 3B, 245 GHz
Microwave power of 400W, vacuum degree of 1-2mmTorr, isotropic coating using silane (SiH 4 ) 20sccm, oxygen (O 2 ) 20sccm, nitrogen (N 2 ) 2sccm process gas, deposition time 30 In a second, the SiO 2 film 18 is formed to have a uniform film thickness of 500 to 1,000 Å and the overhang portion 17 is filled.

【0018】次に, 図3(c)に示すように,酸素或い
はアルゴン(Ar)ガスを用い,Oイオン19等により, マイ
クロ波 2.45GHz, 出力 400W, RF周波数 13.56MHz, 7
00W,真空度1〜2mmTorrで, スパッタエッチングを行
い, SiO2膜18の上縁を削って,SiO2膜18の角を緩やかに
する。
Next, as shown in FIG. 3 (c), oxygen or argon (Ar) gas is used, and by O ions 19 or the like, microwave 2.45 GHz, output 400 W, RF frequency 13.56 MHz, 7
00W, vacuum degree 1~2MmTorr, perform sputter etching, abrading the upper edge of the SiO 2 film 18, to slow the corners of the SiO 2 film 18.

【0019】続いて, 245GHzのマイクロ波の出力 400
W,RF周波数 13.56MHz, 出力 700W,真空度1〜2
mmTorrで, 反応室中にSiH4 20sccm, O2 20sccm, N2 2s
ccm のプロセスガスを導入し, 3,000 Åの厚さの燐珪酸
ガラス(PSG膜) 20を均一な厚さに形成する。
Then, the output of microwave of 245 GHz 400
W, RF frequency 13.56MHz, output 700W, degree of vacuum 1-2
mmTorr, SiH 4 20sccm, O 2 20sccm, N 2 2s in the reaction chamber
introducing a process gas ccm, to form a 3,000 Å thick of phosphosilicate glass (PSG film) 20 a uniform thickness.

【0020】これによりオーバーハング部16を埋め,角
がなだらかなSiO2膜18とPSG 膜20の二層のカバー絶縁膜
が形成できる。
As a result, the overhang portion 16 is filled, and a two-layer cover insulating film of the SiO 2 film 18 and the PSG film 20 having a gentle corner can be formed.

【0021】[0021]

【発明の効果】以上説明したように, 本発明によれば,
容易に順テーパーの絶縁膜を形成することができるた
め,高アスペクト比の配線間を容易に絶縁することがで
き,大集積化を容易にする。
As described above, according to the present invention,
Since a forward-tapered insulating film can be easily formed, it is possible to easily insulate between high-aspect-ratio wirings, which facilitates large-scale integration.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.

【図2】 本発明に用いたECR−P−CVD装置の概
形図
FIG. 2 is a schematic diagram of an ECR-P-CVD apparatus used in the present invention.

【図3】 本発明の一実施例の工程順模式断面図FIG. 3 is a schematic cross-sectional view in order of the processes of an embodiment of the present invention.

【図4】 従来例の説明図FIG. 4 is an explanatory diagram of a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 電極配線膜 3 第1の絶縁膜 4 オーバーハング部 5 プラズマイオン 6 第2の絶縁膜 7 静電チャック 8 反応室 9 プラズマ生成室 10 ソレノイドコイル 11 サブソレノイドコイル 12 シランガス供給口 13 窒素,酸素ガス供給口 14 排気口 15 Si基板, 16 Al配線膜, 17 オーバーハング部 18 SiO2膜 19 Oイオン 20 PSG 膜1 Semiconductor Substrate 2 Electrode Wiring Film 3 First Insulating Film 4 Overhang Part 5 Plasma Ion 6 Second Insulating Film 7 Electrostatic Chuck 8 Reaction Chamber 9 Plasma Generation Chamber 10 Solenoid Coil 11 Sub Solenoid Coil 12 Silane Gas Supply Port 13 Nitrogen , Oxygen gas supply port 14 Exhaust port 15 Si substrate, 16 Al wiring film, 17 Overhang part 18 SiO 2 film 19 O ion 20 PSG film

Claims (1)

【特許請求の範囲】 【請求項1】 プラズマCVD法を用いた半導体装置の
製造方法において, 電極配線膜(2) が形成された半導体基板(1) 上に, 第1
の絶縁膜(3) を形成する第1の工程と, プラズマイオン(5) により, 該第1の絶縁膜(3) をエッ
チングして,該第1の絶縁膜(3) の外縁をテーパー状に
形成する第2の工程と, 該第1の絶縁膜(3) を覆って,第2の絶縁膜(6) を形成
する第3の工程とを含み, 前記第1の工程は,実質的にプラズマにバイアスをかけ
ることなく,かつ前記電極配線膜(2) 表面及び前記半導
体基板(1) 表面が前記第1の絶縁膜(3) にて密着被覆さ
れるような異方性にて行い, 前記第3の工程は,プラズマにバイアスをかけて,かつ
前記第1の工程よりも高い異方性にて行うことを特徴と
する半導体装置の製造方法。
Claim: What is claimed is: 1. A method of manufacturing a semiconductor device using a plasma CVD method, comprising: forming a first substrate on a semiconductor substrate (1) having an electrode wiring film (2) formed thereon;
The first step of forming the insulating film (3), and the outer edge of the first insulating film (3) is tapered by etching the first insulating film (3) with plasma ions (5). And a third step of forming the second insulating film (6) so as to cover the first insulating film (3) and the first step is substantially the same. Without biasing the plasma, and with anisotropy such that the surface of the electrode wiring film (2) and the surface of the semiconductor substrate (1) are adhered and covered with the first insulating film (3). The method of manufacturing a semiconductor device is characterized in that the third step is performed by applying a bias to plasma and with a higher anisotropy than that of the first step.
JP3178621A 1991-07-19 1991-07-19 Method for manufacturing semiconductor device Expired - Fee Related JP3039006B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3178621A JP3039006B2 (en) 1991-07-19 1991-07-19 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3178621A JP3039006B2 (en) 1991-07-19 1991-07-19 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0529482A true JPH0529482A (en) 1993-02-05
JP3039006B2 JP3039006B2 (en) 2000-05-08

Family

ID=16051653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3178621A Expired - Fee Related JP3039006B2 (en) 1991-07-19 1991-07-19 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3039006B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020004854A (en) * 2018-06-28 2020-01-09 ルネサスエレクトロニクス株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020004854A (en) * 2018-06-28 2020-01-09 ルネサスエレクトロニクス株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP3039006B2 (en) 2000-05-08

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