JPH0529469A - Test facilitating circuit - Google Patents

Abstract

PURPOSE:To make it possible to communicate more signals with an internal circuit through only one pin for test exclusive use by a method wherein the output terminals of EOR circuits are respectively connected to the input terminals of output buffer circuits, the input terminals on one side of the input terminals of the EOR circuits are connected with the internal circuit and the other input terminals of the EOR circuits are connected to one another and are connected to the pin. CONSTITUTION:In a test facilitating circuit 20, EOR circuits 21A, 21B,... are respectively provided in such a way as to correspond to output buffer circuits 12A, 12B.... Output terminals of the circuits 21A, 21B,... are respectively connected to input terminals of the circuits 12A, 12B,..., the input terminals on one side of input terminals of the circuits 21A, 21B,... are connected with an internal circuit 10, the other input terminals of the circuits 21A, 21B,... are connected to one another and, at the same time, are connected with a pin 22 for test exclusive use via a buffer circuit 22A. A signal at a low level and a signal at a high level are applied in order to this one pin 22, whereby the levels of both outputs of a high-level output and low-level output of each output buffer circuit can be verified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test facilitating circuit, and more particularly to a circuit for facilitating a test of an output buffer circuit which constitutes a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, an output buffer circuit is provided between an internal circuit and an output pin in order to output the output of the internal circuit to the outside. The normal operation of this output buffer circuit is indispensable for correctly transmitting the logic output of the semiconductor integrated circuit to the outside.

Therefore, it is necessary to test (test) that the output buffer circuit operates normally, that is, whether the high-level output and the low-level output with respect to a constant input have potentials within a predetermined range. Such tests are required to be easy and accurate. Due to such a demand, conventionally, in a semiconductor integrated circuit, in order to facilitate testing, for example, as shown in FIG. 5, an internal circuit 10 and an output buffer circuit 1 are provided.
A test facilitating circuit 8 is provided between 2A, 12B, ... In FIG. 5, reference numerals 11A, 11B ... Are output pins.

In the test facilitation circuit shown in FIG. 5,
Two on the input side of each output buffer circuit 12A, 12B, ...
The output sides of the input multiplexers 14A, 14B, ... Are connected, and the 2-input multiplexers 14A, 14B,
The output of the internal circuit 10 is connected to one input side of ...
A level input pin 16 is connected to the other input side of each of the 2-input multiplexers 14A, 14B, ... Through a buffer circuit 16A. A test mode switching pin 18 is connected to the control input terminal S of each of the 2-input multiplexers 14A, 14B, ... Through a buffer circuit 18A.

In the test facilitation circuit shown in FIG. 5, the normal operation selection signal (for example, H level) is inputted from the test mode switching pin 18 during the normal operation so that the multiplexers 14A, 14B, ... The input on the “1” side shown in is selected, which causes the internal circuit 1
The output signal of 0 is output from the output pins 11A, 11B, ... Through the multiplexers 14A, 14B ,.

On the other hand, at the time of testing, by inputting a test operation selection signal (for example, L level) from the test mode switching pin 18, each multiplexer 14A, 14B, ...
Then, the "0" side input shown in FIG. 4 is selected. In this state, a test signal is input from the level input pin 16 to operate the output buffer circuits 12A, 12B, ...
The output buffer circuits 12A, 12B, ... Are tested by monitoring whether or not the output is within a predetermined range of voltage values.

[0007]

Even in the conventional test facilitating circuit shown in FIG. 5, the output buffer circuit 12A,
The test of 12B, ... can be easily done,
In order to facilitate the testing of the output buffer circuits 12A, 12B, ..., Two pins dedicated to the test, that is, the level input pin 16 and the test mode switching pin 18, were required.

Here, in using the semiconductor integrated circuit, the larger the number of pins that can be used, the easier the exchange of signals with the internal circuit, which is preferable. Therefore, the semiconductor integrated circuit tends to have many pins today. However, there is a limit to the increase in the number of pins, and it is desirable to use the pins so that more signals can be exchanged with the internal circuit within the range of the pins currently provided.

However, as described above, the test-dedicated pin is 2
Using one reduces the number of other pins that can be used, and the dedicated test pins are unnecessary in normal operation. Therefore, it is required to reduce the number of test-dedicated pins, but there has been a problem that such a request cannot be met because there is no technique that can use only one test-dedicated pin.

The present invention has been made to solve the above-mentioned conventional problems. In the semiconductor integrated circuit, the output signal level of the output buffer can be externally controlled by using only one test-dedicated pin. An object of the present invention is to provide a test facilitation circuit that can facilitate testing.

[0011]

A test facilitation circuit of the present invention for achieving the above object is a semiconductor test circuit for facilitating a test of an output buffer circuit which constitutes a semiconductor integrated circuit. Each exclusive-OR circuit is provided between each internal buffer circuit and each output buffer circuit, the output terminal of each exclusive-OR circuit is connected to the input terminal of each output buffer circuit, and each exclusive-OR circuit is connected. One of the input terminals of the circuit is connected to the internal circuit, and the other of the input terminals of the exclusive OR circuits is connected to each other and to a test-dedicated pin for inputting a test signal. It is what

Here, the "other input terminal of the exclusive OR circuit" and the "test-dedicated pin" may be directly connected to each other, but the connection is not limited to this, for example, via a buffer circuit or the like. Of course, it may be done.

[0013]

In the exclusive OR circuit (EOR circuit), as shown in FIG. 1, one of the two inputs T and A is at H level ('
1 '), the output is'1' when the other is L level ('0'), and the output is' 0 'when the two inputs T and A are both' 1 'or both' 0 '. This is a logic circuit. If we change the way of looking at this, if one input T is fixed at "0", the other input A is output as it is, and if one input T is fixed at "1", the other input A is inverted. Is output.

Further, one of the L level ('0') and H level ('1') signals is always output from the internal circuit side to each output buffer circuit side. The present invention has been completed by paying attention to this point, and includes each EOR circuit between an internal circuit and each output buffer circuit,
The output terminal of each EOR circuit is connected to the input terminal of each output buffer circuit, one input terminal of each EOR circuit is connected to an internal circuit, and the other input terminal of each EOR circuit is connected to each other and tested. Since it is connected to the dedicated pin, the L level and H level signals output from the internal circuit are output as they are by applying the L level and H level signals to this one test dedicated pin in sequence, or from the internal circuit. The output signal is inverted and output,
As a result, both the H level signal and the L level signal are sequentially output from each output pin. Therefore, it is necessary to confirm both the high level output and the low level output of each output buffer circuit. You can

It is needless to say that the EOR circuit and the inverter circuit may be combined to form an ENOR circuit, and the exclusive OR circuit in the present invention includes these EOs.
Both the R circuit and the ENOR circuit are included.

[0016]

EXAMPLES Examples of the present invention will be described below. FIG. 2 is a diagram showing a test facilitation circuit according to an embodiment of the present invention. In this figure, the elements corresponding to the elements of the conventional example (see FIG. 5) described above are denoted by the same numbers as those given in FIG. 5, and description thereof is omitted.

In the test facilitating circuit 20 shown in FIG. 2, each EO corresponds to each output buffer circuit 12A, 12B ,.
R circuits 21A, 21B ... Are provided. The output terminal of each EOR circuit 21A, 21B ...
2A, 12B, ..., One of the input terminals of each EOR circuit 21A, 21B, ... Is connected to the internal circuit 10, and the other of the input terminals of each EOR circuit 21A, 21B ,. Are connected to each other and to the test-dedicated pin 22 via the buffer circuit 22A.

FIG. 3 is a timing chart of the circuit shown in FIG. From the internal circuit 10 to each EOR circuit 21A, 2
When the signals A1 ('0') and A2 ('1') are input to 1B, respectively, the test-dedicated pin 26 is set to '
When the 0'signal is input, each EOR circuit 21A, 21B
Output signals of the internal pins, that is, the signals appearing at the output pins 11A and 11B, respectively.
It becomes 0'and '1'. Next to this test dedicated pin 26
When the 1'signal is input, the signals appearing at the output pins 11A and 11B are inverted at that time, and the signals are "1" and "1", respectively.
It becomes 0 '. In this way, by sequentially inputting both the "0" signal and the "1" signal to the test-dedicated pin 26, both the "1" signal and the "0" signal are input to the output pins 11A, 11B ,. Since the signals sequentially appear, it is possible to confirm whether the voltage values of both the high level signal and the low level signal of each output buffer circuit 12A, 12B, ... Are good or bad. In order to perform normal operation in the embodiment shown in this figure, a "0" signal may be input to the test-dedicated pin 26, and specifically, the test-dedicated pin 26 may be grounded.

In the semiconductor circuit incorporating the test facilitation circuit shown in FIG. 2, output buffer circuits 12A and 12A are provided.
When testing B, ..., Output pins 11A, 11B ...
It is preferable to check whether or not the voltage value is within a predetermined range after applying a predetermined load to the. The test load circuit connected to the output pins 11A, 11B, ... During this test is not limited to a particular load circuit, but as an example, the dynamic load circuit shown in FIG. 4 can be used.

In FIG. 4, Iol and Ioh are current sources for low level and high level, Vt is a threshold voltage source for level check, and D is a diode bridge. In the dynamic load circuit 30, the output values of the output buffer circuits 12A, 12B, ... Are the threshold voltage V.
If the high level exceeds t, the output buffer circuit 12A,
.. from the current source Iol to the output buffer circuits 12A, 12B, .. As a result, current flows from the current source Iol to the output buffer circuits 12A, 12B ,. It acts as a load on the output buffer circuits 12A, 12B, .... The magnitude of this load is adjusted by changing the current values of the current sources Ioh and Iol.

The output signals of the output buffer circuits 12A, 12B, ... Are input to the judgment circuit 32 in a state in which the dynamic load circuit 30 is loaded as described above. The determination circuit 32 includes an output buffer circuit 12A,
Each output voltage of 12B, ...
It is a circuit composed of, for example, a window comparator for determining that the voltage is not within 1.5 V. In this judgment circuit 32, the output buffer circuits 12A, 12B, ...
Of the output buffer circuits 12A, 12B, ... When the output voltage of the output voltage exceeds a predetermined high voltage (for example, 4.5V) when the output voltage is high, and is below a predetermined low voltage (for example, 1.5V) when the output voltage is low. Is considered normal, while
If the output voltage of the output buffer circuits 12A, 12B, ... Is within the above predetermined voltage range (for example, 45V to 1.5V), it is determined to be abnormal.

As described above, the output pins 11A, 11
A load circuit is connected to B, ... And output pins 11A, 11B ,.
The output buffer circuits 12A, 12B, ... Are tested normally by monitoring the voltage value appearing at. The EOR circuit 21A shown in FIG.
2B, ... Instead of these EOR circuits 21A, 21B,
An ENOR circuit in which an inverter is connected to the output side of ... May be provided. In this case, test pin 22 is "1"
The signals A1, A2, ... Output from the internal circuit 10 when the signals are input are output pins 11A, 11B ,.
, And the signals A1, A2, ... Output from the internal circuit 10 when a “0” signal is input to the test-dedicated pin 22.
Are inverted and appear on the output pins 11A, 11B, ....

[0023]

As described above, in the test facilitation circuit of the present invention, the E-circuit is provided between the internal circuit and each output buffer circuit.
An OR circuit (including an ENOR circuit) is provided, the output terminal of each EOR circuit is connected to the input terminal of each output buffer circuit, and one of the input terminals of each EOR circuit is connected to an internal circuit, and each EOR circuit is connected. Since the other input terminals are connected to each other and to the test-dedicated pins, only one test-dedicated pin is required, and the number of test-dedicated pins is small, so more signals can be exchanged between the internal circuit and the outside. You will be able to use the pin for this.

[Brief description of drawings]

FIG. 1 is a diagram showing a truth table of an EOR circuit.

FIG. 2 is a diagram showing a test facilitation circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart of the circuit shown in FIG.

FIG. 4 is a diagram showing a dynamic load circuit as a load circuit connected to an output pin.

FIG. 5 is a diagram showing an example of a conventional test facilitation circuit.

[Explanation of symbols]

 10 Internal circuit 11A, 11B, ... Output pin 12A, 12B, ... Output buffer circuit 14A, 14B, ... 2 input multiplexer 20 Test facilitation circuit 21A, 21B, ... EOR circuit 22 Test dedicated pin 22A Buffer circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication H01L 21/66 E 7013-4M F 7013-4M H03K 19/00 B 6959-5J 9169-4M H01L 21 / 82 P

Claims (1)

Claims: What is claimed is: 1. A test facilitation circuit for facilitating a test of an output buffer circuit which constitutes a semiconductor integrated circuit, wherein a test facilitation circuit is provided between an internal circuit of the semiconductor integrated circuit and each output buffer circuit. An exclusive OR circuit is provided, an output terminal of each exclusive OR circuit is connected to an input terminal of each output buffer circuit, and one input terminal of each exclusive OR circuit is connected to the internal circuit. A test facilitating circuit in which the other input terminals of the exclusive OR circuits are connected to each other and to a test-dedicated pin for inputting a test signal.