JPH0529327A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form, with good controllability, an emitter layer 4 provided with a shal1ow and steep concentration profile and to form an emitter provided with a low poly-Si resistance in a method of manufacturing the emitter of a bipolar transistor which uses a poly-Si layer for the emitter electrode. CONSTITUTION:In a semiconductor substrate 1 wherein an opening part 6 is formed in the formation region of an emitter diffusion layer 11 and an emitter poly-Si film 7 is formed so as to cover the opening part 6, As impurities are introduced into the emitter poly-Si film 7, the semiconductor substrate 1 is heat-treated, As inside the emitter poly-Si film 7 is diffused into the semiconductor substrate 1 and an emitter diffusion layer 11 is formed in the semiconductor substrate 1. In succession, P impurities are introduced into the emitter poly-Si film 7, the semiconductor substrate 1 is heat-treated at a low temperature at which a transistor characteristic is not changed, P inside the emitter poly-Si film 7 is activated and the resistance of the emitter poly-Si film 7 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to polycrystalline silicon (polysilicon).
The present invention relates to a method for manufacturing an emitter of a bipolar transistor using a Si) layer as an emitter electrode.

With the demand for advanced information processing in recent years, there has been a demand for the development of computers capable of faster information processing and the development of communications using electromagnetic waves of shorter wavelength.
To meet these demands, it is necessary to develop higher-speed transistors.

[0003]

2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 31 is a silicon (Si) substrate, 32 is a buried diffusion layer, 33 is an epitaxial layer, and 34 is field silicon dioxide (SiO ₂ ).
Film, 35 is a base poly-Si film, 36 is a cover SiO ₂ film, 37 is a sidewall SiO ₂ film, 38 is an emitter poly-Si film, 39 is an external base diffusion layer, 40 is an internal base diffusion layer, 41 is an emitter diffusion layer. is there.

FIG. 3 shows a cross-sectional structure of a conventional Self-Align type bipolar transistor. The feature of this transistor is that an emitter poly-Si film 38 is formed in a region including an emitter opening, and an impurity that is usually introduced by an ion implantation method is heat-treated in the epitaxial poly-33 film 38 in the epitaxial layer 33. This is the point where the emitter diffusion layer 41 is formed by diffusion.

In the case of an npn bipolar transistor, phosphorus (P) or arsenic (As) is used as an impurity to be introduced into the emitter poly-Si film 38, and is introduced into the emitter poly-Si film 38 by an ion implantation method. It is common to do.

Either P or As may be used, but it is known that the use of As gives better characteristics as a bipolar transistor than the use of P. This reason is based on the following two reasons.

First, in a bipolar transistor, the base diffusion layer 40 has an emitter diffusion layer of opposite conductivity type.
It is necessary to form 41. When P is used as the impurity for forming the emitter diffusion layer 41, when the emitter diffusion layer 41 extends into the base diffusion layer 40, the base diffusion layer 40 is pushed out accordingly, and as a result, However, it becomes difficult to form the shallow base diffusion layer 40 having a steep concentration distribution.

In this respect, when the emitter diffusion layer 41 is formed by As, if the conditions are set so that the As concentration is about 10 ²⁰ to 10 ²¹ , the "base extrusion effect" that pushes out the base diffusion layer 40 is obtained. The "base pull-in effect" of pulling in the base diffusion layer 40 is just balanced, and the emitter diffusion layer 41 is made into the base diffusion layer.
Even if formed in 40, the depth of the base diffusion layer 40 does not change,
As a result, it becomes possible to form the shallow base diffusion layer 40 having a sharp concentration distribution.

The width of the base diffusion layer 40 is an essential parameter for increasing the speed of the bipolar transistor, and it is necessary to make it shallow and narrow. For this reason, As is preferable to P as an impurity for forming the emitter diffusion layer 41.

Secondly, since As has a smaller diffusion coefficient and a steeper impurity profile than P, it is easy to realize the internal base layer 40 having a narrow base width in the base diffusion region. In order to increase the speed of the bipolar transistor, it is essential to reduce the parasitic resistance of the emitter, but for this purpose, the existence of a natural oxide film formed at the interface between the poly-Si film and the semiconductor substrate becomes a problem.

As means for breaking the natural oxide film, 1050
There is a method of performing high-temperature short-time annealing at ℃ or higher. However, in forming the emitter diffusion layer 41 using P, since the diffusion coefficient of P is large and the diffusion of P is fast, the shallow base diffusion layer 40 is formed.
It is difficult to form a shallow emitter diffusion layer 41 corresponding to the above with good controllability.

On the other hand, an emitter diffusion layer using As
In the formation of 41, the diffusion coefficient of As is small and the diffusion of As is slow, so that the shallow emitter diffusion layer 41 can be formed with good controllability even by high-temperature short-time heat treatment at about 1050 ° C.

[0013]

[Problems to be Solved by the Invention] As described above,
When As is used to form the emitter, a shallow and narrow base diffusion layer
While it has the advantage that 40 can be formed with good reproducibility, the resistance of the emitter poly-Si film 38 becomes higher than that of P, and the parasitic resistance of the emitter cannot be lowered.

As a result, there is a problem that it is difficult to increase the speed. Accelerating voltage of 20k
Implanted under conditions of eV and dose of 1x10 ¹⁶ / cm ² , 30 at 1,100 ℃
Second diffusion and activation annealing (heat treatment for emitter formation)
Sheet resistance of the emitter poly-Si film 38 is about 1
In contrast to 80 Ω / □, the ion implantation method using As has a high sheet resistance of about 270 Ω / □ when implanted under the conditions of an acceleration voltage of 40 keV and a dose of 1 × 10 ¹⁶ / cm ^2. In terms of the parasitic resistance of the emitter, P is more advantageous than As.

As another method for reducing the emitter resistance, there is a method of filling the upper portion of the emitter poly Si film 38 with tungsten (W) or the like.
Since the resistance of the emitter itself has not been lowered, it is necessary to lower the resistance of the emitter poly-Si film 38 itself in order to further reduce the emitter resistance.

Therefore, a method for forming an emitter diffusion layer having a shallow and steep concentration profile by using As with good controllability and having a low poly-Si resistance comparable to that when using P is desired.

The present invention is provided for the purpose of obtaining means for solving the above problems.

[0018]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 4 is a heat treatment temperature dependence of an emitter poly-Si film sheet resistance, and FIG. 5 is a heat treatment temperature dependence of a current amplification factor (h _FE ). is there.

In the figure, 1 is a semiconductor substrate, 2 is a field SiO ₂ film, 3 is a base poly-Si film, 4 is a cover SiO ₂ film,
5 is a side wall SiO ₂ film, 6 is an opening, 7 is an emitter poly-Si film, 8 is an arsenic ion, 9 is an external base diffusion layer, 10
Is an internal base diffusion layer, 11 is an emitter diffusion layer, and 12 is a P ion.

In order to solve the above problems, the following means are performed in the order of steps. 1) Introduce As impurities into the emitter poly-Si film. (For example, an ion implantation method is used.) 2) The emitter diffusion layer is formed by heat treatment to obtain a predetermined bipolar transistor characteristic. 3) Introduce P impurities into the emitter poly-Si film. (For example, the ion implantation method is used.) 4) The heat treatment at less than 800 ° C activates the impurities in the emitter poly-Si film to reduce the resistance of the emitter poly-Si film.

FIG. 4 shows the heat treatment temperature dependence of the sheet resistance of the emitter poly-Si film. As shown in Fig. 4, an acceleration voltage was applied to the emitter poly-Si film 38 which had already been implanted with 1 × 10 ¹⁶ As ions.
P-ion is implanted with varying dose amount at 20keV, 650-90
This is a plot in which the temperature of the low temperature heat treatment (30 minutes) at 0 ° C is plotted on the horizontal axis and the sheet resistance value of the emitter poly-Si film 38 is plotted on the vertical axis.

In the heat treatment temperature range between 650 ° C. and 750 ° C.,
While the sheet resistance decreases sharply as the heat treatment temperature increases, in the heat treatment temperature range between 750 and 900 ° C, the change in sheet resistance with respect to the change in heat treatment temperature is gentle, and even if the heat treatment temperature is increased, For that reason, it cannot be expected that the sheet resistance will decrease.

On the other hand, according to FIG. 5, at a temperature of 750 ° C. or lower, the current amplification factor, which is one of the transistor characteristics, hardly changes as compared with the case where no heat treatment is performed.
At temperatures above ℃, it begins to drop sharply.

It is almost impossible to control the current amplification factor to be constant in the temperature region where the characteristics change rapidly, and the decrease of the current amplification factor means that the base layer is expanded by heat treatment. Since it makes the formation of a shallow base layer difficult, it hinders the formation of high-speed transistors.

Here, the current amplification factor is described as an example of one of the transistor characteristics, but the same applies to other transistor characteristics such as other collector-emitter breakdown voltage and emitter-base breakdown voltage.

Therefore, in order to reduce the sheet resistance and maintain the transistor characteristics at the same time, 650 ° C or higher and 800 ° C or higher are required.
It can be seen that temperatures below are optimal. In other words, at temperatures above 800 ° C, it is not possible to expect a reduction in sheet resistance, and
This is because the transistor characteristics are significantly changed.

That is, the object of the present invention is to form the emitter diffusion layer 11
In the semiconductor substrate 1 for the bipolar transistor in which the opening 6 is provided in the formation region of the bipolar transistor, and the poly-Si layer having the emitter poly-Si film 7 covering the opening 6 is used as the emitter electrode, FIG. As shown in, the emitter poly-Si film 7
The step of introducing As impurity 8 into the inside of the semiconductor substrate 1 and the semiconductor substrate 1 are heat treated as shown in FIG.
A step of diffusing As in the film 7 into the semiconductor substrate 1 to form an emitter diffusion layer 11 in the semiconductor substrate 1; and as shown in FIG. As shown in FIG. 1D, the semiconductor substrate 1 is heat-treated at a temperature low enough not to change the transistor characteristics to activate P in the poly-Si film 7, And a step of reducing the resistance of the emitter poly-Si film 7.

[0028]

In the present invention, by the method described above,
It is possible to solve the two problems at once by forming a shallow and steep emitter diffusion layer and reducing the emitter poly-Si resistance.

[0029]

FIG. 2 is a schematic sectional view in order of the steps of an embodiment of the present invention. In the figure, 13 is the Si substrate, 14 is the buried diffusion layer, and 15 is
Is an epitaxial layer, 16 is a field SiO ₂ film, 17 is a contact diffusion layer, 18 is a base poly-Si film, 19 is a cover SiO 2.
₂ film, 20 is opening, 21 is sidewall SiO ₂ film, 22 is emitter poly-Si film, 23 is As ion, 24 is external base diffusion layer, 25 is internal base diffusion layer, 26 is emitter diffusion layer, 27 is P ion, 28 is an emitter Al electrode, 29 is a base Al electrode, 30
Is a collector Al electrode.

An embodiment of the present invention will be described in order from the process after forming the opening 20 in the emitter formation region and forming the emitter poly-Si film 22 on the opening 20, which is the essence of the present invention.

FIG. 2A shows a state in which the opening 20 is provided in the emitter formation region surrounded by the sidewall SiO ₂ film 21. As shown in FIG. 2B, the emitter poly-Si film 22
Is coated on the epitaxial layer 15 at a thickness of 1,000 Å at 650 ° C by the CVD method and patterned to the emitter contact electrode.

Then, arsenic ions are formed by an ion implantation method.
(As ⁺ ) is injected into the emitter poly-Si film 22 under the conditions of an acceleration voltage of 40 keV and a dose amount of 1 × 10 ¹⁶ / cm ² . This ion implantation may be performed on the entire surface of the emitter poly-Si film 22 before patterning.

As shown in FIG. 2 (c), 30 at 1100 ° C
Second activation heat treatment is performed. As a result, the base poly-Si film
The impurities in 18 are diffused into the epitaxial layer to form the external base diffusion layer 24, and the B injected into the epitaxial layer 15 through the opening 20 in advance is activated to form the internal base diffusion layer 25. At the same time, the As in the emitter poly-Si film
Diffuse to form an emitter diffusion layer 26.

Again, as shown in FIG. 2D, phosphorus ions (P ⁺ ) are implanted by an ion implantation method under the conditions of an acceleration voltage of 20 keV and a dose amount of 1 × 10 ¹⁶ / cm ² . As shown in Fig. 2 (e), the emitter poly-Si
By activating P in the film, the resistance of the emitter poly-Si film 22 is reduced.

As shown in FIG. 2F, the cover SiO ₂ film 19 is formed.
An electrode window is opened in the substrate, the Al film is coated by the sputtering method, and patterning is performed to form the Al electrodes 28, 29, 30 of the emitter, base, and collector to form a two-layer poly-Si self-aligned bipolar transistor. ..

Although the emitter poly-Si film 22 is used here, amorphous Si may be used when it is formed. However,
It is converted into poly-Si by the subsequent heat treatment. Although the self-aligned bipolar transistor is shown here, it can be formed in other non-self-aligned bipolar transistors.

[0037]

As described above, according to the present invention,
In addition to being able to form a shallow and steep emitter diffusion layer, the resistance of the poly-Si film for the emitter electrode can be reduced, which greatly contributes to the speedup of the self-aligned bipolar transistor.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a schematic cross-sectional view in order of the processes of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

FIG. 4 Heat treatment temperature dependence of emitter poly-Si film sheet resistance

FIG. 5 Dependence of current amplification factor (h _FE ) on heat treatment temperature

[Explanation of symbols]

1 Semiconductor Substrate 2 Field SiO ₂ Film 3 Base Poly Si Film 4 Cover SiO ₂ Film 5 Sidewall SiO ₂ Film 6 Opening 7 Emitter Poly Si Film 8 Arsenic Ion 9 External Base Diffusion Layer 10 Internal Base Diffusion Layer 11 Emitter Diffusion Layer 12 P Ion 13 Si substrate 14 Buried diffusion layer 15 Epitaxial layer 16 Field SiO ₂ film 17 Contact diffusion layer 18 Base poly Si film 19 Cover SiO ₂ film 20 Opening 21 Sidewall SiO ₂ film 22 Emitter poly Si film 23 As Ion 24 External base diffusion Layer 25 Internal base diffusion layer 26 Emitter diffusion layer 27 P ion 28 Emitter Al electrode 29 Base Al electrode 30 Collector Al electrode

Claims (1)

Claims: 1. An opening is formed in a region where an emitter diffusion layer (11) is formed.
(6) is provided, and a semiconductor substrate for a bipolar transistor which uses a polycrystalline silicon layer for forming an emitter polycrystalline silicon film (7) covering the opening (6) as an emitter electrode
In (1), a step of introducing arsenic impurities (8) into the emitter polycrystalline silicon film (7), and then heat treating the semiconductor substrate (1) to Arsenic in the semiconductor substrate (1) is diffused to form an emitter diffusion layer (11) in the semiconductor substrate (1), and further, a phosphorus impurity (1) is formed in the emitter polycrystalline silicon film (7).
2) is introduced, and then the semiconductor substrate (1) is heat-treated at a temperature low enough not to change the transistor characteristics to activate phosphorus in the emitter polycrystalline silicon film (7), And a step of reducing the resistance of the emitter polycrystalline silicon film (7).