JPH05292322A - Picture reader - Google Patents

Abstract

PURPOSE:To attain high speed read and to reduce a chip area in the case of circuit integration by rounding-off dispersion error data dispersed to surrounding picture elements so as to reduce the scale of a data generating means. CONSTITUTION:An error data e/2 shifted by one bit from a latch circuit 5 resulting from error data (e) detected by an error detection circuit 3 is dispersed to a succeeding picture element. Moreover, data e/8 shifted by 3 bits are latched by a latch circuit 21 and inputted to an adder 22 and simultaneously data e/4 are inputted thereto. Furthermore, error data e-1 at the 1st decimal place are fed to a carry terminal of the adder 22 and a carry-in terminal CY 22a. That is, error data having been thrown away in a conventional reader are rounded off and the result is fed to the adder 22. The sum error data in the adder 22 is added to the data e/8 at an adder 24 via a latch circuit 23 and the result becomes data e/2, which are stored in a RAM 7. The error data are dispersed to a succeeding line picture element. Thus, a dispersion error data generating adder is saved and high speed arithmetic operation processing is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus for photoelectrically converting image information as optical information and generating image data from an obtained electric signal.

[0002]

2. Description of the Related Art In this type of image reading apparatus, a solid-state image pickup device such as a CCD is used to convert optical information into an electric signal,
The obtained analog signal is binarized to generate a digital image signal. However, in this case, when an image is displayed, the screen becomes rough and unsightly due to the influence of quantization noise due to binarization and other noises. In order to avoid this, a method has been adopted in which the error of an arbitrary pixel is dispersed to neighboring pixels adjacent to the pixel to visually reduce the noise on the screen.

FIG. 2 is a diagram showing a state of a conventional example in which an error is dispersed. (I-1), i, and (i + 1) show pixel positions in the main scanning direction (x coordinate direction). (J-
1) and j indicate the position of the line in the sub-scanning direction (the y-coordinate direction). Based on this FIG. 2, x = i, y =
Regarding the pixel P _{ij of} j (hatched portion in the figure), the variance of the error will be described.

FIG. 2A shows an error e generated in the pixel P _ij.
Is emitted to peripheral pixels and dispersed. Although e / 2 is distributed to the next pixel on the same line as the pixel P _ij , this distribution is performed in real time. On the other hand, the peripheral pixels of the next line (y = j + 1) are stored in a memory that stores at least one line, and are dispersed when the image data of the next line is input. In this case,
E / 4 is distributed to the same pixel on the next line and e / 8 is distributed to the next pixel on the next line. However, in order to reduce the error due to bit shift in the previous pixel on the next line,
Disperse _r .

E _r = e- (e / 8 + e / 4 + e / 8) FIG. 2 (b) shows how the pixel P _ij receives an error emitted from another pixel. As shown in this figure, e / 8 is received from the previous pixel of the previous line, e / 4 is received from the same pixel of the previous line, and e _r is received from the next pixel of the previous line from the memory, and the same. Receive e / 2 from the previous pixel of the line in real time.

FIG. 3 is a block diagram for embodying the above-mentioned error distribution method. In FIG. 7, 1 is an input terminal to which image data is supplied, and 2 is an adder that takes the image data from the input terminal 1 as one input and adds it to the data at the other input (which will be described later). Reference numeral 3 is an error detection circuit as an error detection means for detecting the error e from the output of the adder 2 and binarizing the image data. 4 is 2
It is an output terminal for outputting the binarized image data. Reference numeral 5 holds the error e from the error detection circuit 3 and shifts it to shift error data e / 2, e / 4, e / 8.
Is a latch circuit as a data shift means for outputting. However, in an actual circuit, this latch circuit always outputs the error data, and the side that receives the shift error data selects the necessary bit data and performs the shift operation.

Reference numeral 6 denotes a distributed data generation circuit for generating distributed error data dispersedly added to the image data of the next line and converting it to error data to be stored in the 8-bit RAM. Reference numeral 7 is a RAM as a storage means for storing the converted error data. Numeral 8 adds the error data stored in the RAM 7 and the shifted error e / 2 from the latch circuit 5, and outputs the addition output by the adder 2 described above.
It is an adder which takes the data of the other input of.

The distributed data generating circuit 6 is composed of adders 11 and 12, an inverting circuit (inverter) 13, an adder 14, a latch circuit 15, an adder 16, a latch circuit 17 and an adder 18.

Next, the operation of the conventional configuration shown in FIG. 3 will be described. The error data detected by the error detection circuit 3 is
It is composed of a code part and a data part, and its data format is shown in FIG. As shown in FIG. 4, the detected error data e is the B ₁₁ and MSB, the B ₀ have a 12-bit to LSB, symbol S of B _11, from B ₁₀ B ₂
9-bit integer part e ₈ to e ₀ , B ₁ and 2 of B ₀
It is composed of a small number of bits e _-1 and e _-2 . Code S
Is 0 for positive and 1 for negative. FIG. 5 shows the binary (binary) and decimal (dec) of this error data.
imal), hexadecimal (hex) and error magnitude (si
It is a figure which respectively contrasts ze). In FIG. 5, the positive / negative relationship of the error data is a two's complement relationship in hexadecimal (binary).

This error data e is e / 2 shifted by 1 bit and dispersed in real time to the next pixel. At the same time, the e / 2 is supplied to the adder 11 together with the e / 4 shifted by 2 bits, and is supplied to one input of the adder 12 as (e / 2e + e / 4e) and to the other input. It is added with e / 8 of bit shift. The addition result (e / 2 + e / 4 + e / 8) is output from the adder 12 and the sign is inverted by the inversion circuit 13 − (e / 2
+ E / 4 + e / 8) is supplied to one input of the adder 14. The error data e is supplied to the other input as it is, and e _r is calculated to reduce the bit shift error.

The e _r obtained by this operation is held in the latch circuit 15 and then supplied to one input of the adder 16. Then, it is added to e / 4 supplied to the other input, further added to e / 8 via the latch circuit 17, and then added to e / 8.
After a / 2, point or more 7-bit truncating the fractional part _{(e 6, e 5, ...} , e 0) and the 8-bit configuration code S, and stores it in the RAM 7. This stored 8
The bit error data is distributed to the pixels of the next line.

FIG. 6 shows the format of 8-bit error data stored in the RAM 7. Further, FIG. 7 shows the binary data and the decimal data (de) of the 8-bit error data.
Cimal), hexadecimal (hex) and error magnitude (s
It is a figure which contrasts each size.

As described above, also in the conventional image reading apparatus, the noise of the displayed image can be made inconspicuous by dispersing the error of any pixel to the pixels around the pixel.

[0014]

However, in the above-mentioned conventional example, a large number of circuits are required to reduce the error due to bit shift. Especially 1 per circuit
Not only is the adder of multiple gates from 20 to 180 difficult to follow a high speed read operation,
However, there is a problem in that the chip area becomes large and the cost is increased to make C.

The present invention solves the above-mentioned conventional problems and provides an image reading apparatus which enables a high-speed reading operation and can reduce the chip area when the number of gates of the circuit is reduced to form an IC. The purpose is to provide.

[0016]

In order to achieve the above object, the present invention detects an error contained in an arbitrary pixel of input image data and outputs the error as a plurality of bits of error data including a sign bit. Detecting means, data shift means for generating shift error data by bit-shifting the error data, and computing the error data and the shift error data to generate distributed error data dispersed in pixels around the arbitrary pixel. A dispersion error generating means is provided, and the dispersion error generating means is configured to use a rounding means for an operation for obtaining the dispersion error data.

[0017]

Therefore, according to the present invention, in the process of the calculation for generating the dispersion error data from the detected error data, the calculation result is rounded to obtain the dispersion error data, so that many calculation circuits are required. In addition, the high-speed reading operation can be performed, and at the same time, the chip area can be reduced when the circuit is integrated into an IC.

[0018]

Embodiments of the present invention will be described below with reference to FIG.

In FIG. 1, reference numeral 9 is a distributed data generating circuit as a data generating means. The configuration other than the distributed data generation circuit 9 is the same as that of FIG. 3 and is denoted by the same reference numeral, and the description thereof is omitted. This distributed data generation circuit 9
Is composed of a latch circuit 21, an adder 22, a latch circuit 23, and an adder circuit 24.

Next, the operation of the configuration shown in FIG. 1 will be described. Error data e which is detected by the error detecting circuit 3, as in the conventional example, as shown in FIG. 4, the B ₁₁ and MSB, B
_It has 12 bits, where ₀ is the LSB, and the 9-bit integer parts e ₈ to e ₀ of the codes S and B ₁₀ to B ₂ of B ₁₁ .
It is composed of two-bit decimal parts e _-1 and e _-2 of B ₁ and B ₀ . The sign S is 0 when it is positive and 1 when it is negative.
Becomes

This error data e is 1 from the latch circuits 5 to 1.
The bit-shifted e / 2 is distributed to the next pixel in real time. Also, after the e / 8 shifted by 3 bits from the latch circuit 5 is held by the latch circuit 21, the adder 2
2 is supplied to one input, and the other input is supplied with e / 4 shifted by 2 bits. Further, in this case, the error data e _{−1 at} the first decimal place of the error data is the adder 22.
Is supplied to the carry-in terminal CY22a, which is a carry input terminal. That is, the error data, which has been conventionally rounded down, is rounded off and added to the addition operation.

The error data added by the adder 22 is further added with e / 8 by the adder 24 via the latch circuit 23 to be e / 2, and then 7 bits (e ₆ , e ₅ ,
, E ₀ ) and the code S have an 8-bit structure, which is RA
Store in M7. The stored error data is distributed to the pixels on the next line.

Therefore, as compared with the conventional distributed data generation circuit, the adder used to generate the distributed error data can be significantly reduced, and the propagation time of the distributed data generation circuit can be shortened. By enabling
It is possible to realize a high-speed reading operation, reduce the circuit scale, and realize an inexpensive IC having a small chip area.

[0024]

As is apparent from the above-described embodiment, the present invention arithmetically processes error data detected from an arbitrary pixel of image data to generate distributed error data dispersed in peripheral pixels of the pixel. By using a means for rounding off the error data as the data generating means, the circuit scale of the data generating means is greatly reduced to enable a high-speed reading operation, and at the same time, when the circuit is integrated into an IC, the chip area is reduced. The effect of realizing a small and inexpensive IC can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a part of an embodiment of an image reading apparatus according to the present invention.

FIG. 2A is a diagram showing how an error of an arbitrary pixel is dispersed to the peripheral pixels. FIG. 7B is a diagram showing a manner of receiving dispersed errors from peripheral pixels.

FIG. 3 is a schematic block diagram of a part of a conventional image reading device.

FIG. 4 is a diagram showing a data format of error data.

5 is a binary, decimal, 16 of error data in FIG.
It is a figure which shows the contrast of the advance and the magnitude of an error.

FIG. 6 is a diagram showing a data format of distributed error data stored in a RAM that is a storage unit.

7 is a binary, decimal, 16 of error data in FIG.
It is a figure which shows the contrast of the advance and the magnitude of an error.

[Explanation of symbols]

 1 Input Terminals 2,8,22,24 Adder 3 Error Detection Circuit 4 Output Terminals 5,21,23 Latch Circuit 7 RAM 9 Distributed Data Generation Circuit

Claims (1)

[Claims] 1. An error detecting means for detecting an error contained in an arbitrary pixel of input image data and transmitting the error as a plurality of bits of error data including a sign bit, and a shift error data obtained by bit-shifting the error data. Data shift means for generating, and data generation means for calculating the error data and the shift error data to generate distributed error data to be distributed to pixels around the arbitrary pixel, wherein the data generating means is the dispersion An image reading apparatus characterized in that rounding means is used for calculation for obtaining error data.