JP3093492B2 - Encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding device for encoding input data.

[0002]

2. Description of the Related Art Conventionally, arithmetic encoders are based on ISO / IEC.
As described in (Committee Draft 11544 and the like), the operation performed between an A (agent: section) register and a C (mode: code) register differs between encoding and decoding, and will be described below. The processing is performed in such a configuration.

[0003] The ISO / IEC (Committe)
e Draft 11544), a conventional configuration for realizing the processing will be described with reference to FIGS. 2 and 3. FIG.

In FIG. 2, reference numeral 1 denotes an A (agent: section) register, 5 denotes a C (mode: sign) register, 2 denotes an adder for adding the values of the A and C registers, and 3 denotes an adder. A subtractor subtracts the value of the A register from the value of the C register. Reference numeral 4 denotes a multiplexer that selects the H side during encoding and the L side during decoding.

In performing each process, the bit configuration of the C register is as shown in FIG. 3, and the description will be made assuming that the A register is composed of 16-bit data.

At the time of encoding, an operation of (A register) + (C register) is required, and the value of the A register is
It must be added to the φth to 15th Xs counted from the LSB side in the bit configuration of the C register in (a). The operation will be described with reference to FIG. The upper 16 bits of the C register are CHIGH and the lower 16 bits are C
When LOW, the output of one A register and CHIG
The purpose can be achieved by adding 32-bit data composed of H and CLOW by an adder of 2, selecting an output of the adder by a multiplexer of 4, and writing again to a C register of 5. When decoding, (CHIGH)-(A
Register) is required, and the value of the A register is
It must be subtracted from the 16th to 31st X in (b). The operation will be described with reference to FIG. The purpose is achieved by subtracting the value of the A register from CHIGH by a subtractor of 3, and selecting its output and 32-bit data composed of CLOW by a 4 multiplexer, and writing it again to the 5 C register.

[0007]

However, the above-mentioned conventional example has a drawback that an adder and a subtractor are required and hardware is increased.

Accordingly, an object of the present invention is to simplify such a circuit configuration.

[0009]

In order to solve the above-mentioned problems, an image processing apparatus according to the present invention comprises a coding circuit for performing arithmetic coding, a code register, a section register, means for shifting the output of the section register, An inverting circuit for bit-inverting the shift output, a section register and a multiplexer for selecting the output of the inverting circuit during encoding or decoding, an adder for adding the multiplexer output and the sign register output, and a digit of the adder. It is characterized in that the uplink input is controlled depending on whether encoding or decoding is performed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following embodiments of the present invention, means for shifting and inverting the output of a section register is provided so that addition and subtraction can be performed with a single adder.

FIG. 1 is a diagram most clearly showing the features of the present invention. In FIG. 1, 1 is an A register, 2 is an adder,
Is a multiplexer, 5 is a C register, 6 is a shifter, and 7 is an inverter.

The detailed operation will be described below.

At the time of encoding, since the carry input of the adder 2 is "none", the output of the A register
The purpose is achieved by adding the output of the register as it is and writing it again to the C register.

At the time of decoding, the output of the A register is shifted by 16 bits by the shifter of 6, and the bit is inverted by the inverter of 7. The output of 7 is selected by the multiplexer of 4 and input to 2. There is an adder input of 2
, The operation of CHIGH-A can be executed, and the purpose is achieved by writing the output of 2 again to the C register.

The six shifters used in the description of the configuration of the first embodiment are intended to perform digit alignment when performing an operation between a code register and a section register, and the shift operation is realized only by wiring. Needless to say, no logic circuit is required.

[0016]

As described above, by using a common adder / subtractor, the circuit scale can be reduced, the manufacturing cost can be reduced, and high-speed operation can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

FIG. 3 is a diagram showing a bit configuration of a C register.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-53-85629 (JP, A) JP-A-56-2043 (JP, A) JP-A-62-135933 (JP, A) JP-A 63-85933 76525 (JP, A) JP-A-63-314918 (JP, A) JP-A-2-202267 (JP, A) JP-A-4-280517 (JP, A) IEEE TRANSACTIONS ON COMMUNICATION S, VOL. COM-29, no. 6, J UNE 1981, pp 858-867, "Com pression of Black- White Images With Arithmetic Coding", by G.M. G. FIG. Langdon. Jr & J. Rissanen (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 7/40 G06T 9/00 H04N 1/411

Claims (1)

(57) [Claims] 1. An encoding circuit for performing arithmetic encoding, comprising:
A code register, a section register, means for shifting the output of the section register, an inverting circuit for bit-inverting the shift output, a multiplexer for selecting the section register and the inverting circuit output during encoding or decoding, and the multiplexer output. An encoding device comprising an adder for adding an output of a code register, wherein the carry input of the adder is controlled depending on whether encoding or decoding is performed.