CA1301937C - Absolute value calculating circuit having a single adder - Google Patents
Absolute value calculating circuit having a single adderInfo
- Publication number
- CA1301937C CA1301937C CA000590450A CA590450A CA1301937C CA 1301937 C CA1301937 C CA 1301937C CA 000590450 A CA000590450 A CA 000590450A CA 590450 A CA590450 A CA 590450A CA 1301937 C CA1301937 C CA 1301937C
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- Prior art keywords
- result
- bit
- addition result
- output
- inverting
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/544—Indexing scheme relating to group G06F7/544
- G06F2207/5442—Absolute difference
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
An absolute value calculating circuit produces an absolute value of a difference between a first and a second numerical value which have a predetermined bit length and are represented by 2's complement notation.
The circuit comprises first inverting means for inverting the first numerical value to output an inverted numerical value, first adding means for adding the second numerical value to the inverted numerical value to output an addition result, second inverting means for inverting the addition result to output a first calculation result and second adding means for adding 1 to the addition result to output a second calculation result. Selecting means select and deliver as an absolute value of a difference either one of the first and second calculation results by referencing a sign of the addition result.
An absolute value calculating circuit produces an absolute value of a difference between a first and a second numerical value which have a predetermined bit length and are represented by 2's complement notation.
The circuit comprises first inverting means for inverting the first numerical value to output an inverted numerical value, first adding means for adding the second numerical value to the inverted numerical value to output an addition result, second inverting means for inverting the addition result to output a first calculation result and second adding means for adding 1 to the addition result to output a second calculation result. Selecting means select and deliver as an absolute value of a difference either one of the first and second calculation results by referencing a sign of the addition result.
Description
~3~ 37 The present invention relates to a circuit for arithmetic operations and, mor~ particularly, to an a~solute value calculating circuit for producing the absolute value of a difference between two numerical values.
To code video signals, for example, arithme*ic operations are frequently per~ormed for rapidly producing the absolute value o~ a difference between two numerical values. An absolute value calculating circuit (re~erred to simply as the calculating circuit herPinafter~ has been proposed in various forms in order to implement such arithmetic operations~ Most of the prior art calculating circuits are of the type reported by Yamashina et al in a - paper entitled "A Realtime Microprogrammable Video Signal LSI" at IEEE International Solid-State Circuits Conference held at GRAND BAL~ROOM WEST, New York City, on February 26, 1987, SESSION XV: HIGH SPEED SIGNAL P~OCESSORS, THPM 15.3.
A calculating circuit of the type described in this paper has a parallel connection of two adders (or subtractors), and a selector. Assuming two input values a and b, one of the adders produces (a - b) and the other produces (b - a), and the selector selects the value of a result of calculation which is positive. A drawback with this type of calculating circuit is that the use of two adders (or subtractors) makes the construction complicated, adds to the number of circuit elements, requires a substantial area on an integrated circuit, and increase the power consumption.
It is therefore an object of the present invention to provide an absolute value calculating circuit which is simple in construction when compared to the solutions offered by the prior art circuits and operable at a hi~h speed.
In accordance with the present invention, an absolute value calculating circuit for producing an absolute value of a differenc~ between a first and a second numerical value which have a predetermined bit length and are represented by 2's complement notation comprises first ~ , , ~3~ 3~
inverting means for inverting the first numerical value to output an inverted numerical value, first adding means for adding the second numerical value to the inverted numerical value to output a total, second inverting means for inverting the total to output a first calculation result, second adding means for adding 1 to the total, to output a second calculation result, and selecting means for selecting and delivering, as an absolute value of the calculated difference, either one of the first or second calculation results according to the sign of the total.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken with accompanying drawings in which:
Figure 1 illustrates a schematic block diagram of a prior art absolute value calculating circuit;
Figure 2 illustrates a block diagram of an absolute value calculating circuit embodying the present invention, and Figure 3 illustrates a circuit diagram of an embodiment of a plus one circuit included in the calculating circuit of Figure 2.
To better understand the present invention, a brief reference will be made to a prior art calculating : 25 circuit of the type using two adders, shown in Figure 1. In the figure, the calculating cirsuit has a first, second and third input terminal 1, 2 and 5, a first and a second inverter 3 and 4, a first and a second adder 6 and 7, a selector 8, and an output terminal 9. Numerical values (assumed to be a and b) having the same predetermined bit length and represented by 2's complement notation are applied to the first and second input terminals 1 and 2, respectively. The numerical values b and a are inverted to values b and a respectively by the f.irst and second inverters 3 and 4 and then fed to a terminal B of the first adder 6 and a terminal A of the second adder 7. Data "l"
., .., ,~;~.
3~
adapted for carrying is applied to each terminal C of the adders 6 and 7 via the third input terminal 5 o~ the calculating circuit, so that the adders 6 and 7 perform respectively arithmetic operations of (a + b + 1) and (a +
b + 1). Generally, a subtraction of (c - d), where c and d are binary numbers, is replaced with an addition of (c + ~), where ~ is a 2's complement of d. A 2's complement of a given binary number d is equal to a number (d + 1) produced by adding 1 to d which is an inverted version of d. By applying this relationship to the results o~ calculations performed by the adders 6 and 7, it will be seen that the first adder 6 outputs (a + b + 1) = (a + ~) = (a - b) while the second adder 7 outputs (a + b ~ (b - a~, respectively. In this instance, a carry output is not used with the adders ~ and 7. These two results of subtraction are individually fed to terminals X and Y of the selector 8 via terminal~ S of the adders 6 and 7, while the sign bit (most significant bit) of the output (a - b) of the adder 6 is delivered to a select terminal W of the selector 8. When the sign bit is "1", (a - b) is smaller than 0 and, hence, the selector 8 outputs (b - a) which is the output of the adder 7. Conversely, when the sign bit is "0", the selector 8 outputs (a - b).
Referring to Figure 2, a calculating circuit embodying the present invention is shown in a schematic block diagram. As shown, the calculating circuit has a first to a third input terminals lO to 12, a first and a second i.nverter 13 and 16, an adder 14, a +l increment circuit 15 for adding 1 to input data, a selector 17, and an output terminal 18. Two numerical values (assumed to be x and y) having the same bit length and represented by 2's complement notation are individually applied to the input terminals 10 and 11. While the numerical value x i5 directly fed to a terminal A of the adder 14, the numerical value y is inverted by the inverter 13 and then fed to a terminal B of the adder 14. In accordance with the present . . ~.
W~3~
invention, the terminal C of the adder 14 in adders 6 and 7 of Fiyure 1 used to receive a numerical value adapted for carrying via the third input terminal 12, is not used.
Hence, the adder 14 performs an addition of (x -~ y) and produces the result on its terminal S. By adopting the previously discussed principle of 2's complements, y = (y -1) is obtained from y = (y + 1) and, therefore, theaddition result (x + y) of the adder 14 may be expressed as (x - y - 1). The addition result (x - y - 1) is fed to the inventer 16, plus one circuit ~5, and a select terminal W of the selector 17 which responds to a sign bit of the addition result. In response, the inv~rter 16 produces a first calculation result (y - x~ by inverting (x - y - 13. This will be clearly understood because the inverted version (x - y - 1) of (X - y - 1) is equal to {(x - y - 1) - 1} and because (x - y - 1) is equivalent to -(x - y - 1), i.e.
, ~
(x - y - 1) = -(x - y - 1) - 1 = (y - x). It will also be clear that the plus one circuit 15 produces a second calculation result (x - y) because it adds 1 to (x - y - 1).
When the sign bit of (x - y - 1) is "1", (x - y - 1) is smaller than 0 and, therefore, the selector 17 delivers the first calculation result from the inverter 16 via its output terminal Z. Conversely, when the sign bit is "0", the selector 17 feeds the second calculation result ~rom the plus one circuit 15 via the terminal Z.
The operation of the calculating circuit having the above construction will be described by using specific numerical values. Assume that the numerical values x and y applied to the input terminals 10 and 11 are respectively (00112 = 3,~) and 01012 = 5,0~ where the suffixes 2 and 10 show that their associated numbers are a binary number and a decimal number, respectively, and that in each binary number the rightmost bit is the least significant bit (LSB).
Further, let the successive bits beginning with LSB be called the first bit (b,), second bit (b2), and so on. The numerical value y is inverted by the inverter 13 and then , , '7 fed to the adder 14 in the form of y = (10102). In response, the adder 14 performs an addition of x(00112) ~ y(10102) to produce (11012). This output (11012) is routed to the plus one circuit 15 and second in~erter 16, whereby the sum x +
y + 1 (11102) = 3~0) and an inverted x + y (00102 = 2~o) are obtained. On the other hand, th~ fourth bit "l" or the sign bit of the output S (11012) of the adder 14 is applied to the select terminal W of the selector 17, so that the selector 17 selects the output (00102) of the inverter 16 based on "1"
appearing on the select terminal W. Since the present invention determines the sign of the output of the adder 14 on the basis of a sign bit, it ignores a carry output of the adder 14 as in the prior art. The result OO10, i.e. 2 verifies the operation 13 - 5¦ = 2.
Figure 3 shows a specific construction of the "+1"
circuit 15 of the calculating circuit in accordance with the present invention. While a variety of implementations may be contemplated for adding 1 to an input value such as an adder or a counter, the plus one circuit 15 is implemented as a simple combination of logical circuits. The circuit of Figure 3 is assumed to operate an input value having four bits, i.e. 8(10002) to +7(01112). It is to be noted that inputs Il to I4 are associated respectively with LSB (b,) to sign bit (b4) of the input value. Specifically, the "~1"
circuit 15 consists o~ a first inverter 21, a first to a third Exclusive-OR (EXOR) gate 22 to 24, and a first and a second AND gate 25 and 26. When 1 is added to an input va~ue, the first bit b~ of the input value is inverted without exception. Therefore, the first inverter 21 unconditionally inverts the first bit b, to produce an output Rl. On the other hand, carry at the n-th bit bn (n being a natural number and n > 1) occurs when all o~ the bits b, to bnl are 1 due to the addition of 1 to the first bit b, and, hence, whether or not carry to the n-th bit bn from the lower bit occurs can be determined on the result of AND operation of all of the lower bits. The AND gates 25 and 26 are .
~Q~9~3~
adapted to determine respectively whether or not carry to the third bit b~ and carry to the fourth bit b4 occur.
Outputs R2 to R4 are the results of addition of the second to fourth bits b2 to b4 and the carry from the lower bits, respectively. This function is implemented by the EXOR's 22 to 24 which individually receive carry from the lower bits at an input terminal and receive the second to fourth bits b2 to b4 at the other input terminal. Although the specific construction of Figure 3 has been described in relation to a four-bit input value, it will be apparent that a 'l+l"
cir~uit operable with an n-bit input value is obtained by increasing the number of EXOR gates and AND gates.
In summary, it will be seen that the present invention provides an absolute value calculating circuit which needs only a single adder and, yet, is operable at a high speed and therefore contributes a great deal to miniature circuit configuration, power saving and cost reduction.
,~ ~
To code video signals, for example, arithme*ic operations are frequently per~ormed for rapidly producing the absolute value o~ a difference between two numerical values. An absolute value calculating circuit (re~erred to simply as the calculating circuit herPinafter~ has been proposed in various forms in order to implement such arithmetic operations~ Most of the prior art calculating circuits are of the type reported by Yamashina et al in a - paper entitled "A Realtime Microprogrammable Video Signal LSI" at IEEE International Solid-State Circuits Conference held at GRAND BAL~ROOM WEST, New York City, on February 26, 1987, SESSION XV: HIGH SPEED SIGNAL P~OCESSORS, THPM 15.3.
A calculating circuit of the type described in this paper has a parallel connection of two adders (or subtractors), and a selector. Assuming two input values a and b, one of the adders produces (a - b) and the other produces (b - a), and the selector selects the value of a result of calculation which is positive. A drawback with this type of calculating circuit is that the use of two adders (or subtractors) makes the construction complicated, adds to the number of circuit elements, requires a substantial area on an integrated circuit, and increase the power consumption.
It is therefore an object of the present invention to provide an absolute value calculating circuit which is simple in construction when compared to the solutions offered by the prior art circuits and operable at a hi~h speed.
In accordance with the present invention, an absolute value calculating circuit for producing an absolute value of a differenc~ between a first and a second numerical value which have a predetermined bit length and are represented by 2's complement notation comprises first ~ , , ~3~ 3~
inverting means for inverting the first numerical value to output an inverted numerical value, first adding means for adding the second numerical value to the inverted numerical value to output a total, second inverting means for inverting the total to output a first calculation result, second adding means for adding 1 to the total, to output a second calculation result, and selecting means for selecting and delivering, as an absolute value of the calculated difference, either one of the first or second calculation results according to the sign of the total.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken with accompanying drawings in which:
Figure 1 illustrates a schematic block diagram of a prior art absolute value calculating circuit;
Figure 2 illustrates a block diagram of an absolute value calculating circuit embodying the present invention, and Figure 3 illustrates a circuit diagram of an embodiment of a plus one circuit included in the calculating circuit of Figure 2.
To better understand the present invention, a brief reference will be made to a prior art calculating : 25 circuit of the type using two adders, shown in Figure 1. In the figure, the calculating cirsuit has a first, second and third input terminal 1, 2 and 5, a first and a second inverter 3 and 4, a first and a second adder 6 and 7, a selector 8, and an output terminal 9. Numerical values (assumed to be a and b) having the same predetermined bit length and represented by 2's complement notation are applied to the first and second input terminals 1 and 2, respectively. The numerical values b and a are inverted to values b and a respectively by the f.irst and second inverters 3 and 4 and then fed to a terminal B of the first adder 6 and a terminal A of the second adder 7. Data "l"
., .., ,~;~.
3~
adapted for carrying is applied to each terminal C of the adders 6 and 7 via the third input terminal 5 o~ the calculating circuit, so that the adders 6 and 7 perform respectively arithmetic operations of (a + b + 1) and (a +
b + 1). Generally, a subtraction of (c - d), where c and d are binary numbers, is replaced with an addition of (c + ~), where ~ is a 2's complement of d. A 2's complement of a given binary number d is equal to a number (d + 1) produced by adding 1 to d which is an inverted version of d. By applying this relationship to the results o~ calculations performed by the adders 6 and 7, it will be seen that the first adder 6 outputs (a + b + 1) = (a + ~) = (a - b) while the second adder 7 outputs (a + b ~ (b - a~, respectively. In this instance, a carry output is not used with the adders ~ and 7. These two results of subtraction are individually fed to terminals X and Y of the selector 8 via terminal~ S of the adders 6 and 7, while the sign bit (most significant bit) of the output (a - b) of the adder 6 is delivered to a select terminal W of the selector 8. When the sign bit is "1", (a - b) is smaller than 0 and, hence, the selector 8 outputs (b - a) which is the output of the adder 7. Conversely, when the sign bit is "0", the selector 8 outputs (a - b).
Referring to Figure 2, a calculating circuit embodying the present invention is shown in a schematic block diagram. As shown, the calculating circuit has a first to a third input terminals lO to 12, a first and a second i.nverter 13 and 16, an adder 14, a +l increment circuit 15 for adding 1 to input data, a selector 17, and an output terminal 18. Two numerical values (assumed to be x and y) having the same bit length and represented by 2's complement notation are individually applied to the input terminals 10 and 11. While the numerical value x i5 directly fed to a terminal A of the adder 14, the numerical value y is inverted by the inverter 13 and then fed to a terminal B of the adder 14. In accordance with the present . . ~.
W~3~
invention, the terminal C of the adder 14 in adders 6 and 7 of Fiyure 1 used to receive a numerical value adapted for carrying via the third input terminal 12, is not used.
Hence, the adder 14 performs an addition of (x -~ y) and produces the result on its terminal S. By adopting the previously discussed principle of 2's complements, y = (y -1) is obtained from y = (y + 1) and, therefore, theaddition result (x + y) of the adder 14 may be expressed as (x - y - 1). The addition result (x - y - 1) is fed to the inventer 16, plus one circuit ~5, and a select terminal W of the selector 17 which responds to a sign bit of the addition result. In response, the inv~rter 16 produces a first calculation result (y - x~ by inverting (x - y - 13. This will be clearly understood because the inverted version (x - y - 1) of (X - y - 1) is equal to {(x - y - 1) - 1} and because (x - y - 1) is equivalent to -(x - y - 1), i.e.
, ~
(x - y - 1) = -(x - y - 1) - 1 = (y - x). It will also be clear that the plus one circuit 15 produces a second calculation result (x - y) because it adds 1 to (x - y - 1).
When the sign bit of (x - y - 1) is "1", (x - y - 1) is smaller than 0 and, therefore, the selector 17 delivers the first calculation result from the inverter 16 via its output terminal Z. Conversely, when the sign bit is "0", the selector 17 feeds the second calculation result ~rom the plus one circuit 15 via the terminal Z.
The operation of the calculating circuit having the above construction will be described by using specific numerical values. Assume that the numerical values x and y applied to the input terminals 10 and 11 are respectively (00112 = 3,~) and 01012 = 5,0~ where the suffixes 2 and 10 show that their associated numbers are a binary number and a decimal number, respectively, and that in each binary number the rightmost bit is the least significant bit (LSB).
Further, let the successive bits beginning with LSB be called the first bit (b,), second bit (b2), and so on. The numerical value y is inverted by the inverter 13 and then , , '7 fed to the adder 14 in the form of y = (10102). In response, the adder 14 performs an addition of x(00112) ~ y(10102) to produce (11012). This output (11012) is routed to the plus one circuit 15 and second in~erter 16, whereby the sum x +
y + 1 (11102) = 3~0) and an inverted x + y (00102 = 2~o) are obtained. On the other hand, th~ fourth bit "l" or the sign bit of the output S (11012) of the adder 14 is applied to the select terminal W of the selector 17, so that the selector 17 selects the output (00102) of the inverter 16 based on "1"
appearing on the select terminal W. Since the present invention determines the sign of the output of the adder 14 on the basis of a sign bit, it ignores a carry output of the adder 14 as in the prior art. The result OO10, i.e. 2 verifies the operation 13 - 5¦ = 2.
Figure 3 shows a specific construction of the "+1"
circuit 15 of the calculating circuit in accordance with the present invention. While a variety of implementations may be contemplated for adding 1 to an input value such as an adder or a counter, the plus one circuit 15 is implemented as a simple combination of logical circuits. The circuit of Figure 3 is assumed to operate an input value having four bits, i.e. 8(10002) to +7(01112). It is to be noted that inputs Il to I4 are associated respectively with LSB (b,) to sign bit (b4) of the input value. Specifically, the "~1"
circuit 15 consists o~ a first inverter 21, a first to a third Exclusive-OR (EXOR) gate 22 to 24, and a first and a second AND gate 25 and 26. When 1 is added to an input va~ue, the first bit b~ of the input value is inverted without exception. Therefore, the first inverter 21 unconditionally inverts the first bit b, to produce an output Rl. On the other hand, carry at the n-th bit bn (n being a natural number and n > 1) occurs when all o~ the bits b, to bnl are 1 due to the addition of 1 to the first bit b, and, hence, whether or not carry to the n-th bit bn from the lower bit occurs can be determined on the result of AND operation of all of the lower bits. The AND gates 25 and 26 are .
~Q~9~3~
adapted to determine respectively whether or not carry to the third bit b~ and carry to the fourth bit b4 occur.
Outputs R2 to R4 are the results of addition of the second to fourth bits b2 to b4 and the carry from the lower bits, respectively. This function is implemented by the EXOR's 22 to 24 which individually receive carry from the lower bits at an input terminal and receive the second to fourth bits b2 to b4 at the other input terminal. Although the specific construction of Figure 3 has been described in relation to a four-bit input value, it will be apparent that a 'l+l"
cir~uit operable with an n-bit input value is obtained by increasing the number of EXOR gates and AND gates.
In summary, it will be seen that the present invention provides an absolute value calculating circuit which needs only a single adder and, yet, is operable at a high speed and therefore contributes a great deal to miniature circuit configuration, power saving and cost reduction.
,~ ~
Claims (4)
1. An absolute value calculating circuit for producing an absolute value of a difference between a first and a second numerical value which have a predetermined bit length and are represented by 2's complement notation, comprising:
first inverting means for inverting the first numerical value to output an inverted numerical value;
first adding means for adding the second numerical value to the inverted numerical value to output an addition result;
second inverting means for inverting the addition result to output a first calculation result:
second adding means for adding a logical 1 bit to the addition result to output a second calculation result;
and selecting means for selecting and delivering as an absolute value of a difference either one of the first or second calculation results according to the sign of the addition result.
first inverting means for inverting the first numerical value to output an inverted numerical value;
first adding means for adding the second numerical value to the inverted numerical value to output an addition result;
second inverting means for inverting the addition result to output a first calculation result:
second adding means for adding a logical 1 bit to the addition result to output a second calculation result;
and selecting means for selecting and delivering as an absolute value of a difference either one of the first or second calculation results according to the sign of the addition result.
2. A circuit as claimed in claim 1, wherein said selecting means selects the first calculation result when the addition result is negative and the second calculation result when the addition result is positive.
3. A circuit as claimed in claim 1, wherein said selecting means comprises a selector to which a sign bit of the addition result is applied as an input for selection.
4. A circuit as claimed in claim 1, wherein said second adding means comprises:
inverting means for inverting a least significant bit (first bit) of the addition result having n bits to output a first bit of the second calculation result having n bits;
first through (n-2)th AND gate means provided on a one-for-one basis with respect to the third through n-th bits of the addition result so that an i-th (1 ? i ? n-2) AND gate means outputs a result of AND operation of the first to (i+l)th bits of the addition result as an i-th carry bit;
first Exclusive-OR gate means associated with the second bit of the addition result for outputting a result of Exclusive-OR operation of the first and second bits of the addition result as a second bit of the second calculation result; and second through (n-l)th Exclusive-OR gate means provided on a one-for-one basis with respect to the third through n-th hits of the addition result so that a j-th (2 ( j c n-l) Exclusive-OR gate means outputs a result of Exclusive-OR operation of the (j-l)th carry bit and the (j+l)th hit of the addition result as a (j+l)th bit of the second calculation result.
inverting means for inverting a least significant bit (first bit) of the addition result having n bits to output a first bit of the second calculation result having n bits;
first through (n-2)th AND gate means provided on a one-for-one basis with respect to the third through n-th bits of the addition result so that an i-th (1 ? i ? n-2) AND gate means outputs a result of AND operation of the first to (i+l)th bits of the addition result as an i-th carry bit;
first Exclusive-OR gate means associated with the second bit of the addition result for outputting a result of Exclusive-OR operation of the first and second bits of the addition result as a second bit of the second calculation result; and second through (n-l)th Exclusive-OR gate means provided on a one-for-one basis with respect to the third through n-th hits of the addition result so that a j-th (2 ( j c n-l) Exclusive-OR gate means outputs a result of Exclusive-OR operation of the (j-l)th carry bit and the (j+l)th hit of the addition result as a (j+l)th bit of the second calculation result.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026565A JPH01204138A (en) | 1988-02-09 | 1988-02-09 | Arithmetic circuit |
| JP26565/1988 | 1988-02-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1301937C true CA1301937C (en) | 1992-05-26 |
Family
ID=12197063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000590450A Expired - Lifetime CA1301937C (en) | 1988-02-09 | 1989-02-08 | Absolute value calculating circuit having a single adder |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4953115A (en) |
| EP (1) | EP0328063B1 (en) |
| JP (1) | JPH01204138A (en) |
| CA (1) | CA1301937C (en) |
| DE (1) | DE68927121T2 (en) |
Families Citing this family (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0776911B2 (en) * | 1988-03-23 | 1995-08-16 | 松下電器産業株式会社 | Floating point arithmetic unit |
| US5379351A (en) * | 1992-02-19 | 1995-01-03 | Integrated Information Technology, Inc. | Video compression/decompression processing and processors |
| JPH038018A (en) * | 1989-06-06 | 1991-01-16 | Toshiba Corp | Adder / subtracter for signed absolute value |
| JPH03136166A (en) * | 1989-10-23 | 1991-06-10 | Nec Corp | Arithmetic circuit |
| JPH0484317A (en) * | 1990-07-27 | 1992-03-17 | Nec Corp | Arithmetic logic unit |
| US6965644B2 (en) * | 1992-02-19 | 2005-11-15 | 8×8, Inc. | Programmable architecture and methods for motion estimation |
| US5251164A (en) * | 1992-05-22 | 1993-10-05 | S-Mos Systems, Inc. | Low-power area-efficient absolute value arithmetic unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3100835A (en) * | 1960-01-06 | 1963-08-13 | Ibm | Selecting adder |
| NL288833A (en) * | 1962-02-12 | |||
| US4153939A (en) * | 1976-01-24 | 1979-05-08 | Nippon Electric Co., Ltd. | Incrementer circuit |
| US4075704A (en) * | 1976-07-02 | 1978-02-21 | Floating Point Systems, Inc. | Floating point data processor for high speech operation |
| US4218751A (en) * | 1979-03-07 | 1980-08-19 | International Business Machines Corporation | Absolute difference generator for use in display systems |
| JPS5966790A (en) * | 1982-10-08 | 1984-04-16 | Nec Corp | Operating circuit |
| JPS59188740A (en) * | 1983-04-11 | 1984-10-26 | Hitachi Ltd | Floating adder |
| US4849921A (en) * | 1985-06-19 | 1989-07-18 | Nec Corporation | Arithmetic circuit for calculating the absolute value of the difference between a pair of input signals |
| JPH0650462B2 (en) * | 1986-02-18 | 1994-06-29 | 日本電気株式会社 | Shift number control circuit |
| US4841467A (en) * | 1987-10-05 | 1989-06-20 | General Electric Company | Architecture to implement floating point multiply/accumulate operations |
-
1988
- 1988-02-09 JP JP63026565A patent/JPH01204138A/en active Pending
-
1989
- 1989-02-08 DE DE68927121T patent/DE68927121T2/en not_active Expired - Fee Related
- 1989-02-08 EP EP89102140A patent/EP0328063B1/en not_active Expired - Lifetime
- 1989-02-08 CA CA000590450A patent/CA1301937C/en not_active Expired - Lifetime
- 1989-02-09 US US07/308,296 patent/US4953115A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE68927121T2 (en) | 1997-01-30 |
| EP0328063A3 (en) | 1991-06-12 |
| US4953115A (en) | 1990-08-28 |
| EP0328063B1 (en) | 1996-09-11 |
| EP0328063A2 (en) | 1989-08-16 |
| DE68927121D1 (en) | 1996-10-17 |
| JPH01204138A (en) | 1989-08-16 |
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