JPH05291588A - Transistor using two-layer polysilicon gate and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve writing characteristics of an EPROM using a transistor having a two-layer polysilicon gate so that an entire length of a channel is under the control of the gate. CONSTITUTION:A width of polysilicon of a second polysilicon layer 4, i.e., an upper layer gate is set 90% or less of that of a first polysilicon layer 2, i.e., a lower layer gate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor having a two-layer polysilicon gate used as a memory element of EPROM and a method of manufacturing the same.

[0002]

2. Description of the Related Art Such a transistor has a gate in which a first oxide film, a first polysilicon layer, a second oxide film and a second polysilicon layer are sequentially stacked on a semiconductor substrate, and a gate in the periphery thereof. It has a source and a drain formed by doping impurities. A method of manufacturing such a transistor is shown in FIG. That is, first, a silicon (Si) substrate is oxidized to form a first gate oxide film 1, and C is formed thereon.
The first polysilicon layer 2 is formed by VD. Further thereon, the second oxide film 3 and the second polysilicon layer 4 are formed by the same method. This state is shown in FIG. A gate is patterned thereon with a photoresist 6 (FIG. 2 (2)), and the second polysilicon layer 4, the second oxide film 3 and the first polysilicon layer 2 are sequentially formed by anisotropic etching. Etching is performed (FIG. 2C).

After that, the resist 6 is removed by O ₂ plasma, the whole is oxidized to form a thin oxide film, and then a third polysilicon layer 5 to be the gate electrode of the peripheral transistor is formed by CVD (FIG. 2 ( 4)). When the peripheral transistors are patterned and etched, the portions of the memory elements do not have a resist pattern, so that they are in the form of etch back, and sidewalls are formed as shown in FIG. 2 (5). After that, if + As is injected into the periphery and driven, as shown in FIG.
And the drain 8 are formed to complete the transistor of the memory element. In this case, as shown in FIG. 2 (6), the channel length L ₁ becomes longer than the width of the gate, and there is a drawback that the write characteristic is deteriorated.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to develop a process in which the sidewall is not formed, and to develop a transistor having a short channel length, that is, a double-layer polysilicon gate having a good writing characteristic of EPROM. To do.

[0005]

According to the present invention, this problem is solved as follows. That is, in the transistor as described above, the width of the second polysilicon layer is 90% or less of the width of the first polysilicon layer. With this structure, after forming the polysilicon for the gate electrode of the peripheral transistor and etching it thereafter, the side wall as in the prior art is not formed. Therefore, when + As is injected and driven for the source and drain, these source and drain regions wrap around below the floating gate made of the first polysilicon layer, and the channel length is
It is equal to or shorter than the width of the first polysilicon layer. Therefore, the entire channel is under the control of the floating gate, and extremely good write characteristics can be obtained.

Further, according to the present invention, such a transistor is manufactured by the following method. That is, a first oxide film, a first polysilicon layer, a second oxide film and a second polysilicon layer are sequentially formed on a semiconductor substrate, a gate is patterned with a photoresist, and a second polysilicon film is formed. The layer is isotropically etched, and the second oxide film and the first polysilicon layer are anisotropically etched, respectively, to remove the photoresist and then form and remove the third polysilicon layer. After that, impurities are doped around the periphery. By this method, the second polysilicon layer having a width of 90% or less of the width of the first polysilicon layer is reliably formed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described in detail below with reference to FIG. FIG. 1 is a cross-sectional view showing the process flow of an EPROM memory element according to the present invention. First silicon S
The i-substrate is oxidized to form the first oxide film 1 for the gate,
A first polysilicon layer 2 is formed thereon by CVD. Further thereon, the second oxide film 3 and the second polysilicon layer 4 are formed by the same method. This state is shown in FIG. The gate is patterned by the photoresist 6 thereon (FIG. 1 (2)). Next, the memory portion is etched. At this time, the second polysilicon layer 4 is subjected to isotropic etching, and the second oxide film 3 and the first polysilicon layer 2 are subjected to anisotropic etching. .. The state after this etching is shown in FIG.

In this case, the etching conditions for the second polysilicon 4 are as follows: SF ₆ is 50 sccm and C ₂ ClF ₅ is 1.
The pressure is 00 sccm, the pressure is 100 mTorr, and the RF power is 100 W. The etching conditions for the second oxide film 3 are as follows: Ar is 300 sccm, CF ₄ is 100 sccm,
CHF ₃ is 50 sccm, pressure is 1.5 Torr, RF
The power is 500 W, and the etching conditions for the first polysilicon layer 2 are 100 sccm for CCl _{4 and} 1 for O _2.
0sccm, He is 400sccm, pressure is 500mT
orr. These values are an example for good etching, and it has been confirmed that good etching is possible by values around these values.

After that, the resist 6 is removed, and the third polysilicon layer 5 to be the gate electrode of the peripheral transistor is CV-ed.
When the film is formed by D (FIG. 1 (4)), the film can be formed with good coverage. Therefore, when the third polysilicon layer 5 is removed by etching ((5) in FIG. 1), side walls (FIGS. 2 (4) and (5)) as in the conventional technique are not formed. Then, as + As is injected and driven to form the source and drain of the portion of the memory element, the transistor of the memory element is completed as shown in FIG. 1 (6). At this time, no offset occurs between the source / drain region and the gate electrode, that is, the channel length does not become longer than the width of the gate electrode, so that good write characteristics are achieved.

[0010]

In the transistor having the two-layer polysilicon gate according to the present invention, since the sidewall is not formed on the side surface of the gate electrode, no offset is generated between the source / drain and the gate electrode, and therefore the channel is entirely the gate. Since it is under the control, the write characteristic is improved and the operation speed is also increased. According to the method of manufacturing a transistor having a two-layer polysilicon gate according to the present invention, the second polysilicon layer having a width of 90% or less as compared with the first polysilicon layer can be reliably formed. Further, since the second polysilicon layer is isotropically etched, an etching residue is unlikely to be generated, and the etching residue is used as a mask for the second polysilicon layer.
It is possible to prevent etching residue from being generated in the oxide film and the first polysilicon layer.

[Brief description of drawings]

1 is a cross-sectional view showing a process of manufacturing an EPROM memory element according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of an EPROM memory element according to the prior art.

[Explanation of symbols]

 1 First Oxide Film 2 First Polysilicon Layer 3 Second Oxide Film 4 Second Polysilicon Layer 5 Third Polysilicon Layer 6 Photoresist 7 Source 8 Drain

Claims (3)

[Claims] 1. A gate in which a first oxide film, a first polysilicon layer, a second oxide film, and a second polysilicon layer are sequentially stacked on a semiconductor substrate, and an impurity is doped around the gate. A transistor having a two-layer polysilicon gate, wherein the width of the second polysilicon layer is 90% or less of the width of the first polysilicon layer in the transistor having the source and the drain. 2. A first oxide film, a first polysilicon layer, a second oxide film and a second polysilicon layer are sequentially formed on a semiconductor substrate, and a gate is patterned with a photoresist, The second polysilicon layer is isotropically etched, and the second oxide film and the first polysilicon layer are anisotropically etched, respectively, and the photoresist is removed to form the third polysilicon layer. 2. The method for manufacturing a transistor having a two-layer polysilicon gate according to claim 1, wherein the transistor is removed and removed, and then impurities are doped around the periphery. 3. The etching conditions for the second polysilicon layer are as follows: SF ₆ is 10 to 100 sccm and C ₂ ClF ₅ is 2.
0 to 100 sccm, the pressure is 50 to 500 mTorr, and the etching condition of the first polysilicon layer is CC
l ₄ is 10 to 200 sccm, O ₂ is ₂ to 100 sccm
m and He are 50 to 700 sccm, and the pressure is 100 to 10
The method for manufacturing a transistor having a two-layer polysilicon gate according to claim 2, wherein the transistor has a thickness of 00 mTorr.