JPH05291571A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05291571A JPH05291571A JP8674192A JP8674192A JPH05291571A JP H05291571 A JPH05291571 A JP H05291571A JP 8674192 A JP8674192 A JP 8674192A JP 8674192 A JP8674192 A JP 8674192A JP H05291571 A JPH05291571 A JP H05291571A
- Authority
- JP
- Japan
- Prior art keywords
- source
- region
- transistor
- diode
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【０００１】この発明はトランジスタに関し、特にバイ
ポーラトランジスタまたはＭＯＳ型電界効果トランジス
タの構造に関する。The present invention relates to a transistor, and more particularly to the structure of a bipolar transistor or a MOS type field effect transistor.
【０００２】[0002]
【従来の技術】従来、トランジスタは図４に断面図とし
て示すＭＯＳ型電界効果トランジスタのようにドレイン
（バイポーラトランジスタの場合はコレクタ）として作
用する基板の上のエピタキシャル層１１の表面に逆導電
型の層２０を設け、ソースアルミ電極（バイポーラトラ
ンジスタ場合はエミッタ電極）１５を前記逆導電型の層
２０まで引き出し、ボンデングワイヤ６を接続するボン
ディングパッドとしている。2. Description of the Related Art Conventionally, a transistor has a reverse conductivity type on the surface of an epitaxial layer 11 on a substrate which acts as a drain (collector in the case of a bipolar transistor) like a MOS field effect transistor shown in a sectional view in FIG. A layer 20 is provided, a source aluminum electrode (emitter electrode in the case of a bipolar transistor) 15 is led out to the layer 20 of the opposite conductivity type, and it is used as a bonding pad for connecting the bonding wire 6.
【０００３】なお、上記のような構成とする主な理由は
ドレイン（コレクタ）領域表面に酸化膜を介して、設け
たボンディングパッドにワイヤボンディングを行うと
（特にパワートランジスタの場合はワイヤが太いので）
酸化膜にクラックが入りがちであり、クラックが入ると
ソース−ドレイン間（エミッタ−コレクタ間）がショー
トまたは耐圧不良となるのでそれをさけるためである。The main reason for adopting the above-mentioned structure is to perform wire bonding on a bonding pad provided on the surface of the drain (collector) region through an oxide film (especially in the case of a power transistor, the wire is thick). )
This is because cracks tend to occur in the oxide film, and if cracks occur, a short circuit occurs between the source and drain (between the emitter and collector) or a withstand voltage defect, and this is avoided.
【０００４】したがって、ドレイン−ソース間（コレク
タ−エミッタ間）は逆方向に電圧が引加されるとショー
ト状態となっている。Therefore, the drain-source (collector-emitter) is short-circuited when a voltage is applied in the opposite direction.
【０００５】なお，図４に示すトランジスタのボンディ
ングパッドではなく、酸化膜上にボンディングパッドを
設けるものについても、ＭＯＳ型電界効果トランジスタ
はやはり逆方向はショートとなっており、バイポーラト
ランジスタの場合は比較的低い耐圧のエミッタ接合の逆
耐圧を有しており、いずれも逆方向に電圧が与えられる
と電流が流れる構造となっている。Even in the case where the bonding pad is provided on the oxide film instead of the bonding pad of the transistor shown in FIG. 4, the MOS field effect transistor is also short-circuited in the opposite direction. It has a reverse breakdown voltage of the emitter junction with a relatively low breakdown voltage, and each has a structure in which a current flows when a voltage is applied in the opposite direction.
【０００６】[0006]
【発明が解決しようとする課題】ところで上記の従来の
トランジスタは逆方向にはＯＮ状態となっているので、
突発的な電気的パルス、つまりサージに対して過大な電
流が流れ、ダメージを受け易いという欠点があった。By the way, since the above-mentioned conventional transistor is turned on in the opposite direction,
There is a drawback in that excessive current flows due to a sudden electric pulse, that is, a surge, and is easily damaged.
【０００７】[0007]
【課題を解決するための手段】この発明のトランジスタ
は、基板となるウェーハに、基板とは逆の導電型で表面
をのぞき取り囲まれた基板と同じ導電型ボンディング領
域を形成し、その表面に選択的に基板とは逆の導電型の
ソース（エミッタ）電極接続領域を形成し、前記電極接
続領域にソース電極（エミッタ電極）を接続し、前記ボ
ンディング領域表面にボンディングパッドを設けたこと
を特徴とする。According to the transistor of the present invention, a bonding region having the same conductivity type as that of a substrate having a conductivity type opposite to that of the substrate except the surface is formed on a wafer serving as a substrate, and the bonding region is selected on the surface. A source (emitter) electrode connection region having a conductivity type opposite to that of the substrate is formed, a source electrode (emitter electrode) is connected to the electrode connection region, and a bonding pad is provided on the surface of the bonding region. To do.
【０００８】[0008]
【作用】上記の構成によると、ソース電極（エミッタ電
極）はソース（エミッタ）電極接続領域とボンディング
領域とで作るダイオードを介してボンディングパッドに
接続するので逆方向には電流が流れず保護の役割を果た
し、トランジスタがＯＮ状態のときにはダイオードは順
方向となるので十分な通電が電圧降下を起こすことなく
可能である。According to the above structure, since the source electrode (emitter electrode) is connected to the bonding pad through the diode formed by the source (emitter) electrode connecting region and the bonding region, a current does not flow in the opposite direction and the role of protection. Since the diode is in the forward direction when the transistor is in the ON state, sufficient current can be supplied without causing a voltage drop.
【０００９】[0009]
【実施例１】以下、この発明について図面を参照して説
明する。First Embodiment The present invention will be described below with reference to the drawings.
【００１０】第１図はこの発明の一実施例のＮチャンネ
ルＭＯＳ型電界効果トランジスタの断面図である。図に
おいて、１はゲートポリシリコン電極、２は層間絶縁
膜，３はゲート酸化膜，４は厚い酸化膜、５はアルミで
なるボンディングパッド、６はソースボンディングワイ
ヤー、７・８はＭＯＳトランジスタを形成するベース・
ソース部、９・１０は絶縁領域を形成するための押込拡
散部・埋込拡散部、１１はドレインとして作用するＮ型
エピタキシャル層、１２はＮ+ 型エピタキシャル層、１
２はＮ+ 型基板ウェーハ、１３はダイオードのアノード
として作用するＰ型ソース電極接続する領域、１４はダ
イオードのカソードとして作用するＮ型のボンディング
領域で、エピタキシャル層１１と同時に形成される、１
５はソースアルミ電極である。FIG. 1 is a sectional view of an N-channel MOS field effect transistor according to an embodiment of the present invention. In the figure, 1 is a gate polysilicon electrode, 2 is an interlayer insulating film, 3 is a gate oxide film, 4 is a thick oxide film, 5 is a bonding pad made of aluminum, 6 is a source bonding wire, and 7 and 8 are MOS transistors. Base
Source portions, 9 and 10 are indented diffusion portions / buried diffusion portions for forming insulating regions, 11 is an N-type epitaxial layer acting as a drain, 12 is an N + -type epitaxial layer, 1
Reference numeral 2 is an N + -type substrate wafer, 13 is a region for connecting a P-type source electrode that acts as an anode of the diode, and 14 is an N-type bonding region that acts as a cathode of the diode, which is formed simultaneously with the epitaxial layer 11.
Reference numeral 5 is a source aluminum electrode.
【００１１】次に上記のＭＯＳ型電界効果トランジスタ
の動作について説明する。ゲートポリシリコン電極１に
正の電圧を印加することでＭＯＳ型電界効果トランジス
タはＯＮ状態となり、ＯＮ電流は基板ウェーハ１２→エ
ピタキシャル層１１→ベース部７→ソース部８→ソース
アルミ電極１５を通り、ソース電極接続領域１３からボ
ンディング領域１４とボンディングパッド５を通ってソ
ースボンディングワイヤ６に通電される。Next, the operation of the above MOS type field effect transistor will be described. By applying a positive voltage to the gate polysilicon electrode 1, the MOS field effect transistor is turned on, and the ON current passes through the substrate wafer 12 → epitaxial layer 11 → base portion 7 → source portion 8 → source aluminum electrode 15, The source bonding wire 6 is energized from the source electrode connection region 13 through the bonding region 14 and the bonding pad 5.
【００１２】一方、ＭＯＳ型電界効果トランジスタがＯ
ＦＦ状態のときソース−ドレイン間に逆電圧が印加され
た場合は、ソース電極接続領域１３とボンディング領域
１４、ソースアルミ電極１５には電流は流れない。On the other hand, the MOS field effect transistor is
When a reverse voltage is applied between the source and the drain in the FF state, no current flows in the source electrode connection region 13, the bonding region 14, and the source aluminum electrode 15.
【００１３】この実施例によればトランジスタがＯＮ状
態のときには，基板つまりドレインがソースワイヤーへ
の通電は可能であり、ＯＦＦ状態のときには、ダイオー
ドの働きにより、ソース側からのサージに対して、トラ
ンジスタを保護することになり、破壊耐量が向上すると
いう利点がある。本実施例はＭＯＳ型電界効果トランジ
スタであるがバイポーラトランジスタでも同様な効果が
ある。According to this embodiment, when the transistor is in the ON state, the substrate, that is, the drain, can energize the source wire, and in the OFF state, the diode functions to prevent the surge from the source side. Will be protected, and there is an advantage that the breakage resistance is improved. This embodiment is a MOS field effect transistor, but a bipolar transistor also has a similar effect.
【００１４】図２に電界効果トランジスタとバイポーラ
トランジスタにダイオードを形成した場合の回路図を示
す。ダイオード１６・１７によりソース側からのサージ
に対してトランジスタは保護される。FIG. 2 shows a circuit diagram when a diode is formed in the field effect transistor and the bipolar transistor. The transistors are protected against surges from the source side by the diodes 16 and 17.
【００１５】図５にソース−ドレイン間の電圧・電流特
性を示す。１８はドレインからソース方向への通常の耐
圧値、１９はダイオードの逆耐圧値であり、（ａ），
（ｂ）のようにダイオードの耐圧は、図１０のソース電
極接続領域１３の不純物より設定が自由である。FIG. 5 shows the voltage-current characteristics between the source and the drain. 18 is the normal withstand voltage value from the drain to the source direction, 19 is the reverse withstand voltage value of the diode, (a),
As shown in (b), the breakdown voltage of the diode can be freely set by the impurities in the source electrode connection region 13 of FIG.
【００１６】[0016]
【実施例２】図３はこの発明の第２実施例の断面図であ
る。この実施例は、前記第１の実施例の図１注のソース
電極接続領域１３、つまりダイオードのアノードとなる
Ｐ領域をボンディングパッド５を取り囲む環状にした点
を除いては、第１の実施例と同様であるため、同一部分
には同一参照符号を付してその説明を省略する。この実
施例ではＰ領域１３を長く環状に形成しているため、接
合面積が大きくなることで電流容量が大きくなり大電流
通電が可能になり、破壊耐量も向上するという利点があ
る。Second Embodiment FIG. 3 is a sectional view of a second embodiment of the present invention. This embodiment is the same as the first embodiment except that the source electrode connection region 13 of FIG. 1Note of the first embodiment, that is, the P region serving as the anode of the diode is formed in an annular shape surrounding the bonding pad 5. Therefore, the same parts are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, since the P region 13 is formed in a long annular shape, there is an advantage that the junction area becomes large, the current capacity becomes large, a large current can be conducted, and the breakdown resistance is improved.
【００１７】以上実施例はＮチャンネルＭＯＳ型電界効
果トランジスタに付いて主として説明したが、他のトラ
ンジスタん、例えばＰチャンネル電界効果トランジス
タ、ＮＰＮトランジスタにも同様の効果があることは言
うまでもない。Although the embodiments have been mainly described with respect to the N-channel MOS type field effect transistor, it goes without saying that other transistors such as a P-channel field effect transistor and an NPN transistor also have similar effects.
【００１８】[0018]
【発明の効果】以上説明したように、この発明はトラン
ジスタの逆方向にも耐圧を持たせたことにより、逆方向
のサージに対してトランジスタ本体を保護することによ
り破壊し憎くなるという効果がある。As described above, according to the present invention, the breakdown voltage is provided in the reverse direction of the transistor as well, so that the transistor body is protected against the surge in the reverse direction and is destroyed and hated. .
【００１９】また、両方向に耐圧のあるトライアックよ
りもＭＯＳ型電界効果トランジスタにすればスイッチン
グスピードが早くなり、スイッチングロスも少なくなり
有利である。Further, if a MOS type field effect transistor is used rather than a triac having a withstand voltage in both directions, the switching speed becomes faster and the switching loss is reduced, which is advantageous.
【図１】 この発明のダイオードを形成したＭＯＳ型電
界効果トランジスタの断面図。FIG. 1 is a sectional view of a MOS field effect transistor having a diode according to the present invention.
【図２】 （ａ）は本発明のＭＯＳ型電界効果トランジ
スタの等価回路図。（ｂ）は、バイポーラＮＰＮトラン
ジスタの等価回路図である。FIG. 2A is an equivalent circuit diagram of a MOS field effect transistor of the present invention. (B) is an equivalent circuit diagram of a bipolar NPN transistor.
【図３】 本発明の他の実施例の断面図。FIG. 3 is a sectional view of another embodiment of the present invention.
【図４】 従来のＭＯＳ型電界効果トランジスタのソー
スボンディングワイヤ付近の断面図。FIG. 4 is a cross-sectional view of a conventional MOS field effect transistor in the vicinity of a source bonding wire.
【図５】 （ａ），（ｂ）は本発明の電圧・電流特性図
である。（ｃ）は従来トランジスタの電圧・電流特性図
である。5A and 5B are voltage / current characteristic diagrams of the present invention. (C) is a voltage-current characteristic diagram of a conventional transistor.
１ ゲートポリシリコン電極 ２ 層間絶縁膜 ３ ゲート酸化膜 ４ 厚い酸化膜 ５ ソース電極ボンディングパッド ６ ソースボンディングワイヤ ７ ＭＯＳトランジスタユニットセル部Ｐ型ベース領域 ８ ＭＯＳトランジスタユニットセル部Ｎ型ソース領域 ９ 押込拡散部 １０ 埋込拡散部 １１ エピタキシャル層 １２ 基板ウェーハ １３ ダイオードアノードＰ型領域（ソース電極接続領
域） １４ ダイオードカソードＮ型領域（ボンディング領
域） １５ ソースアルミ電極 １６ ダイオード １７ ダイオード １８ トランジスタ耐圧値 １９ ダイオード耐圧値1 Gate Polysilicon Electrode 2 Interlayer Insulation Film 3 Gate Oxide Film 4 Thick Oxide Film 5 Source Electrode Bonding Pad 6 Source Bonding Wire 7 MOS Transistor Unit Cell Part P-type Base Region 8 MOS Transistor Unit Cell Part N-type Source Region 9 Indented Diffusion Part 10 Embedded Diffusion Part 11 Epitaxial Layer 12 Substrate Wafer 13 Diode Anode P-type Region (Source Electrode Connection Region) 14 Diode Cathode N-type Region (Bonding Region) 15 Source Aluminum Electrode 16 Diode 17 Diode 18 Transistor Withstand Voltage Value 19 Diode Withstand Voltage Value
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/73 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 29/73
Claims (2)
基板とは逆導電型の領域で表面をのぞいて囲まれて電気
的に絶縁された、基板と同じ導電型のボンディイング領
域と、その領域内表面に選択的に形成された基板とは逆
導電型のソース（又はエミッタ）電極接続領域と、前記
ボンディング領域の表面に設けたボンディングパッド
と、前記ソース（又はエミッタ）電極接続領域に接続す
るソース（又はエミッタ）とを具備することを特徴とす
る半導体装置。1. A bonding region of the same conductivity type as that of the substrate, which is surrounded by a region of a conductivity type opposite to that of the substrate acting as a drain (or collector) except for the surface and is electrically insulated, and within that region. A source (or emitter) electrode connection region having a conductivity type opposite to that of the substrate selectively formed on the surface, a bonding pad provided on the surface of the bonding region, and a source connected to the source (or emitter) electrode connection region. (Or an emitter).
が、前記ボンディング領域内で環状に形成されているこ
とを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the source (or emitter) electrode connection region is formed in a ring shape in the bonding region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8674192A JP3211351B2 (en) | 1992-04-08 | 1992-04-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8674192A JP3211351B2 (en) | 1992-04-08 | 1992-04-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05291571A true JPH05291571A (en) | 1993-11-05 |
| JP3211351B2 JP3211351B2 (en) | 2001-09-25 |
Family
ID=13895234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8674192A Expired - Fee Related JP3211351B2 (en) | 1992-04-08 | 1992-04-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3211351B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248657B1 (en) | 1998-03-13 | 2001-06-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
-
1992
- 1992-04-08 JP JP8674192A patent/JP3211351B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248657B1 (en) | 1998-03-13 | 2001-06-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| KR100306858B1 (en) * | 1998-03-13 | 2001-11-17 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3211351B2 (en) | 2001-09-25 |
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