JPH0529156U - Package for thin integrated circuits - Google Patents
Package for thin integrated circuitsInfo
- Publication number
- JPH0529156U JPH0529156U JP7796591U JP7796591U JPH0529156U JP H0529156 U JPH0529156 U JP H0529156U JP 7796591 U JP7796591 U JP 7796591U JP 7796591 U JP7796591 U JP 7796591U JP H0529156 U JPH0529156 U JP H0529156U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- integrated circuit
- sealing plate
- thin
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 外部リードの端部の板厚方向のばらつきのな
い薄型集積回路用パッケージの提供。
【構成】 基板４は、グリーンシートを積層して焼結し
たラミネートセラミックよりなる。外部リード５は、基
板４の凹部３が設けられた面とは異なった側の面に固着
される。基板４に搭載された集積回路２と外部リード５
とは、基板４内に形成された内部配線８によって電気的
に接続される。そして、基板４と封止板７とは、外部リ
ード５を介すことなくフリットシール６を介して接合さ
れる。
(57) [Abstract] [Purpose] To provide a thin integrated circuit package in which the ends of the external leads do not vary in the plate thickness direction. [Structure] The substrate 4 is made of a laminated ceramic in which green sheets are laminated and sintered. The external leads 5 are fixed to the surface of the substrate 4 different from the surface on which the concave portion 3 is provided. Integrated circuit 2 and external leads 5 mounted on substrate 4
Are electrically connected to each other by an internal wiring 8 formed in the substrate 4. Then, the substrate 4 and the sealing plate 7 are bonded via the frit seal 6 without the external lead 5.
Description
【０００１】[0001]
本考案は、薄型製品に用いて好適な薄型の集積回路用パッケージに関するもの である。 The present invention relates to a thin integrated circuit package suitable for use in thin products.
【０００２】[0002]
従来の薄型集積回路用パッケージの一例として、実開平１−１６０８６０号公 報に開示された技術が知られている。この技術は、図２に示すように、凹部101 を備えたプレスセラミック基板１０２と、セラミック製封止板１０３と、基板１ ０２と封止板１０３との間に挟まれた外部リード１０４とからなり、基板１０２ と封止板１０３との間には、封止ガラス１０５（フリットシール）が配され、内 部が気密に保たれている。 As an example of a conventional package for a thin integrated circuit, the technique disclosed in Japanese Utility Model Publication No. 1-160860 is known. As shown in FIG. 2, this technique includes a press ceramic substrate 102 having a recess 101, a ceramic sealing plate 103, and an external lead 104 sandwiched between the substrate 102 and the sealing plate 103. Thus, the sealing glass 105 (frit seal) is arranged between the substrate 102 and the sealing plate 103, and the inside is kept airtight.
【０００３】[0003]
基板１０２と封止板１０３との間に外部リード１０４を挟む構造では、基板１ ０２と封止板１０３との間に、外部リード１０４の両側に配される封止ガラス１ ０５の厚さと、外部リード１０４の厚さとが合わせられた厚みがある。このため 、外部リード１０４に配されていない側の封止ガラス１０５の厚さが厚くなる。 In the structure in which the external lead 104 is sandwiched between the substrate 102 and the sealing plate 103, the thickness of the sealing glass 105 arranged on both sides of the external lead 104 between the substrate 102 and the sealing plate 103, There is a combined thickness with the thickness of the external lead 104. Therefore, the thickness of the sealing glass 105 on the side not provided on the external lead 104 becomes thick.
【０００４】 ところで、封止ガラス１０５によって封止する際、封止ガラス１０５が軟化す るため、外部リード１０４の位置がわずかにずれる。したがって、封止ガラス１ ０５の厚さが厚いと、外部リード１０４の上下方向（板厚方向）の位置ずれ量の ばらつきも増す。By the way, when the sealing glass 105 is used for sealing, the sealing glass 105 is softened, so that the positions of the external leads 104 are slightly displaced. Therefore, if the thickness of the sealing glass 105 is large, the variation in the amount of positional deviation of the external leads 104 in the vertical direction (plate thickness direction) also increases.
【０００５】 この結果、外部リード１０４のうち、マザーボード（図示しない）等と半田付 けされる端部１０４ａの上下方向位置も同様にばらつきが生じ、外部リード１０ ４とマザーボードとの半田付けの信頼性が低下する。As a result, the vertical position of the end 104a of the external lead 104, which is soldered to the mother board (not shown) or the like, also varies, and the reliability of soldering between the external lead 104 and the mother board is increased. Is reduced.
【０００６】 また、集積回路用パッケージの中には、ガラス封止後に外部リード１０４を曲 加工するガルウイングタイプもあるが、この場合でも、外部リード１０４の位置 のばらつきによって、曲加工時に加えられる押圧力が変化することとなり、結果 的に外部リード１０４の端部１０４ａの上下方向位置にばらつきが生じる。Some integrated circuit packages include a gull wing type in which the outer leads 104 are bent after being sealed with glass. However, even in this case, the push applied during the bending process due to variations in the positions of the outer leads 104. The pressure changes, and as a result, the vertical position of the end 104a of the external lead 104 varies.
【０００７】[0007]
本考案は、上記の事情に鑑みてなされたもので、その目的は、外部リードの端 部の板厚方向のばらつきのない薄型集積回路用パッケージの提供にある。 The present invention has been made in view of the above circumstances, and an object thereof is to provide a thin integrated circuit package in which the ends of the external leads do not vary in the plate thickness direction.
【０００８】[0008]
本考案の薄型集積回路用パッケージは、次の技術的手段を採用した。薄型集積 回路用パッケージは、集積回路が搭載される凹部を備えたセラミック基板と、こ の基板に搭載される前記集積回路に電気的に接続される外部リードと、前記集積 回路が搭載された前記基板の前記凹部が設けられた面に、フリットシールを介し て固着される封止板とを具備し、前記封止板の端から前記外部リードの端までの 幅が１ｍｍ以下に設けられる。 The thin integrated circuit package of the present invention employs the following technical means. The thin integrated circuit package includes a ceramic substrate having a concave portion on which the integrated circuit is mounted, external leads electrically connected to the integrated circuit mounted on the substrate, and the external circuit on which the integrated circuit is mounted. A sealing plate fixed to the surface of the substrate on which the concave portion is provided via a frit seal is provided, and the width from the end of the sealing plate to the end of the external lead is set to 1 mm or less.
【０００９】 そして、前記基板は、グリーンシートを積層して焼結したラミネートセラミッ クよりなる。また、前記外部リードは、前記基板の前記凹部が設けられた面とは 異なった側の面に固着される。さらに、前記基板に搭載された前記集積回路と前 記外部リードとは、前記基板内に形成された内部配線を介して、電気的に接続さ れる。The substrate is made of a laminated ceramic in which green sheets are laminated and sintered. Further, the external lead is fixed to a surface of the substrate on a side different from the surface on which the concave portion is provided. Further, the integrated circuit mounted on the substrate and the external leads described above are electrically connected to each other via internal wiring formed in the substrate.
【００１０】 なお、好適には、封止板を光透過性のセラミック材料で形成する。[0012] Preferably, the sealing plate is made of a light transmissive ceramic material.
【００１１】[0011]
本考案の外部リードは、基板と封止板との間に挟まれず、封止板が固着される 側とは異なった側の面に固着される。この結果、基板に対する外部リードの位置 ずれが無くなり、結果的に外部リードの端部の板厚方向のばらつきが無くなる。 この結果、集積回路用パッケージが搭載される電気基板と、外部リードの端部と の半田付けの信頼性が増す。 The external lead of the present invention is not sandwiched between the substrate and the sealing plate, but is fixed to the surface on the side different from the side to which the sealing plate is fixed. As a result, the positional deviation of the external lead with respect to the substrate is eliminated, and as a result, the variation in the thickness direction of the end portion of the external lead is eliminated. As a result, the reliability of soldering between the electric board on which the integrated circuit package is mounted and the end portions of the external leads is increased.
【００１２】[0012]
次に、本考案の薄型集積回路用パッケージを、図に示す一実施例に基づき説明 する。 Next, a thin integrated circuit package of the present invention will be described based on an embodiment shown in the drawings.
【００１３】 〔実施例の構成〕 図１は本考案の実施例を示すもので、薄型集積回路用パッケージの断面図を示 す。本考案の薄型集積回路用パッケージ１は、集積回路２が搭載される凹部３を 備えたセラミック基板４と、この基板４に搭載される集積回路２に電気的に接続 される外部リード５と、基板４の凹部３が設けられた側の面にフリットシール６ を介して固着される封止板７とからなる。[Structure of Embodiment] FIG. 1 shows an embodiment of the present invention and is a cross-sectional view of a thin integrated circuit package. A thin integrated circuit package 1 of the present invention comprises a ceramic substrate 4 having a recess 3 in which an integrated circuit 2 is mounted, external leads 5 electrically connected to the integrated circuit 2 mounted in the substrate 4, A sealing plate 7 is fixed to the surface of the substrate 4 on the side where the recess 3 is provided via a frit seal 6.
【００１４】 基板４は、内部に内部配線８が形成されたラミネートセラミックで、その製造 方法の一例を簡単に説明する。アルミナの未焼結セラミックであるグリーンシー トを非常に薄く形成し、２枚のグリーンシートを積層して焼結してなる。１枚の グリーンシートは、薄い板状を呈し、その表面に積層されるグリーンシートは基 板４の中央部分に凹部３を形成するために、中央に穴が形成されたものである。 各グリーンシートの表面には、スクリーン印刷によって内部配線８が形成されて いる。この内部配線８は、集積回路２と外部リード５とを電気的に接続するため のもので、導体柱９やスルーホール１０を介して各層の内部配線８が電気的に接 続される。基板４の表面（凹部３が形成された側の面）の最外周には、所定幅の 薄いアルミナコート１１が施されている。このアルミナコート１１は、フリット シール６である封止ガラスとの接着性を向上する目的で設けられたものである。 一方、基板４の裏面（凹部３が形成された側とは異なった側の面）の最外周には 、多数の外部リード５が接合される多数のメタライズ層12が形成されている。な お、スルーホール１０には、外部リード５の接合時にろう材のフィレット１３が 形成されて、外部リード５の接合強度を高くする効果を備える。The substrate 4 is a laminated ceramic in which the internal wiring 8 is formed, and an example of its manufacturing method will be briefly described. A green sheet, which is a non-sintered ceramic of alumina, is formed to be very thin, and two green sheets are laminated and sintered. One green sheet has a thin plate shape, and the green sheet laminated on the surface of the green sheet has a hole formed in the center of the base plate 4 to form the recess 3. Internal wiring 8 is formed on the surface of each green sheet by screen printing. The internal wiring 8 is for electrically connecting the integrated circuit 2 and the external lead 5, and the internal wiring 8 of each layer is electrically connected via the conductor pillar 9 and the through hole 10. A thin alumina coat 11 having a predetermined width is applied to the outermost periphery of the surface of the substrate 4 (the surface on the side where the recess 3 is formed). The alumina coat 11 is provided for the purpose of improving the adhesiveness with the sealing glass which is the frit seal 6. On the other hand, a large number of metallized layers 12 to which a large number of external leads 5 are joined are formed on the outermost periphery of the back surface of the substrate 4 (the surface on the side different from the side on which the concave portions 3 are formed). In addition, a fillet 13 of a brazing material is formed in the through hole 10 when the external lead 5 is bonded, which has the effect of increasing the bonding strength of the external lead 5.
【００１５】 外部リード５は、４２アロイ、コバール等の金属薄板をプレス加工やエッチン グ処理によって形成したもので、各外部リード５が基板４の各メタライズ層１２ に接合された後、周囲のリードフレーム（図示しない）が切断されるものである 。この外部リード５は、中間部分に曲折部分１４を備える。この曲折部分１４は 、マザーボード（図示しない）に搭載後、熱ストレスを吸収するためのものであ る。The external leads 5 are formed by pressing or etching a thin metal plate such as 42 alloy or Kovar, and after each external lead 5 is bonded to each metallized layer 12 of the substrate 4, the surrounding leads are formed. The frame (not shown) is cut. The outer lead 5 has a bent portion 14 in the middle portion. The bent portion 14 is for absorbing heat stress after being mounted on a motherboard (not shown).
【００１６】 封止板７は、基板４とほぼ同じ熱膨張率を備える薄いセラミック板で、本実施 例では、封止後にフリットシール６のクラックの有無を外部から視認できるよう に、光透過性のセラミック材料である透光性アルミナを用いている。この封止板 ７は、最外周に設けられたフリットシール６である封止ガラスを介して基板４の 表面に固着され、内部に搭載された集積回路２を気密に保つものである。The sealing plate 7 is a thin ceramic plate having substantially the same coefficient of thermal expansion as that of the substrate 4. In this embodiment, the light transmissivity is set so that the presence or absence of cracks in the frit seal 6 can be visually confirmed after sealing. Translucent alumina, which is a ceramic material of, is used. The sealing plate 7 is fixed to the surface of the substrate 4 via a sealing glass, which is a frit seal 6 provided on the outermost periphery, and keeps the integrated circuit 2 mounted inside airtight.
【００１７】 なお、本実施例の薄型集積回路用パッケージ１の各部の厚さは、封止板７の厚 さ（図１のＡを参照）は０．１８±０．０１５ｍｍで、フリットシール６の厚さ （図１のＢを参照）は０．１２±０．０５ｍｍで、アルミナコート１１の厚さ（ 図１のＣを参照）は０．０５ｍｍで、基板４の表面側の積層体の厚さ（図１のＤ を参照）は０．１５ｍｍで、基板４の裏面側の積層体の厚さ（図１のＥを参照） は０．２０ｍｍで、外部リード５の幅（図１のＦを参照）は０．２±０．０７ｍ ｍで、設けられている。そして、薄型集積回路用パッケージ１のトータルの厚さ （封止板７の端から外部リード５の端までの幅）は、１ｍｍ以下である０．８８ ±０．１０ｍｍに設けられている。The thickness of each part of the thin integrated circuit package 1 of this embodiment is 0.18 ± 0.015 mm for the thickness of the sealing plate 7 (see A in FIG. 1), and the frit seal 6 is used. Has a thickness (see B in FIG. 1) of 0.12 ± 0.05 mm, and the thickness of the alumina coat 11 (see C in FIG. 1) is 0.05 mm. The thickness (see D in FIG. 1) is 0.15 mm, the thickness of the laminate on the back side of the substrate 4 (see E in FIG. 1) is 0.20 mm, and the width of the external lead 5 (see FIG. 1). (See F) is 0.2 ± 0.07 mm and is provided. The total thickness of the thin integrated circuit package 1 (width from the end of the sealing plate 7 to the end of the external lead 5) is 0.88 ± 0.10 mm, which is 1 mm or less.
【００１８】 〔実施例の効果〕 本実施例の薄型集積回路用パッケージ１は、フリットシール６の厚さが従来に 比較して大変薄いため、外部から力が加えられてもフリットシール６にクラック が生じにくい。この結果、集積回路２の気密保持の信頼性が従来より高くなる。 また、ラミネートセラミックは、従来使用されていたプレスセラミックに比較し て抗析強度が高い（プレスセラミックが３８ｋｇ／ｍｍ2 でラミネートセラミッ クが４７ｋｇ／ｍｍ2 ）ため、薄型集積回路用パッケージ１の強度が向上する。 さらに、封止板７を透光性アルミナで形成したことにより、クラックの発生状態 を外部から視認できる。この結果、従来行っていた加圧試験による気密試験を無 くすことができるため、加圧試験時にフリットシール６にクラックが生じる不具 合を無くすことがきる。[Effects of the Embodiment] In the thin integrated circuit package 1 of this embodiment, the frit seal 6 is much thinner than the conventional one, and therefore the frit seal 6 is cracked even when an external force is applied. Is less likely to occur. As a result, the reliability of maintaining the airtightness of the integrated circuit 2 becomes higher than in the conventional case. In addition, the laminated ceramics have higher anti-sedimentation strength than the conventionally used pressed ceramics (38kg / mm 2 for pressed ceramics and 47kg / mm 2 for laminated ceramics). Is improved. Furthermore, since the sealing plate 7 is made of translucent alumina, the state of cracks can be visually confirmed from the outside. As a result, it is possible to eliminate the airtightness test by the pressure test that has been conventionally performed, so that it is possible to eliminate the defect that the frit seal 6 is cracked during the pressure test.
【００１９】 また、本実施例の薄型集積回路用パッケージ１は、外部リード５がセラミック 基板４と封止板７との間に挟まれず封止板７が固着される側とは異なった側の面 のセラミック基板４に固着される。この結果、セラミック基板４に対する外部リ ード５の位置ずれが無くなり、結果的に外部リード５の端部５ａの板厚方向のば らつきが無くなる。この結果、薄型集積回路用パッケージ１が搭載されるマザー ボード（図示しない）と外部リード５の端部５ａとの半田付けの信頼性が増す。Further, in the thin integrated circuit package 1 of the present embodiment, the external lead 5 is not sandwiched between the ceramic substrate 4 and the sealing plate 7, and is provided on the side different from the side to which the sealing plate 7 is fixed. The surface is fixed to the ceramic substrate 4. As a result, the positional deviation of the external lead 5 with respect to the ceramic substrate 4 is eliminated, and as a result, the fluctuation of the end portion 5a of the external lead 5 in the plate thickness direction is eliminated. As a result, the reliability of soldering between the mother board (not shown) on which the thin integrated circuit package 1 is mounted and the ends 5a of the external leads 5 is increased.
【００２０】 上記の実施例で記載した数値や材質などは、実施例を説明するために用いたも のであって、本考案が本実施例に限定されるものではなく、適宜変更可能なもの である。The numerical values, materials, etc. described in the above embodiment are used for explaining the embodiment, and the present invention is not limited to this embodiment, and can be appropriately changed. is there.
【図１】実施例の薄型集積回路用パッケージの断面図で
ある。FIG. 1 is a cross-sectional view of a thin integrated circuit package of an example.
【図２】従来の薄型集積回路用パッケージの要部断面図
である。FIG. 2 is a sectional view of a main part of a conventional thin integrated circuit package.
１ 薄型集積回路用パッケージ ２ 集積回路 ３ 凹部 ４ セラミック基板 ５ 外部リード ６ フリットシール ７ 封止板 ８ 内部配線 1 Thin Integrated Circuit Package 2 Integrated Circuit 3 Recess 4 Ceramic Substrate 5 External Lead 6 Frit Seal 7 Sealing Plate 8 Internal Wiring
Claims (2)
ミック基板と、この基板に搭載される前記集積回路に電
気的に接続される外部リードと、前記集積回路が搭載さ
れた前記基板の前記凹部が設けられた面に、フリットシ
ールを介して固着される封止板とを具備し、 前記封止板の端から前記外部リードの端までの幅が１ｍ
ｍ以下に設けられる薄型集積回路用パッケージにおい
て、 前記基板は、グリーンシートを積層して焼結したラミネ
ートセラミックよりなり、 前記外部リードは、前記基板の前記凹部が設けられた面
とは異なった側の面に固着され、 前記基板に搭載された前記集積回路と前記外部リードと
は、前記基板内に形成された内部配線を介して電気的に
接続されることを特徴とする薄型集積回路用パッケー
ジ。1. A ceramic substrate having a concave portion on which an integrated circuit is mounted, external leads electrically connected to the integrated circuit mounted on the substrate, and the substrate of the substrate on which the integrated circuit is mounted. A sealing plate fixed to the surface provided with the recess via a frit seal, and the width from the end of the sealing plate to the end of the external lead is 1 m.
In the package for thin integrated circuit having a thickness of m or less, the substrate is made of a laminated ceramic obtained by stacking and sintering green sheets, and the external lead is provided on a side different from a surface of the substrate on which the concave portion is provided. A thin integrated circuit package, wherein the integrated circuit mounted on the substrate and the external leads are electrically connected to each other via internal wiring formed in the substrate. ..
料である請求項１の薄型集積回路用パッケージ。2. The thin integrated circuit package according to claim 1, wherein the sealing plate is made of a light transmissive ceramic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7796591U JPH0529156U (en) | 1991-09-26 | 1991-09-26 | Package for thin integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7796591U JPH0529156U (en) | 1991-09-26 | 1991-09-26 | Package for thin integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0529156U true JPH0529156U (en) | 1993-04-16 |
Family
ID=13648665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7796591U Pending JPH0529156U (en) | 1991-09-26 | 1991-09-26 | Package for thin integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0529156U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7364372B2 (en) | 2005-11-18 | 2008-04-29 | Seiko Epson Corporation | Method of manufacturing optical module |
-
1991
- 1991-09-26 JP JP7796591U patent/JPH0529156U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7364372B2 (en) | 2005-11-18 | 2008-04-29 | Seiko Epson Corporation | Method of manufacturing optical module |
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