JPH0529143U - Electrode structure of semiconductor device - Google Patents

Electrode structure of semiconductor device

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Publication number
JPH0529143U
JPH0529143U JP086335U JP8633591U JPH0529143U JP H0529143 U JPH0529143 U JP H0529143U JP 086335 U JP086335 U JP 086335U JP 8633591 U JP8633591 U JP 8633591U JP H0529143 U JPH0529143 U JP H0529143U
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JP
Japan
Prior art keywords
electrode
metal film
bonding
scribe line
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP086335U
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Japanese (ja)
Inventor
彰 羽賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP086335U priority Critical patent/JPH0529143U/en
Publication of JPH0529143U publication Critical patent/JPH0529143U/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】 ボンディング座標の入力・修正の際のバラツ
キを減少させて、ボンディングズレ量を低減することに
より、ボンディング歩留りの向上を図る。 【構成】 電極金属膜1の端部からスクライブ線3の方
向に引き出した突出パターン1−5を有している。この
突出パターン1−5の引き出し部位は、電極金属膜1の
端部の電極幅1−2中央付近であり、引き出す方向は、
スクライブ線に対して直角方向とし、突出パターン1−
5を利用して位置精度を高める。
(57) [Abstract] [Purpose] To improve the bonding yield by reducing the variation when inputting / correcting the bonding coordinates and reducing the amount of bonding deviation. [Structure] A protruding pattern 1-5 is drawn from the end of the electrode metal film 1 in the direction of the scribe line 3. The projecting pattern 1-5 is drawn out near the center of the electrode width 1-2 at the end of the electrode metal film 1, and the drawing direction is
Protrusion pattern 1-
5 is used to improve the position accuracy.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、半導体装置の電極構造に関し、特にワイヤーボンディングの際のボ ンディングズレによる電極間ショート不良をなくした電極構造に関する。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a semiconductor device, and more particularly to an electrode structure which eliminates a short circuit between electrodes due to a bonding deviation during wire bonding.

【0002】[0002]

【従来の技術】[Prior Art]

従来技術について図面を用いて説明する。図7は、従来技術による半導体装置 の電極部の平面図である。半導体装置(以下LSIと称す)の外縁であるスクラ イブ線3の近傍に、スクライブ線3と平行に電極金属膜1が所望の数だけ設けら れる。電極金属膜1上の絶縁膜には開孔部2が設けられており、電極金属膜1の 一部が外部に露出する構造をとっている。 A conventional technique will be described with reference to the drawings. FIG. 7 is a plan view of an electrode portion of a conventional semiconductor device. A desired number of electrode metal films 1 are provided in parallel with the scribe line 3 in the vicinity of the scribe line 3 which is the outer edge of a semiconductor device (hereinafter referred to as LSI). An opening 2 is provided in the insulating film on the electrode metal film 1 so that a part of the electrode metal film 1 is exposed to the outside.

【0003】 開孔部2の形状は、通常矩形であり、スクライブ線3と平行な辺を開孔幅2− 1、垂直な辺を開孔長2−2と称する。従って、露出金属1−1の面積は、開孔 幅と開孔長との積に等しい。The shape of the opening 2 is usually rectangular, and the side parallel to the scribe line 3 is called the opening width 2-1 and the vertical side is called the opening length 2-2. Therefore, the area of the exposed metal 1-1 is equal to the product of the opening width and the opening length.

【0004】 一方、電極金属膜は、スルーホール5等を介して内部配線パターン4と電気的 に接続され、図示していないLSI内部の電気回路へと導かれている。On the other hand, the electrode metal film is electrically connected to the internal wiring pattern 4 through the through holes 5 and the like, and is led to an electric circuit inside the LSI (not shown).

【0005】 一般に、このような電極構造をもつLSIとパッケージとを電気的に接続する 手段として、ワイヤーボンディング法が用いられている。その際、ワイヤーと露 出金属パッドとの密着を安定させるために、露出金属1の部分には、あらかじめ ウェットエッチング法等の処理によって、表面にわずかな凹凸を形成している。Generally, a wire bonding method is used as a means for electrically connecting an LSI having such an electrode structure and a package. At that time, in order to stabilize the adhesion between the wire and the exposed metal pad, a slight unevenness is formed on the surface of the exposed metal 1 in advance by a treatment such as a wet etching method.

【0006】 近年、LSIの集積度が向上し、それに伴って電極数が飛躍的に増加してきて いる。限られた面積のLSI上になるべく多くの電極を設ける必要があるため、 電極ピッチ(パッドピッチ)の縮小化が進行し、それによって、電極幅1−2、 開孔幅2−1、電極間隔1−3のいずれもが小さくなりつつある。In recent years, the degree of integration of LSI has been improved, and the number of electrodes has been dramatically increased accordingly. Since it is necessary to provide as many electrodes as possible on the LSI having a limited area, the electrode pitch (pad pitch) is being reduced, and as a result, the electrode width 1-2, the opening width 2-1 and the electrode spacing are provided. All of 1-3 are becoming smaller.

【0007】 この電極ピッチ(パッドピッチ)の縮小化につれて、ワイヤーボンディング時 の不良が増加しつつある。As the electrode pitch (pad pitch) is reduced, defects during wire bonding are increasing.

【0008】 即ち、ボンディング時のキャピラリ(ツール)と隣接ワイヤーとの接触、ワイ ヤー同士のショート、電極部でのボンディングズレにより、隣接電極間ショート 等である。特に、電極ピッチ(パッドピッチ)のファイン化がある程度進行する と、ボンディングズレに対するマージンが極端に減少し、隣接電極間ショートの 問題は無視できないものとなる。That is, there is a short circuit between adjacent electrodes due to a contact between a capillary (tool) and an adjacent wire at the time of bonding, a short circuit between wires, and a misalignment of bonding at an electrode portion. In particular, as the electrode pitch (pad pitch) becomes finer to a certain extent, the margin for bonding displacement is extremely reduced, and the problem of short circuit between adjacent electrodes cannot be ignored.

【0009】 ボンディングズレによる影響を緩和する方法としては、図8のように電極形状 をワイヤー方向と一致させるものがある。基本的な構成は図7と同様である。即 ち、電極金属膜1,開孔部2,スクライブ線3,内部配線パターン4,スルーホ ール5である。但し、電極形状とワイヤー6の方向を一致させていることにより 、開孔部2及び電極金属膜1は矩形ではなく、平行四辺形の角を落とした形状と なっており、しかも電極の大きさも、LSIコーナー部に近い程大きなものとな っている(放射状にワイヤリングするため)。As a method of mitigating the influence of the bonding deviation, there is a method of matching the electrode shape with the wire direction as shown in FIG. The basic configuration is the same as in FIG. That is, the electrode metal film 1, the opening 2, the scribe line 3, the internal wiring pattern 4, and the through hole 5. However, since the shape of the electrode and the direction of the wire 6 are made to coincide with each other, the opening 2 and the electrode metal film 1 are not rectangular, but the shape of the parallelogram is reduced, and the size of the electrode is also reduced. , The larger the area is, the closer to the LSI corner (because of radial wiring).

【0010】 また、電極間隔1−3は、スクライブ線側と内部配線パターン側で異なってい る。以上の事柄から、ボンディングズレに対してはマージンがあるものの、電極 配置上、高密度にレイアウトすることができないため、150μm以下のファイ ンピッチ電極では、ワイヤー方向を設計上全て平行にすることを前提として、図 7のような矩形の開孔部を有する電極を並べているのが現状である。Further, the electrode interval 1-3 is different between the scribe line side and the internal wiring pattern side. From the above, although there is a margin for bonding deviation, it is not possible to lay out at high density due to the electrode arrangement. Therefore, it is assumed that the wire directions are all parallel in the design for the fine pitch electrode of 150 μm or less. As a current situation, electrodes having rectangular openings as shown in FIG. 7 are arranged.

【0011】[0011]

【考案が解決しようとする課題】[Problems to be solved by the device]

従来の電極構造を用いて電極ピッチを縮小して行くと、ボンディングズレに対 するマージンが減少し、隣接電極間ショートの危険が増加することを前項で述べ た。特に、電極ピッチが120μm以下の領域では、ワイヤーボンダー自身の精 度が安定していても、ボンディング座標の入力時及び修正時に、データの誤入力 ,誤修正が発生し易くなるので、ボンディングズレが発生し易くなる。この様子 を図9に示す。 It was mentioned in the previous section that if the electrode pitch is reduced using the conventional electrode structure, the margin for bonding displacement will decrease and the risk of short-circuiting between adjacent electrodes will increase. In particular, in the area where the electrode pitch is 120 μm or less, even if the accuracy of the wire bonder itself is stable, erroneous input of data and erroneous correction are likely to occur at the time of inputting and correcting the bonding coordinates, so that the bonding deviation occurs. It tends to occur. This is shown in FIG.

【0012】 図9は、ワイヤーボンダー画面上に写し出されたLSIの電極部の様子である 。クロスマーク7は、ボンディング座標の入力及び修正の際に位置をワイヤーボ ンダー側のICメモリ、もしくは他の記憶装置に記憶させるための指標となるも のである。FIG. 9 shows a state of the electrode part of the LSI projected on the wire bonder screen. The cross mark 7 serves as an index for storing the position in the IC memory on the wire bonder side or another storage device when the bonding coordinates are input and corrected.

【0013】 電極ピッチ(パッドピッチ)が120μm以下になると、図に示すように電極 間隔1−3が分離できず、画面上、横方向の位置精度が通常±5μmに対して約 ±10μmと悪化し、これによって図10に示した隣接電極間でのショートが発 生するという問題があった。When the electrode pitch (pad pitch) is 120 μm or less, the electrode interval 1-3 cannot be separated as shown in the figure, and the positional accuracy in the lateral direction on the screen is deteriorated to about ± 10 μm as compared with ± 5 μm. However, this causes a problem that a short circuit occurs between the adjacent electrodes as shown in FIG.

【0014】 これを防止する従来技術としては、図11に示すように開孔部内の露出金属部 に段差を設けたターゲットマーク1−4を入れて、クロスマークで座標入力・修 正する際の位置精度を確保する事例がある(特願平3−006147号)。As a conventional technique for preventing this, as shown in FIG. 11, when a target mark 1-4 having a step is provided on an exposed metal portion in an opening portion and a coordinate is inputted / corrected by a cross mark, There is a case to secure the position accuracy (Japanese Patent Application No. 3-006147).

【0015】 しかしながら、露出金属部は、ウェットエッチングによって表面に凹凸が付け られているため、ワイヤーボンダーの画面上では、コントラストが低下し、明瞭 にターゲットマーク14を識別することができず、十分な効果は得られない。However, since the surface of the exposed metal portion is roughened by wet etching, the contrast is lowered on the screen of the wire bonder, and the target mark 14 cannot be clearly discriminated. No effect.

【0016】 本考案の目的は、ボンディング座標の入力・修正の際のバラツキを減少させて 、ボンディングズレ量を低減することにより、ボンディング歩留りの向上を図る 半導体装置の電極構造を提供することにある。An object of the present invention is to provide an electrode structure of a semiconductor device, which reduces variations in inputting / correcting bonding coordinates and reduces the amount of bonding deviation, thereby improving the bonding yield. ..

【0017】[0017]

【課題を解決するための手段】[Means for Solving the Problems]

前記目的を達成するため、本考案に係る半導体装置の電極構造においては、電 極金属膜上の絶縁膜に開孔部を有し、電極金属膜の一部を露出させる電極構造で あって、 電極金属膜の端部をスクライブ線方向に直角に引き出した突出パターンを有す るものである。 In order to achieve the above-mentioned object, an electrode structure of a semiconductor device according to the present invention is an electrode structure having an opening in an insulating film on an electrode metal film and exposing a part of the electrode metal film, It has a protruding pattern in which the end portion of the electrode metal film is drawn out at a right angle to the scribe line direction.

【0018】 また、前記突出パターン内に、スクライブ線に対して直角方向にスリットを設 ける構造を有するものである。In addition, a structure is provided in which a slit is provided in the protrusion pattern in a direction perpendicular to the scribe line.

【0019】[0019]

【作用】[Action]

電極金属膜の端部に、スクライブ線方向に引き出した突出パターンを有してい る。この突出パターンを有することにより、電極間隔の不明瞭な120μmピッ チ以下の電極ピッチにおいても、ボンディング座標の入力及び修正時の位置精度 を5μm以下に確保する。 At the end of the electrode metal film, there is a protruding pattern drawn out in the scribe line direction. By having this protruding pattern, the positional accuracy at the time of inputting and correcting the bonding coordinates is secured to 5 μm or less even at an electrode pitch of 120 μm pitch or less where the electrode interval is unclear.

【0020】[0020]

【実施例】【Example】

次に本考案について図面を用いて説明する。 Next, the present invention will be described with reference to the drawings.

【0021】 (実施例1)図1は、本考案の実施例1に係る半導体装置の電極構造を示す平 面図である。(Embodiment 1) FIG. 1 is a plan view showing an electrode structure of a semiconductor device according to Embodiment 1 of the present invention.

【0022】 図1において、スクライブ線3の近傍に、スクライブ線3と平行方向に電極金 属膜1が所望の数だけ設けられている。電極金属膜1上の絶縁膜には、開孔部2 が設けられており、電極金属膜1の一部が外部に露出する構造をとっている。そ の外部に露出した露出金属1−1には、あらかじめウェットエッチング法等の処 理によって表面にわずかな凹凸が形成されている。開孔部2の形状は矩形であり 、スクライブ線3と平行な辺を開孔幅2−1、垂直な辺を開孔長2−2と称する 。In FIG. 1, a desired number of electrode metal films 1 are provided in the vicinity of the scribe line 3 in a direction parallel to the scribe line 3. An opening 2 is provided in the insulating film on the electrode metal film 1 so that a part of the electrode metal film 1 is exposed to the outside. The exposed metal 1-1 exposed to the outside has slight irregularities formed on its surface in advance by a process such as a wet etching method. The shape of the opening 2 is rectangular, the side parallel to the scribe line 3 is called the opening width 2-1, and the vertical side is called the opening length 2-2.

【0023】 一方、電極金属膜1は、スルーホール5等を介して内部配線パターン4と電気 的に接続され、図示していないLSI内部の電気回路に導かれている。On the other hand, the electrode metal film 1 is electrically connected to the internal wiring pattern 4 via the through holes 5 and the like, and is led to an electric circuit inside the LSI (not shown).

【0024】 突出パターン1−5は、電極金属膜1端部のスクライブ線側からスクライブ線 に対して直角方向に引き出される。突出パターン1−5を引き出す部位は、電極 幅に対して中央の部分である。The protruding pattern 1-5 is drawn out from the end of the electrode metal film 1 on the scribe line side in a direction perpendicular to the scribe line. The part where the protrusion pattern 1-5 is pulled out is the central part with respect to the electrode width.

【0025】 上述した構成の電極構造において、電極ピッチ(パッドピッチ)が120μm 以下のサンプルを、ワイヤーボンダーのカメラでとらえると、画面上は図2のよ うな画像となる。When a sample having an electrode pitch (pad pitch) of 120 μm or less is captured by a wire bonder camera in the electrode structure having the above-described configuration, an image as shown in FIG. 2 is displayed on the screen.

【0026】 電極間隔1−3を識別することは困難であるが、突出パターン1−5上にクロ スマーク7を合わせることにより、突出パターン1−5が無い時に比べて、座標 入力,修正による位置精度は5μm程度改善される。It is difficult to identify the electrode interval 1-3, but by aligning the cross mark 7 on the protruding pattern 1-5, the position by coordinate input and correction can be compared with the case where the protruding pattern 1-5 is not present. The accuracy is improved by about 5 μm.

【0027】 (実施例2)図3は、本考案の実施例2に係る半導体装置の電極構造を示す平 面図である。主要構成部は実施例1と同じであるので、ここでは相違点だけを述 べる。(Embodiment 2) FIG. 3 is a plan view showing an electrode structure of a semiconductor device according to Embodiment 2 of the present invention. Since the main components are the same as in the first embodiment, only the differences will be described here.

【0028】 実施例2において、突出パターン1−5の中央部には、スリット1−6が設け てある。スリット1−6の根元部は、電極金属膜1の端部の電極幅中央部に位置 し、またスリット1−6の幅は、3〜5μm程度にする。In the second embodiment, a slit 1-6 is provided at the center of the protruding pattern 1-5. The root of the slit 1-6 is located at the center of the electrode width at the end of the electrode metal film 1, and the width of the slit 1-6 is about 3 to 5 μm.

【0029】 上述した構成の電極構造においては、電極ピッチ(パッドピッチ)が120μ m以下のサンプルを、ワイヤーボンダーのカメラでとらえると、画面上は図4の ような画像となる。この場合も、電極間隔1−3を識別することは難しいが、突 出パターン1−5のスリット1−6とクロスマーク7とを一致させることにより 、突出パターンが無い時に比べて、座標入力,修正時の位置精度は5〜10μm 程度改善される。In the electrode structure having the above-described structure, when a sample having an electrode pitch (pad pitch) of 120 μm or less is captured by a wire bonder camera, an image as shown in FIG. 4 is displayed on the screen. Also in this case, it is difficult to identify the electrode interval 1-3, but by matching the slits 1-6 of the protrusion pattern 1-5 with the cross mark 7, the coordinate input, The position accuracy at the time of correction is improved by about 5 to 10 μm.

【0030】 (実施例3)図5は、本考案の実施例3に係る半導体装置の電極構造を示す平 面図である。主要構成部は実施例1及び実施例2と同一であるので、ここでは相 違点だけを述べる。(Third Embodiment) FIG. 5 is a plan view showing an electrode structure of a semiconductor device according to a third embodiment of the present invention. Since the main components are the same as in the first and second embodiments, only the differences will be described here.

【0031】 実施例3において、突出パターン1−5には、スリット1−6と、スリット1 −6の先端を閉塞し、かつ鋭角状に形成された先鋭部1−7とが設けてある。In the third embodiment, the protrusion pattern 1-5 is provided with the slit 1-6 and the sharpened portion 1-7 that closes the tip of the slit 1-6 and is formed in an acute angle.

【0032】 スリット1−6の根元部は、電極金属膜1の端部の電極幅中央部に位置し、ま たスリット1−6の幅は、3〜5μm程度にする。The base of the slit 1-6 is located at the center of the electrode width at the end of the electrode metal film 1, and the width of the slit 1-6 is about 3 to 5 μm.

【0033】 一方、開孔部2の中央2−3から先鋭部1−7までの距離L(図5参照)は、 使用するワイヤーボンダー装置のクロスマーク7の交点部7aから上端部7bま での距離(図6参照)と、画面上で一致する距離に設定する。On the other hand, the distance L (see FIG. 5) from the center 2-3 of the opening 2 to the sharpened portion 1-7 is from the intersection 7a to the upper end 7b of the cross mark 7 of the wire bonder device used. Is set to a distance that matches the distance (see FIG. 6) on the screen.

【0034】 上述した構成の電極構造において、電極ピッチ(パッドピッチ)が120μm 以下のサンプルを、ワイヤーボンダーのカメラで捕らえ、画面に写し出したもの が図6である。この場合も、電極間隔1−3の識別は困難であるが、スリット1 −6とクロスマーク7とを一致させることにより、突出パターンが無い時に比べ て、座標入力,修正時の位置精度は、5〜10μm程度改善される。FIG. 6 shows a sample having an electrode pitch (pad pitch) of 120 μm or less captured by a wire bonder camera and projected on the screen in the electrode structure having the above-described configuration. Also in this case, it is difficult to identify the electrode interval 1-3, but by making the slits 1-6 and the cross mark 7 coincide with each other, the positional accuracy at the time of coordinate input and correction is better than that when there is no protruding pattern. It is improved by about 5 to 10 μm.

【0035】 さらに、電極の奥行き方向についても、クロスマーク7の上端部7bと突出パ ターン1−5の先鋭部1−7とを一致させることで位置精度が確保できるため、 トータル精度は2.5μm程度となり、ファインピッチボンディングを安定して 行える。Further, also in the depth direction of the electrode, since the positional accuracy can be secured by aligning the upper end portion 7b of the cross mark 7 with the sharpened portion 1-7 of the protruding pattern 1-5, the total accuracy is 2. It becomes about 5 μm, and fine pitch bonding can be performed stably.

【0036】[0036]

【考案の効果】[Effect of the device]

以上説明したように本考案は、電極金属膜の端部をスクライブ線方向に引き出 した突出パターンを有し、この突出パターンの引き出し部位は電極金属膜端部の 電極幅中央付近で、かつ引き出し方向をスクライブ線と直角方向としたことによ り、電極間隔の不明瞭な120μmピッチ以下の電極ピッチにおいても、ボンデ ィング座標の入力及び修正時の位置精度が5μm以下に確保できる。これによっ て、ボンディングズレ不良の低減が行え、歩留り向上が図られるという効果を有 する。 As described above, the present invention has the protruding pattern in which the end portion of the electrode metal film is drawn out in the scribe line direction, and the lead-out portion of this protruding pattern is near the center of the electrode width of the electrode metal film end and Since the direction is perpendicular to the scribe line, the positional accuracy at the time of inputting and correcting the bonding coordinates can be secured to 5 μm or less even at an electrode pitch of 120 μm or less where the electrode spacing is unclear. This has the effect of reducing bonding misalignment defects and improving yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の実施例1を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.

【図2】ワイヤーボンダーのCRT画面上に写し出され
た実施例1の画像を示す図である。
FIG. 2 is a diagram showing an image of Example 1 displayed on a CRT screen of a wire bonder.

【図3】本考案の実施例2を示す平面図である。FIG. 3 is a plan view showing a second embodiment of the present invention.

【図4】ワイヤーボンダーのCRT画面上に写し出され
た実施例2の画像を示す図である。
FIG. 4 is a diagram showing an image of Example 2 displayed on a CRT screen of a wire bonder.

【図5】本考案の実施例3を示す平面図である。FIG. 5 is a plan view showing a third embodiment of the present invention.

【図6】ワイヤーボンダーのCRT画面上に写し出され
た実施例3の画像を示す図である。
FIG. 6 is a diagram showing an image of Example 3 displayed on a CRT screen of a wire bonder.

【図7】従来例を示す平面図である。FIG. 7 is a plan view showing a conventional example.

【図8】ワイヤー方向と電極形状を揃えた従来例を示す
平面図である。
FIG. 8 is a plan view showing a conventional example in which the wire direction and the electrode shape are aligned.

【図9】ワイヤーボンダーのCRT画面上に写し出され
た図7の従来例における画像を示す図である。
FIG. 9 is a diagram showing an image in the conventional example of FIG. 7 projected on a CRT screen of a wire bonder.

【図10】ボンディングズレによる隣接電極間ショート
不良を示す概念図である。
FIG. 10 is a conceptual diagram showing a short circuit defect between adjacent electrodes due to a bonding shift.

【図11】露出金属部にターゲットマークを入れた従来
例を示す平面図である。
FIG. 11 is a plan view showing a conventional example in which a target mark is provided on an exposed metal portion.

【符号の説明】[Explanation of symbols]

1 電極金属膜 1−1 露出金属 1−2 電極幅 1−3 電極間隔 1−4 ターゲットマーク 1−5 突出パターン 1−6 突出パターンのスリット 1−7 突出パターンの先鋭部 2 開孔部 2−1 開孔幅 2−2 開孔長 3 スクライブ線 4 内部配線パターン 5 スルーホール 6 ワイヤー 7 クロスマーク DESCRIPTION OF SYMBOLS 1 Electrode metal film 1-1 Exposed metal 1-2 Electrode width 1-3 Electrode spacing 1-4 Target mark 1-5 Projection pattern 1-6 Slit of projection pattern 1-7 Sharp tip 2 of projection pattern 2 Opening 2- 1 Opening width 2-2 Opening length 3 Scribing line 4 Internal wiring pattern 5 Through hole 6 Wire 7 Cross mark

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 電極金属膜上の絶縁膜に開孔部を有し、
電極金属膜の一部を露出させる電極構造であって、 電極金属膜の端部をスクライブ線方向に直角に引き出し
た突出パターンを有することを特徴とする半導体装置の
電極構造。
1. An opening is formed in an insulating film on an electrode metal film,
An electrode structure for exposing a part of an electrode metal film, the electrode structure of a semiconductor device having a protruding pattern in which an end portion of the electrode metal film is drawn out at a right angle to a scribe line direction.
【請求項2】 前記突出パターン内に、スクライブ線に
対して直角方向にスリットを設ける構造を有することを
特徴とする請求項1に記載の半導体装置の電極構造。
2. The electrode structure of a semiconductor device according to claim 1, wherein a slit is provided in the protrusion pattern in a direction perpendicular to the scribe line.
JP086335U 1991-09-26 1991-09-26 Electrode structure of semiconductor device Pending JPH0529143U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP086335U JPH0529143U (en) 1991-09-26 1991-09-26 Electrode structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP086335U JPH0529143U (en) 1991-09-26 1991-09-26 Electrode structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0529143U true JPH0529143U (en) 1993-04-16

Family

ID=13883976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP086335U Pending JPH0529143U (en) 1991-09-26 1991-09-26 Electrode structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0529143U (en)

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