JPH05291391A - Method of forming element isolating structure in semiconductor device - Google Patents

Abstract

PURPOSE:To form an element isolating layer having an extremely small width and form a minute element isolation structure in which a buried layer does not come up at all in a method of forming an element isolation (PN isolation) which is formed in a semiconductor device such as a bipolar type semiconductor device or the like. CONSTITUTION:An insulating film 2 is formed on a substrate 1 and an opening part corresponding to an element forming region 10 is provided therein, and a P<+> type side wall 5a is formed on the side wall of the insulating film 2 provided with the opening part 10, and if the remaining insulating film 2 is removed, only the side wall 5a is left on the substrate 1, and if an N-type single crystal grows up to a height of the side wall 5a, the side wall 5a becomes an element isolation layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to element isolation in semiconductor devices, particularly bipolar semiconductor devices (particularly P
N separation).

[0002]

2. Description of the Related Art Various structures are used for a conventional element isolation structure. Particularly, a typical structure and manufacturing method for a bipolar semiconductor device are shown in FIGS. 3 to 4 and described below.

First, a buried N ⁺ layer 3 for reducing collector resistance is formed on a P-type semiconductor substrate 1, and an oxide film 2 is formed on the surface (FIG. 3A). Next, P for PN separation
⁺ To form a buried layer (5a described later), again oxide film 4
(FIG. 3 (b)), the portion where the P ⁺ layer 5a is to be formed is opened, and impurities are injected and diffused from the opening 5 to form the P ⁺ layer 5a (FIG. 3 (c)). .. Next, the surface insulating film (oxide film) 2 is entirely peeled off to prepare for epitaxial layer growth (FIG. 3D).

Next, the epitaxial layer 6 is grown by a known epitaxial technique. At this time, the N ⁺ buried layer 3,
And P ⁺ buried layer 5a are both auto-doped.
Diffuse upward as in (e). Then from the top again P ⁺
An oxide film 7 for forming a layer is formed. Then, in order to form the upper P ⁺ layer, a portion 5b is opened directly above the layer 5a by a known photolithography (hereinafter abbreviated as photolithography) / etching technique, impurities are implanted, and a diffusion layer 5c is obtained. That is, this layer 5c is formed right above the lower buried layer 5a layer (FIG. 4 (f)).

Next, when annealing is performed by a known diffusion technique, the 5a and 5c layers grow and connect to form a 5d layer, and this 5d layer serves as an element isolation layer (FIG. 4 (g)).

Next, an insulating film 8 for forming an element is formed (FIG. 4 (h)).

A cross-sectional view in which a transistor is actually formed is shown in FIG. Reference numeral 9a is a base layer, 10a is an emitter layer, 11a is a collector layer, and 9, 10, 11 are contact layers, respectively.

[0008]

Although there are various other element isolation structures, the problems of the above-mentioned conventional example will be described.

In order to miniaturize the element isolation structure, FIG.
For example, it is necessary to narrow the interval between the isolation (element isolation) layer 5d and the buried diffusion layer 3 shown in the sectional view of (i). Further, in order to narrow the area A between the transistor formation region 9a and the buried diffusion layer 3, it is necessary to reduce the areas of the base layer 9a, the emitter layer 10a, and the collector layer 11a. Breakdown voltage, transistor collector-base breakdown voltage BVCBO,
A desired value cannot be obtained for the breakdown voltage such as the collector-emitter breakdown voltage BVCEO and the emitter-base breakdown voltage BVEBO.
Further, due to various heat treatments, in particular, the buried layer floated up to the isolation layer and spread laterally, which was a major obstacle to miniaturization.

According to the present invention, the expansion of the isolation described above, the floating of the buried layer is minimized, the epitaxial layer is formed thin, and the isolation width is self-aligned to the minimum width. The purpose of the present invention is to obtain a fine isolation structure without raising the N ⁺ layer.

[0011]

To solve the above problems, the present invention has a means for forming an isolation layer by a sidewall by self-alignment in the formation of element isolation, and a damage layer (metal contamination) left by etching at that time. Layers)
Is provided, a means for forming an overall epitaxial layer thereon, and a means for removing a damage layer, a metal contamination layer, etc. after the entire surface is etched back through a resist.

[0012]

As described above, according to the present invention, since the isolation layer is formed by the sidewall, it is possible to form a fine element isolation layer without the subsequent heat treatment. Therefore, there is no upward diffusion from the buried layer and lateral diffusion from the isolation portion, and the thickness of the epitaxial layer can be reduced. Therefore, a fine element isolation structure becomes possible.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A manufacturing process of an embodiment of the present invention will be described with reference to FIGS.
And will be described step by step below. First, an N ⁺ buried layer 3 for reducing collector resistance is formed on a P-type semiconductor substrate 1,
An insulating film (oxide film in this embodiment) 2 is formed on the surface (FIG. 1A).

Next, a resist pattern 4 having an opening corresponding to the element forming region 10 is formed by a known photolithography technique (FIG. 1B). Then, using the resist 4 as a mask, the insulating film 2 is formed by a known dry etching technique to form an opening corresponding to the element formation region 10. At the end of etching, light etching is performed to remove the damaged layer (the surface becomes rough) on the surface of the substrate 1.

Next, the resist 4 is removed, and the epitaxial layer 5 is formed by a known epitaxial growth technique. At this time, the epitaxial layer 5 is formed as a P ⁺ type layer by forming a layer of silane SiH ₄ and diborane B ₂ H ₆ . Further, in this case, as described above, P ⁺ is formed on the element forming region 10.
Although the layer 5 is formed, polysilicon 5b is formed on the insulating film 2 which is an oxide film (FIG. 1C).

Next, the entire surface is dry-etched by using a known etch-back technique so that the P ⁺ layer of the sidewall layer 5a can be obtained. The width of this layer 5a is determined by the height of the insulating film 2 (FIG. 1 (d)).

After that, when the insulating film 4 is wet-etched, only the P ⁺ layer 5a of the sidewall remains as an element isolation layer on the substrate 1 (FIG. 2 (e)). Next, SiH ₄ + PH ₃ is flown by a known epitaxial technique to grow a single crystal layer (here, N type) 6 (FIG. 2F).

Next, a resist 7 is applied in order to remove the layer 6a grown and left on the element isolation layer 5a (see FIG. 2).
(G)) When the entire surface is etched back (dry etching) (after etching back, light etching is always performed), a complete element isolation structure can be obtained. Thereafter, as shown in FIG. 2H, an insulating film 8 for forming elements is formed to complete the element isolation.

[0019]

As described in detail above, according to the present invention, since the isolation layer is formed by the sidewall, it is possible to form a fine element isolation layer without the subsequent heat treatment. Therefore, there is no upward diffusion from the buried layer and lateral diffusion from the isolation portion, and the thickness of the epitaxial layer can be reduced. Therefore, a fine element isolation structure becomes possible and high integration can be expected.

Further, after each dry etching, a light etching is performed to remove the damaged layer and metal contamination, so that further improvement in characteristics is expected.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a second embodiment of the present invention.

FIG. 3 Conventional example (No. 1)

FIG. 4 Conventional example (No. 2)

[Explanation of symbols]

1 substrate 2 insulating film 3 N ⁺ burying layer 4 pattern 5 P ⁺ layer 5a sidewall

Claims (1)

[Claims] 1. (a) An insulating film is formed on a semiconductor substrate,
A step of forming an opening corresponding to an element formation region separated by an element isolation layer in the insulating film, (b) a step of forming a layer of the first conductivity type at least on the opening of the insulating film, (c) A step of forming a sidewall of the first conductivity type layer on an opening side wall of an insulating film having the opening; (d) a step of removing the remaining insulating film; (e) a substrate surface A step of growing a second-conductivity-type layer and flattening the second-conductivity-type layer so that the second-conductivity-type layer does not remain on the sidewalls; and Forming method.