JPH052892A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To relatively simplify the change of the characteristic such as the power consumption and the operation speed in the semiconductor memory device without changing the mask pattern at the time of the production. CONSTITUTION:A control circuit TCONT activating and inactivating an internal circuit based on a chip select signal CS is equipped with a level forced circuit making an activated control signal phi1 to be supplied to the specific internal circuit such as an address buffer ABUF to an activated level regardless of the chip select signal CS. This level forced circuit is composed of a CMOS transfer gate TG1 and MOSFETQn 3 and the direction of an operation state for this level forced circuit is supplied from the fuse program circuit FPGM. In the disconnection state of a fuse FUSE included in the fuse program circuit, the address buffer ABUF is activated at all times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for selecting functions relating to power consumption and operating speed of a semiconductor memory device,
For example, the present invention relates to a technique effectively applied to a static RAM (random access memory).

[0002]

2. Description of the Related Art There is a correlation between the power consumption of a semiconductor integrated circuit such as a static RAM and the operating speed, and in order to increase the operating speed, the power consumption of the amplifier circuit is increased to increase the driving capability or address. In order to increase the response speed to signal changes and shorten the access time, the address buffer can be kept active even in the standby state. When changing characteristics such as power consumption or operating speed in a semiconductor integrated circuit, the wiring pattern can be changed or the circuit configuration can be partially changed. In such a case, the semiconductor integrated circuit is manufactured. It is necessary to change the mask pattern used in various processes.
Incidentally, as an example of the document describing the static RAM, "LSI" issued by Ohmsha, Ltd. on November 30, 1984 is available.
Handbook, pp. 106-109.

[0003]

However, even if the basic circuit configuration is the same, it is necessary to change the mask pattern in order to change the characteristics. Therefore, it is necessary to change the design or manufacture a new mask for that purpose. There has been a problem that it takes a considerable amount of time and the characteristics of the same kind of semiconductor integrated circuit cannot be easily changed.

An object of the present invention is to provide a semiconductor memory device in which characteristics such as overall power consumption and operating speed can be changed relatively easily without changing a mask pattern at the time of manufacturing. Especially.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a control circuit for activating and deactivating an internal circuit based on a first control signal supplied for selecting an operation of a semiconductor memory device such as a chip select signal is provided with an address buffer. Is provided with a level forcing circuit for forcing an activation control signal to be supplied to a specific internal circuit to an activation level irrespective of the first control signal, and instructing an operating state to the level forcing circuit. It is to be given from.

When the circuit for forming the voltage obtained by stepping down the power supply voltage as the operating voltage of the address buffer or the like is further set as the specific internal circuit, the internal circuit is always activated to step down the power supply voltage and First step-down circuit that consumes less power and a second step-down circuit as the activation control signal
In response to the activation of the address buffer, including the second step-down circuit which receives the activation control signal to step down the power supply voltage and consumes a relatively large amount of power, it is necessary for the operation of the address buffer. Guarantee the supply of electric current.

As the instructing means, a fuse program circuit whose output state changes depending on whether or not the fuse is blown can be used.

[0010]

According to the above means, when it is desired to prioritize the speeding up of the access speed even if the power consumption increases, a specific internal circuit such as an address buffer is placed in a standby state (first It is activated even in the non-selected state of the operation by the 1 control signal). This shortens the time from the selected state of the operation to the confirmation of the selected operation of the memory cell while increasing the power consumption by constantly reflecting the change of the address signal on the output of the address buffer,
Allows selection of fast access.

When it is desired to give priority to low power consumption even if the access speed is sacrificed to some extent, a specific internal circuit such as an address buffer is activated based on the level of the first control signal based on an instruction from the instruction means. . This enables a specific internal circuit such as an address buffer to be activated in response to the selected state of the operation according to the first control signal, and the access speed is slowed down to some extent, while priority is given to low power consumption.

Lowering the operating voltage of an internal circuit, such as an address buffer, which is expected to consume a relatively large amount of power, contributes to a low power consumption, and further, a relatively low power consumption. The two-step configuration in which the step-down circuit and the second step-down circuit having relatively large power consumption are adopted and the activation control of the second step-down circuit is further promoted to reduce the power consumption in the standby state. At this time, in the constant activation control of the specific internal circuit according to the instruction of the instruction means, the second step-down voltage circuit and the address buffer are synchronously controlled so that the current supply required for the operation of the address buffer, that is, the high-speed access is performed. Act to assure.

[0013]

FIG. 1 shows a static RAM according to an embodiment of the present invention. This static RAM is formed on a single semiconductor substrate such as a silicon substrate by a known MOS type semiconductor integrated circuit manufacturing technique, although not particularly limited thereto. In the figure, MCA is a memory cell array, and a plurality of static memory cells MC are arranged in a matrix in this memory cell array MCA. For example, when each memory cell MC is a 6-transistor type of complementary MOS (hereinafter also referred to as CMOS) circuit type, a static type latch in which one input of one pair of CMOS inverters is cross-coupled to the other output is mainly used. , N-channel type selection MOS for both input / output terminals
It is formed by combining FETs. The data input / output terminal of the memory cell MC is, for example, the drain electrode of both selection MOSFETs, and the selection terminal of the memory cell MC is the selection MOSF.
It is used as the gate electrode of ET. The selection terminals of the memory cells MC arranged in a matrix are word lines WL corresponding to each row.
And the data input / output terminals are coupled to the complementary data lines DL and DL * corresponding to each column. In the figure, one memory cell MC and a pair of complementary data lines DL,
DL * (the symbol * means inversion or low enable) and only one word line WL are shown, but in reality, there are a large number of complementary data lines arranged crosswise in the XY directions. A large number of memory cells MC are arranged in a matrix at positions intersecting with the word lines.

ABUF is an address input terminal A0 to A
n is an address buffer which outputs the address signal supplied from n as an internal complementary address signal and outputs it. A pre-address decoder PADEC and an address decoder ADEC for decoding the address signal output thereby are provided in the subsequent stage of the address buffer ABUF. Are placed. The address decoder ADE is not particularly limited.
By the output of C, the word line is selected, and the complementary data line is selected via a column switch circuit (not shown), and a memory cell having a predetermined number of bits is selected. The selected memory cell is made conductive by the write driver WD and the sense amplifier SA, and the write driver WD that receives write data in the write operation writes the data in the selected memory cell, and the read operation in the selected memory cell. Read data is amplified by the sense amplifier SA. The data amplified by the sense amplifier SA is output to the outside via the output buffer DOBUF. The write data is given to the write driver WD from the input buffer DIBUF. An input terminal of the input buffer DIBUF and an output terminal of the output buffer DOBUF have their data input / output terminals commonly connected to D1 to Dm for each corresponding bit.

TCONT is a controller for generating an internal operation control signal of the static RAM. The controller TCONT is not particularly limited, but as an external access control signal, a chip select signal CS for instructing chip selection for selecting the operation of the static RAM.
* (An example of a first signal), a write enable signal WE * for instructing data writing, and an output enable signal OE * for instructing external output of data are supplied, and further, a fuse program circuit FPGM (an example of an instructing means) described later. Signal S, S * from The controller TCONT generates internal control signals φ1 to φ5 and the like based on the levels of the input signals and combinations of the levels, and outputs the internal control signals φ1 to φ5 to a predetermined circuit block.

The static RAM of this embodiment operates by receiving the ground voltage GND of a relatively low level and the power supply voltage Vdd of a relatively high level. The ground potential GND is commonly applied to each circuit. The power supply voltage Vdd is commonly applied to the circuits other than the pre-address decoder PADEC and the address decoder ADEC, but the step-down potential Vgd generated by the step-down circuit GDV is applied as an operating voltage to the pre-address decoder PADEC and the address decoder ADEC. To be This is its pre-address decoder PA
This is to reduce the power consumption by the DEC and the address decoder ADEC.

In FIG. 2, the address buffer ABUF,
An example of the controller TCONT and the fuse program circuit FPGM is shown.

FIG. 2 shows a typical configuration for 1 bit.
The address buffer ABUF of inputs the bit Ai included in the address signal and outputs the even-numbered inverters INV1 and INV1.
Internal complementary address signals ai, ai * are output through INV2, INV3, INV4 and odd-numbered stage inverters INV1, INV2, INV3, INV5. Each of the inverters is constructed in a CMOS inverter type in which a P-channel type MOSFET and an N-channel type MOSFET are connected in series. Especially, the first stage inverter INV1
Is a basic configuration in which a P-channel type MOSFET Qp1 and an N-channel type MOSFET Qn1 are connected in series, and an N-channel type MOSFET Qn2 connected in parallel to the MOSFET Qn1, an output terminal and a MOSFET Qp.
P-channel type MOS interposed between the drain and the drain
It has FET Qp2 and these MOSFETs Qp2, Qn
2 is a control signal φ output from the controller TCONT
It is switch-controlled by 1. The control signal φ1 is used as an activation control signal for the address buffer ABUF (an example of a first activation control signal), and when it is set to a low level, the first-stage inverter INV1 can output an inverted signal of the input, which causes The address buffer ABUF is activated. When the control signal φ1 is set to the high level, the first stage inverter I
The output of NV1 is forced to the ground potential GND through the MOSFET Qn2 in the ON state, and the address buffer ABUF is output.
Is deactivated.

In the controller TCONT, the control signal φ1 is supplied with an inverter INV6 for inputting a chip select signal CS *, an inverter INV7 directly connected to the output of the inverter INV7, a CMOS transfer gate TG1,
And inverters INV8 and INV9. In the path from the output of the CMOS transfer gate TG1 to the input of the inverter INV8, an N-channel MOSFET whose source is connected to the ground potential GND is provided.
The drain of Qn3 is coupled. N-channel type MOSFE constituting the CMOS transfer gate TG1
TQn4 is switch-controlled by the control signal S, and CM
The P-channel type MOSFET Qp4 and the MOSFET Qn3 forming the OS transfer gate TG are switch-controlled by the control signal S *. Therefore, when the control signal S is set to the high level and the control signal S * is set to the low level, the control signal φ1 is set to the low level in response to the low level (chip selection level) of the chip select signal CS *. The address buffer ABUF is activated. On the other hand, in the inverted state of the control signals S and S *, the control signal φ1 is always set to the low level regardless of the chip selection state, and the address buffer is activated even in the standby state.

The CMOS transfer gate TG1 and the MOSFET Qn3 are an example of a level forcing circuit for forcing the signal φ1 for controlling activation of the address buffer ABUF to the activation level of the address buffer ABUF regardless of the chip select signal CS *.

The control signal S is output from the final stage of the inverters INV12 to INV14 connected in series, and the control signal S * is output from the inverter INV15 which receives the output of the inverter INV12. The input of inverter INV12 is coupled to the output node of the resistor divider circuit. This resistance voltage divider circuit includes a fuse FUSE and an N-channel type MOSF whose gate is coupled to the power supply voltage Vdd.
ETQn5, two N-channel MOSFETs Qn of the so-called diode connection type in which the gate is coupled to the drain
6 and Qn7 are connected in series. The fuse FUSE functions as a resistance element in the non-cut state,
It outputs a divided voltage that is considered to be high level to the input of the inverter INV12. When the fuse FUSE is blown, the input of the inverter INV12 is fixed at low level. At this time, the output of the inverter INV12 is received by the gate and switch-controlled N-channel type MOSF
The ETQn8 performs feedback control so that once the output of the inverter INV12 is set to the high level, that state is maintained.

Therefore, in the circuit of FIG. 2, the control signal φ1 is forced to the low level regardless of the chip select signal CS * when the fuse FUSE is not cut, and the address buffer ABU is maintained even in the standby state.
Activate F. As a result, the change in the address signal is always reflected in the output of the address buffer ABUF.
When the chip selection state is set from the standby state, the pre-address decoder PADEC can immediately output a selection signal according to the address signal at that time, which enables high-speed access. However, since the address buffer ABUF operates even in the standby state, the power consumption increases relatively. On the other hand, when the fuse FUSE is in the cut state, the level of the control signal φ1 changes according to the level of the chip select signal CS *, so that the address buffer ABUF changes the chip select signal CS * from the high level to the low level. As a result, the address signal at that time can be input only after the control signal φ1 which is inverted to the low level is transmitted to the first input stage, and the access time becomes slower than in the above case. In the fuse FUSE cut-off state, the address buffer ABUF is inactivated in the standby state, so that the power consumption is reduced by that amount as compared with the above case.

In the controller TCONT, CMOS inverters INV10 and INV11 connected in series to the output of the inverter INV6 form the control signal φ2. The control signal φ2 is supplied to the step-down circuit GDV, but passes through a signal generation logic (not shown) as a basic signal for generating the other control signals φ3 to φ5.

FIG. 3 shows an example of the step-down circuit GDV. The step-down circuit GDV shown in the figure includes a first step-down circuit GDV1, a second step-down circuit GDV2, and a control circuit GDV.
It is composed of C.

The first step-down circuit GDV1 is a circuit for stepping down the power supply voltage Vdd so as to relatively reduce power consumption, and a reference voltage generating circuit for generating a reference voltage by using the threshold voltage of the MOSFET. It is composed of RVG and a differential amplifier circuit AMP1. Reference voltage generation circuit RVG
Is not particularly limited, but using the threshold voltage of the built-in MOSFET, a reference voltage Vref of 3.9 V and a voltage Vthn corresponding to the threshold voltage of the N-channel MOSFET or a voltage slightly higher than the threshold voltage Vthn. And output. The differential amplifier circuit AMP1 includes a pair of N-channel type input MOSFETs Qn11 and Qn12 commonly connected to an N-channel type power switch MOSFET Qn10.
In addition, mainly composed of a configuration in which a current mirror load composed of P-channel MOSFETs Qp10 and Qp11 is connected,
The output of the differential amplifier circuit AMP1 is input M through the depletion type N-channel MOSFET Qn13.
It is configured by feedback connection to the gate of the OSFET Qn12. The gate of the input MOSFET Qn12 serves as the step-down voltage output terminal of the first step-down circuit GDV1 and its output voltage is set to 3.9 volts. The other input M
The reference voltage Vref is applied to the gate of the OSFET Qn11.
And the voltage Vthn is supplied to the gate of the power switch MOSFET Qn10. Therefore, the first step-down circuit GDV1 is always activated, but the conductance of the power switch MOSFET Qn10 is small and the ON resistance thereof is relatively large, so that the differential amplifier circuit AM.
The power consumption of P1 is made relatively low. In other words, the current supply capability of the first step-down circuit GDV1 is made relatively low.

The second step-down circuit GDV2 is the first step-down circuit 1
Is a circuit for stepping down the power supply voltage Vdd by relatively increasing the power consumption so as to supplement the current supply capacity of the above, and is composed of two differential amplifier circuits AMP2 and AMP3. The differential amplifier circuit AMP2 is mainly composed of a pair of N-channel type input MOSFETs Qn21, Qn22 commonly connected to an N-channel type power switch MOSFET Qn20 and a current mirror load composed of P-channel type MOSFETs Qp20, Qp21 connected thereto. The output of the dynamic amplifier circuit AMP2 is used as one input MOSFET Qn2
It is configured by feedback connection to the gate of 2. This input MOSFET
The gate of Qn22 is used as the step-down voltage output terminal of the second step-down circuit GDV2, and is connected to the output terminal of the first step-down circuit GDV1. The reference voltage Vref is supplied to the gate of the other input MOSFET Qn21, and the power switch MO
The gate of the SFET Qn20 has the differential amplifier circuit AMP.
3 outputs are provided. The differential amplifier circuit AMP3 includes a pair of P-channel type input MOSFETs Qp commonly connected to a P-channel type power switch MOSFET Qp30.
31 and Qp32 have N-channel MOSFET Qn3
Mainly composed of a current mirror load composed of 0 and Qn31, the output of the differential amplifier circuit AMP3 is feedback-connected to the gate of one of the input MOSFETs Qp32.
In addition, it can be connected to the ground potential GND through the N-channel MOSFET Qn33. Input MOSFET
The gate of Qp32 is coupled to the gate of the power switch MOSFET Qn20 of the differential amplifier circuit AMP2. The reference voltage Vref is supplied to the gate of the other input MOSFET Qp31, and the power switch MOSFET Qp
A control signal φ6 output from the control circuit GDVC is supplied to the gate of 30 and the gate of the MOSFET Qn33. This control signal φ6 is used as an activation control signal of the differential amplifier circuit AMP3, that is, an activation control signal of the second step-down circuit GDV2 (an example of the second activation control signal), and when it is set to a low level, the differential signal The amplifier circuit AMP3 is activated, and the output thereof activates the differential amplifier circuit AMP2. When the second step-down circuit GDV2 is activated, the differential amplifier circuits AMP2 and AMP3 each output 3.9V.
Try to. At this time, the power switch MOS
The FET Qn20 has a differential amplifier circuit AMP3 at its gate.
, Taking a relatively large conductance,
The current supply capacity of the differential amplifier circuit AMP2 is made relatively large.

The control circuit GDVC is not particularly limited, but CMOS transfer gates TG connected in series are used.
2 and a CMOS inverter INV20, and the drain of a P-channel MOSFET Qp40 whose source is coupled to the power supply voltage Vdd is connected to the input of the inverter INV20. CMOS transfer gate TG2
The control signal S is supplied to the gates of the N-channel type MOSFET Qn40 and the gate of the MOSFET Qp40, and the control signal S * is supplied to the gate of the P-channel type MOSFET Qp41 forming the CMOS transfer gate TG2. The CMOS transfer gate TG2 and the MOSFET Qn40 are another example of a level forcing circuit for forcing the signal φ6 for controlling activation of the step-down circuit GDV to the activation level regardless of the chip select signal CS *.

Therefore, in the circuit of FIG. 3, the control signal φ6 is forced to the low level regardless of the chip select signal CS * when the fuse FUSE is not cut, and the second step-down circuit GDV2 is activated even in the standby state. To do. As a result, the second buffer GDV2 is always activated in response to the constant activation of the address buffer ABUF in the non-cut state of the fuse FUSE, so that the address buffer ABUF which operates in response to the input address signal is operated. Is always supplied with a sufficient current necessary for its operation, which guarantees high-speed access by always activating the address buffer ABUF. However, since the second step-down circuit is activated even in the standby state, the power consumption increases relatively. On the other hand, when the fuse FUSE is in the cut state, the second step-down circuit GDV2 is activated only after being brought into the chip selection state like the address buffer ABUF. Achieve power consumption.

According to the above embodiment, there are the following effects.

(1) In the static RAM of the above-described embodiment, if it is desired to prioritize the speeding up of the access speed even if the power consumption increases, the fuse FUSE is left uncut and the chip is packaged. . In the non-cut state of the fuse FUSE, the control signals φ1 and φ6 are forced to the low level regardless of the chip select signal CS *, and even in the standby state, the address buffer AB.
The UF and the second step-down circuit GDV2 are activated. As a result, the change in the address signal is always caused by the address buffer ABU.
This is reflected in the output of F, and the time from the switching from the standby state to the chip selection state to the confirmation of the memory cell selection operation is shortened, and high-speed access is realized.
Further, at this time, a sufficient current necessary for the operation is constantly supplied to the address buffer ABUF which operates in response to the address signal, thus guaranteeing such high speed access.

(2) In the static RAM of the above embodiment, if it is desired to prioritize reduction of power consumption rather than access speed, the fuse FUSE is cut off and the chip is packaged. In the blown state of the fuse, the levels of the control signals φ1 and φ6 change according to the level of the chip enable signal CS, so that the address buffer ABUF and the second step-down circuit GDV2 are in the chip select state by the chip select signal CS *. It is activated only when instructed, and the access time is delayed by the operation delay until activation, but power consumption can be reduced because there is no unnecessary current consumption in the standby state.

(3) Due to the above effects, the characteristics of the static RAM such as power consumption and operating speed can be changed relatively easily without changing the mask pattern at the time of manufacturing.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the target controlled by the control signal φ1 is not limited to the address buffer, but may be the input buffer DIBUF. Further, similar control may be performed on the sense amplifier SA. For example, the number of serial operation stages of the sense amplifier can be controlled according to the level of the activation control signal, or the circuit having high and low drive capability can be switched and controlled. Further, instead of the fuse program circuit FPGM, the signals S and S * may be formed according to the level of the external signal. If the package has unused terminals, they can be used.

In the above description, the case where the invention made by the present inventor is mainly applied to a static RAM as a memory LSI which is a field of application which is the background of the invention has been described, but the present invention is not limited thereto. The present invention can be widely applied to on-chip static RAMs such as microcomputers and semiconductor memory devices of other memory formats. The present invention can be applied at least to a semiconductor memory device under the condition that there is a relation between the power consumption and the operating speed.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by changing the instruction from the instruction means, a specific internal circuit such as an address buffer is activated even in the non-selected state of the operation by the first control signal, or the selected state of the operation by the first control signal. It becomes possible to activate only when, and to change the characteristics such as power consumption and operating speed in the semiconductor memory device,
The effect is that it can be performed relatively easily without changing the mask pattern at the time of manufacturing.

By adopting the fuse program circuit as the instructing means, semiconductor memory devices having apparently different characteristics can be easily obtained.

Reducing the operating voltage of an internal circuit such as an address buffer which is expected to consume a relatively large amount of power contributes to low power consumption, and further, the first power consumption is relatively small. The two-step configuration in which the step-down circuit and the second step-down circuit having relatively large power consumption are adopted to control activation of the second step-down circuit can further promote the reduction of power consumption in the standby state. At this time, in the constant activation control of the specific internal circuit instructed by the instruction means, the second step-down voltage circuit and the address buffer are synchronously controlled so that the current supply required for the operation of the address buffer, that is, the high-speed access is performed. It can be guaranteed.

[Brief description of drawings]

FIG. 1 is a static R according to an embodiment of the present invention.
It is a block diagram of AM.

FIG. 2 is a circuit diagram of an example of a fuse program circuit, a controller, and an address buffer.

FIG. 3 is a circuit diagram of an example of a step-down circuit.

[Explanation of symbols]

MCA memory cell array MC memory cell ABUF address buffer CS * Chip select signal (first control signal) TCONT controller TG1 CMOS transfer gate Qn3 MOSFET φ1 control signal (first activation control signal) FPGM fuse program circuit S, S * control signal (instruction signal) FUSE fuse GDV1 first step-down circuit GDV2 second step-down circuit Vdd power supply voltage Vgd Step-down voltage GDVC control circuit φ2 control signal (second activation control signal)

Claims (5)

[Claims] 1. A memory cell that responds to an address signal is controlled by activating or deactivating an internal circuit by an activation control signal based on a first control signal supplied for selecting an operation of a semiconductor memory device. In a semiconductor memory device that selects data from a cell array and amplifies and outputs data of a selected memory cell, an activation control signal to be supplied to a specific internal circuit is forced to an activation level regardless of the first control signal. A semiconductor memory device, comprising: a level forcing circuit for performing the above operation; and an instruction means for instructing whether or not the level forcing operation is possible for the level forcing circuit. 2. The semiconductor memory device according to claim 1, wherein the specific internal circuit is an address buffer which is activated and controlled by receiving a first activation control signal as the activation control signal. 3. The specific internal circuit is a circuit that forms a voltage obtained by reducing a power supply voltage as an operating voltage of the address buffer, and is always activated to reduce the power supply voltage and has relatively low power consumption. 3. A first step-down circuit, and a second step-down circuit which receives a second activation control signal as the activation control signal to step down a power supply voltage and consumes a relatively large amount of power. The semiconductor memory device described. 4. The fuse program circuit according to claim 1, wherein the instruction means is a fuse program circuit whose output state is changed depending on whether a fuse is blown or not, and which gives an instruction according to the change.
The semiconductor memory device according to the item. 5. The semiconductor memory device according to claim 1, wherein a static RAM that employs a static memory cell as the memory cell is configured.