JPH052883A - Circuit for generating substrate bias - Google Patents

Abstract

PURPOSE:To freely set an optimum substrate bias at the time of a characteristic test by providing plural oscillating circuits with a different frequency, a switching circuit for changing-over them and a judging circuit judging an operation mode so as to output a switch changing-over signal. CONSTITUTION:An output phi is adopted as an H level and switch elements S and S are respectively turned on and off so that the oscillating circuit 2 is selected and a pulse is supplied to a node (A) in a reading and writing cycle under detecting and testing the test mode of a semiconductor storing device in an operation mode judging equipment 3. Therefore, the potential of the substrate bias VS is set by the frequency of the circuit 2. The lower the potential of the bias VS is, the lower the threshold of a memory element is set and the judgement of normal/defective in the memory element comes to be easy. When the frequency of the circuit 2 is set lower than that of the oscillating circuit 1 here, the bias VS in the test mode is set smaller than that of normal time and the threshold voltage of the memory element becomes low so as to make high efficiency test possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate bias generating circuit, and more particularly to a substrate bias generating circuit incorporated in a semiconductor memory device.

[0002]

2. Description of the Related Art A substrate bias generation circuit is a circuit for applying a potential lower than a reference potential G, which is a ground potential, as a substrate bias VS when a constituent element of a semiconductor memory device is an N channel MOS transistor.

A conventional substrate bias generating circuit of this type is
As shown in FIG. 3, an oscillator circuit 1 which is a high frequency (pulse) source for generating a substrate bias, a charge pump capacitor C1 for coupling the output of the oscillator circuit 1, and a cascade-connected N-channel MOS transistor. And the transistors N1 and N2. The source of the transistor N1 is connected to the reference potential G, the gate and drain in are commonly connected, and further connected to the sources of the capacitor C1 and the transistor N2 to form a node A. The gate and drain-in of the transistor N2 are commonly connected and connected to the substrate bias output terminal TVS.

Next, the operation of the conventional substrate bias generating circuit will be described.

The high frequency power generated in the oscillator circuit 1, that is, the pulse is transmitted to the node A through the capacitor C1 and raises the potential of the node A. The potential at node A is the reference potential G
If it is higher than this, current flows until the transistor N1 becomes conductive and reaches the reference potential G, and the potential of the node A becomes the reference potential G. On the contrary, when the potential of the node A is lower than the reference potential G, the transistor N1 is turned off and the potential of the node A is held.

Next, when the potential of the substrate bias VS, which is the output of the substrate bias output terminal TVS, is higher than the node A, the transistor N2 becomes conductive and current flows until the potential of the node A is reached. The potential is set to the potential of the node A. On the contrary, when the potential of the substrate bias VS is lower than the node A, the transistor N2 is turned off and the potential of the substrate bias VS is held as it is. By the above operation, the potential of the substrate bias VS is held at a negative potential with respect to the ground potential G which is the reference potential, and the potential of the substrate bias VS is set by the oscillation frequency.

[0007]

Since only one semiconductor memory device is provided with the above-described conventional substrate bias generating circuit and the oscillation frequency is fixed,
Since only a constant substrate bias potential is applied, there is a problem in that it is not possible to set the optimum substrate bias potential for a highly efficient characteristic test corresponding to high integration of semiconductor memory devices.

[0008]

A substrate bias generating circuit of the present invention comprises a first oscillating circuit which is a high frequency source of a first frequency, and a second oscillating circuit which is a high frequency source of a second frequency. A switch circuit that switches between the outputs of the first and second oscillator circuits and an operation mode determination circuit that determines an operation mode by a signal of a predetermined format and outputs a switching signal of the switch circuit are configured. .

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the substrate bias generating circuit of the present invention.

The substrate bias generating circuit of this embodiment is shown in FIG.
2, the oscillation circuits 1 and 2 which are high frequency (pulse) sources having different frequencies, the operation mode determination circuit 3 for determining the operation mode of the semiconductor memory device, and the operation mode determination circuit 3
Switch elements S1 and S2 that are connected to each other by the output φ, charge pump capacitors C1 and C2 that couple the respective outputs of the oscillation circuits 1 and 2, an inverter I1, and the same cascade connection as in the conventional example. It is configured to include transistors N1 and N2 which are channel MOS transistors.

Of the above, the parts other than the oscillation circuit 2, the operation mode determination circuit 3, the capacitor C2, the inverter I1, and the switch elements S1 and S2 are the same as those shown in the above-mentioned prior art example. For the sake of simplicity, the description is omitted except for those that are directly connected to the present invention so that the description will not be repeated.

The operation mode determination circuit 3 includes RAS (row address strobe), CAS (column address strobe), WE which are clocks for operating the semiconductor memory device.
, The address Ai is applied.

The switch elements S1 and S2 are on when the output φ of the operation mode determination circuit 3 is at the "L" level, and off when the output φ is at the "H" level.

Next, the operation of this embodiment will be described.

FIG. 2 is a time chart showing an example of the operation of this embodiment.

In the normal state, as shown in FIG. 2A, the output φ of the operation mode determination circuit 3 is set to "L" level to turn on the switch element S1 and the inverter I1 inverts φ to "H". By setting to "" level, the switch element S2 is turned off to select the oscillation circuit 1 and supply the pulse to the node A. Therefore, the same operation as in the above-described conventional example is performed, and the potential of the substrate bias VS is also the same as in the conventional example.

Next, at the time of the test, as shown in FIG.
In addition to the write CBR, which is a write mode in which the CAS of the clock is earlier than the RAS, the semiconductor memory device is in the test mode by applying the super voltage S superimposed on the address Ai and designating the test mode. The operation mode determination circuit 3 detects this and sets the output φ to the "H" level in the read / write cycle under test. As a result,
Contrary to the normal state, the switching element S1 is turned off and the switching element S2 is turned on to select the oscillation circuit 2 to supply a pulse to the node A. Therefore, the potential of the substrate bias VS is set by the frequency of the oscillator circuit 2.

In the test of the semiconductor memory device, a test signal according to a test pattern for judging the quality of the memory element is applied. At this time, the lower the potential of the substrate bias VS, the lower the threshold voltage of the memory element can be set, which facilitates the determination of pass / fail.

Here, the frequency of the oscillation circuit 2 is set to the oscillation circuit 1
If the frequency is set lower than the frequency of, the substrate bias VS in the test mode will be set shallower than in the normal state, and the threshold voltage of the memory element can be lowered to enable a highly efficient test.

[0021]

As described above, in the substrate bias generating circuit of the present invention, a plurality of oscillating circuits having different frequencies, a switch circuit for switching the oscillating circuits and an operation mode determining circuit for determining the operation mode and outputting a switching signal of the switch circuit are determined. By including the circuit, the optimum substrate bias can be freely set at the time of the characteristic test of the semiconductor memory device, so that the test can be performed with high efficiency.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a substrate bias generation circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the substrate bias generation circuit of the present embodiment.

FIG. 3 is a circuit diagram showing an example of a conventional substrate bias generation circuit.

[Explanation of symbols]

1, 2 oscillator circuit 3 Operation mode determination circuit C1, C2 capacitors I1 inverter S1, S2 switch element

Claims (3)

[Claims] 1. A first oscillating circuit which is a high frequency source of a first frequency, a second oscillating circuit which is a high frequency source of a second frequency, and outputs of the first and second oscillating circuits. A substrate bias generation circuit comprising: a switch circuit; and an operation mode determination circuit that determines an operation mode based on a signal of a predetermined format and outputs a switching signal of the switch circuit. 2. The operation mode determination circuit inputs an address, a row address strobe and a column address strobe which are operation clocks of a semiconductor memory device, and superimposes a test mode signal of a predetermined format on the address input. The substrate bias generating circuit according to claim 1, wherein the switching signal is output. 3. The first and second switch elements, each of which is connected to an output of the first and second oscillator circuits and is in contact with by a low level switching signal and is disconnected by a high level switching signal, The substrate bias generating circuit according to claim 1, further comprising an inverter circuit that inverts a switching signal of the first switch element to generate a switching signal of the second switch element.