JPH05283721A - Semiconductor light-receiving device - Google Patents
Semiconductor light-receiving deviceInfo
- Publication number
- JPH05283721A JPH05283721A JP4112220A JP11222092A JPH05283721A JP H05283721 A JPH05283721 A JP H05283721A JP 4112220 A JP4112220 A JP 4112220A JP 11222092 A JP11222092 A JP 11222092A JP H05283721 A JPH05283721 A JP H05283721A
- Authority
- JP
- Japan
- Prior art keywords
- light receiving
- receiving element
- receiving device
- ground pattern
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Light Receiving Elements (AREA)
- Selective Calling Equipment (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ノイズ等の侵入を防止
するシールド用の接地パターンが設けられた半導体受光
装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving device provided with a shield ground pattern for preventing intrusion of noise and the like.
【０００２】[0002]
【従来の技術】家電製品等に幅広く使用されているリモ
ートコントローラ（以下、リモコンとする）は、赤外線
等を用いた送信機と、ｐｉｎフォトダイオード等を用い
た半導体受光装置とから構成されている。このリモコン
用の半導体受光装置を図に基づいて説明する。図４は従
来の半導体受光装置を説明する断面図、図５はこの半導
体受光装置を用いた信号処理回路を説明するブロック図
である。すなわち、この半導体受光装置１は、おもに、
所定の配線パターン１２が形成された基板１１と、この
基板１１表面で配線パターン１２上に搭載され、かつボ
ンディングワイヤー１２ａにて電気的に接続された受光
素子１３、および信号処理用の集積回路２１と、基板１
１裏面で、受光素子１３の搭載位置に対応して形成され
た接地パターン１５とから構成されている。2. Description of the Related Art A remote controller (hereinafter, referred to as a remote controller) widely used for home electric appliances and the like is composed of a transmitter using infrared rays and the like and a semiconductor light receiving device using a pin photodiode and the like. .. This semiconductor light receiving device for remote control will be described with reference to the drawings. FIG. 4 is a sectional view for explaining a conventional semiconductor light receiving device, and FIG. 5 is a block diagram for explaining a signal processing circuit using this semiconductor light receiving device. That is, the semiconductor light receiving device 1 is mainly
A substrate 11 on which a predetermined wiring pattern 12 is formed, a light receiving element 13 mounted on the wiring pattern 12 on the surface of the substrate 11 and electrically connected by a bonding wire 12a, and an integrated circuit 21 for signal processing. And board 1
On the back surface 1, the ground pattern 15 is formed corresponding to the mounting position of the light receiving element 13.
【０００３】また、基板１１の裏面に形成された配線パ
ターン１２には抵抗器やコンデンサ等から成るチップ部
品２２が接続されている。さらに、基板１１の表面に搭
載された、ベアチップ状態である受光素子１３と集積回
路２１、および配線用のボンディングワイヤー１２ａは
保護のための樹脂３０にて封止されている。Further, a chip component 22 composed of a resistor, a capacitor and the like is connected to the wiring pattern 12 formed on the back surface of the substrate 11. Further, the light receiving element 13 in a bare chip state, the integrated circuit 21, and the bonding wire 12a for wiring mounted on the surface of the substrate 11 are sealed with a resin 30 for protection.
【０００４】このようなリモコン用の半導体受光装置１
に用いられている集積回路２１は、図５に示すような信
号処理回路から構成されている。すなわち、この集積回
路２１は、受光素子１３の出力側に接続されたヘッドア
ンプ２１ａと、ヘッドアンプ２１ａに接続されたリミッ
ターアンプ２１ｂと、バンドパスフィルター２１ｃを介
してリミッターアンプ２１ｂと接続された検波器２１ｄ
と、この検波器２１ｄに接続された積分回路２１ｅおよ
びシュミット回路２１ｆとから構成されている。また、
ヘッドアンプ２１ａの入力側には、オートバイアスレベ
ルコントロール（ＡＢＬＣ）が設けられている。A semiconductor light receiving device 1 for such a remote controller
The integrated circuit 21 used in FIG. 1 is composed of a signal processing circuit as shown in FIG. That is, the integrated circuit 21 includes a head amplifier 21a connected to the output side of the light receiving element 13, a limiter amplifier 21b connected to the head amplifier 21a, and a detection amplifier connected to the limiter amplifier 21b via a bandpass filter 21c. 21d
And a Schmitt circuit 21f and an integrating circuit 21e connected to the detector 21d. Also,
An automatic bias level control (ABLC) is provided on the input side of the head amplifier 21a.
【０００５】送信機（図示せず）に設けられた所定の命
令ボタンを押すと、その命令の基づいた赤外線信号が送
信される。そして、受光素子１３にてこの赤外線信号を
受光して、赤外線信号が電気信号に変換される。そし
て、受光素子１３から出力された電気信号は、上述の信
号処理回路にて、各機構および装置を制御する制御信号
に変換される。When a predetermined command button provided on a transmitter (not shown) is pressed, an infrared signal based on the command is transmitted. Then, the light receiving element 13 receives the infrared signal, and the infrared signal is converted into an electric signal. Then, the electric signal output from the light receiving element 13 is converted into a control signal for controlling each mechanism and device by the above-mentioned signal processing circuit.
【０００６】この受光素子１３の出力から集積回路２１
の入力までの間の線路はインピーダンスが高いため、ノ
イズによる発振が発生しやすい。これを防止するため、
受光素子１３と集積回路２１との間にシールド用の接地
パターン１５が設けられている。From the output of the light receiving element 13, the integrated circuit 21
Since the line up to the input of has high impedance, oscillation due to noise is likely to occur. To prevent this,
A ground pattern 15 for shielding is provided between the light receiving element 13 and the integrated circuit 21.
【０００７】このような半導体受光装置１に用いられる
配線パターン１２のレイアウトを、図６に示す。図６
（ａ）は表面側、（ｂ）は裏面側である。すなわち、図
６（ａ）に示すように、基板１１の表面側に所定の配線
パターン１２がそれぞれ形成されている。これらの配線
パターン１２のうち、図中斜線領域Ｓは受光素子１３を
搭載するためのダイパッド兼用の配線パターン１２であ
る。また、図６（ｂ）に示すように、基板１１の裏面側
にも所定の配線パターン１２が形成されており、さら
に、図６（ａ）の領域Ｓに対応する位置、すなわち図６
（ｂ）の図中斜線領域Ｄに接地パターン１５が形成され
ている。この接地パターン１５により、ノイズ等の侵入
を防止している。The layout of the wiring pattern 12 used in such a semiconductor light receiving device 1 is shown in FIG. Figure 6
(A) is the front side and (b) is the back side. That is, as shown in FIG. 6A, predetermined wiring patterns 12 are formed on the front surface side of the substrate 11. Of these wiring patterns 12, the hatched area S in the drawing is the wiring pattern 12 that also serves as a die pad for mounting the light receiving element 13. Further, as shown in FIG. 6B, a predetermined wiring pattern 12 is also formed on the back surface side of the substrate 11, and further, a position corresponding to the area S of FIG. 6A, that is, FIG.
The ground pattern 15 is formed in the hatched area D in FIG. The ground pattern 15 prevents noise and the like from entering.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、このよ
うな半導体受光装置には次のような問題がある。すなわ
ち、受光素子の裏面側はカソードとなっており、集積回
路と接続するためのカソード電極が設けられている。こ
のため、基板に形成された配線パターン上にこの受光素
子を搭載することで、電気的な接続を得る必要がある。
したがって、シールド用の接地パターンは、基板の裏面
側で、受光素子の搭載位置と対応した場所に設けなけれ
ばならない。このため、受光素子のカソードと接地パタ
ーンとの間に基板を挟むことになり、この間で構成され
た容量結合により、シールド効果の低下を招く。However, such a semiconductor light receiving device has the following problems. That is, the back surface side of the light receiving element serves as a cathode, and a cathode electrode for connecting to the integrated circuit is provided. Therefore, it is necessary to mount the light receiving element on the wiring pattern formed on the substrate to obtain electrical connection.
Therefore, the ground pattern for shielding must be provided on the back surface side of the substrate at a position corresponding to the mounting position of the light receiving element. Therefore, the substrate is sandwiched between the cathode of the light receiving element and the ground pattern, and the capacitive coupling formed between them causes a reduction in the shield effect.
【０００９】また、基板の裏面側に接地パターンが形成
されているため、この部分に配線パターンを形成した
り、チップ部品を接続することができない。したがっ
て、部品の実装密度の低下や、配線パターンのレイアウ
トの制約を受けることになる。よって、本発明はシール
ド効果を向上させ、かつ設計自由度が高い半導体受光装
置を提供することを目的とする。Further, since the ground pattern is formed on the back side of the substrate, it is not possible to form a wiring pattern or connect a chip component to this portion. Therefore, the mounting density of components is reduced and the layout of the wiring pattern is restricted. Therefore, it is an object of the present invention to provide a semiconductor light receiving device that improves the shield effect and has a high degree of freedom in design.
【００１０】[0010]
【課題を解決するための手段】本発明は、以上の課題を
解決するためになされた半導体受光装置である。すなわ
ち、この半導体受光装置は、基板上に配線パターンと接
地パターンとを形成し、この接地パターン上に絶縁層を
介して受光素子を搭載したもので、さらに、受光素子を
配線パターンと接地パターンとの両方にそれぞれボンデ
ィングワイヤーを介して電気的に接続したものである。SUMMARY OF THE INVENTION The present invention is a semiconductor light receiving device made to solve the above problems. That is, this semiconductor light receiving device is one in which a wiring pattern and a ground pattern are formed on a substrate, and a light receiving element is mounted on this ground pattern via an insulating layer. Furthermore, the light receiving element is provided with a wiring pattern and a ground pattern. Both of them are electrically connected to each other via bonding wires.
【００１１】[0011]
【作用】基板の表面に接地パターンが形成され、その上
の絶縁層を介して受光素子が接続されているので、受光
素子と接地パターンとの間隔は絶縁層の厚さだけとな
る。このように、受光素子裏面のカソード側の近傍に接
地パターンが設けられているため容量結合が小さく、シ
ールド効果が向上する。また、接地パターンが基板の裏
面に形成されていないため、この部分に配線パターンを
形成したり、チップ部品を接続することができる。Since the ground pattern is formed on the surface of the substrate and the light receiving element is connected through the insulating layer thereon, the distance between the light receiving element and the ground pattern is only the thickness of the insulating layer. As described above, since the ground pattern is provided near the cathode side on the back surface of the light receiving element, capacitive coupling is small and the shield effect is improved. Further, since the ground pattern is not formed on the back surface of the substrate, it is possible to form a wiring pattern on this portion or connect a chip component.
【００１２】[0012]
【実施例】以下に、本発明の半導体受光装置の実施例を
図に基づいて説明する。図１は本発明の半導体受光装置
を説明する断面図、図２は受光素子の構造を説明する断
面図である。すなわち、図１に示すような半導体受光装
置１は、おもに、セラミックス等から成る基板１１と、
基板１１に搭載された受光素子１３、および信号処理用
の集積回路２１とから構成されている。Embodiments of the semiconductor light receiving device of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view for explaining a semiconductor light receiving device of the present invention, and FIG. 2 is a sectional view for explaining a structure of a light receiving element. That is, the semiconductor light receiving device 1 as shown in FIG. 1 mainly includes a substrate 11 made of ceramics or the like,
It is composed of a light receiving element 13 mounted on the substrate 11 and an integrated circuit 21 for signal processing.
【００１３】基板１１の表面には配線パターン１２と接
地パターン１５とが設けられており、この接地パターン
１５上には絶縁層１４を介して受光素子１３が搭載され
ている。また、受光素子１３はボンディングワイヤー１
２ａを用いて、接地パターン１５および配線パターン１
２とそれぞれ電気的に接続されている。集積回路２１も
ボンディングワイヤー１２ａを用いて配線パターン１２
と電気的に接続されている。さらに、基板１１の裏面に
も配線パターン１２が形成されており、抵抗器やコンデ
ンサ等から成るチップ部品２２が接続されている。ま
た、基板１１上に搭載された受光素子１３や集積回路２
１はベアチップ状態であるため、保護用の樹脂３０にて
封止されている。A wiring pattern 12 and a ground pattern 15 are provided on the surface of the substrate 11, and a light receiving element 13 is mounted on the ground pattern 15 via an insulating layer 14. Further, the light receiving element 13 is the bonding wire 1
2a, ground pattern 15 and wiring pattern 1
2 are electrically connected to each other. The integrated circuit 21 also uses the bonding wire 12a to form the wiring pattern 12
Is electrically connected to. Further, the wiring pattern 12 is also formed on the back surface of the substrate 11, and chip components 22 such as resistors and capacitors are connected to the wiring pattern 12. In addition, the light receiving element 13 and the integrated circuit 2 mounted on the substrate 11
Since 1 is in a bare chip state, it is sealed with a protective resin 30.
【００１４】次に、本発明の半導体受光装置１に用いる
受光素子１３を図２に基づいて説明する。すなわち、こ
の受光素子１３は、シリコン等の半導体材料から成るｐ
ｉｎフォトダイオードで、上部に設けられたｐ＋から成
るｐ層１６（アノード）と、下部に設けられたｎ＋から
成るｎ層１８（カソード）と、これらの間に設けられた
真性半導体ｎ−から成るｉ層１７とから構成されてい
る。ｐ層１６にはアルミニウム等から成るアノード電極
１３ａが設けられており、カソード電極１３ｂがｉ層１
７の上部に設けられたｎ＋層と導通状態で設けられてい
る。Next, the light receiving element 13 used in the semiconductor light receiving device 1 of the present invention will be described with reference to FIG. That is, the light receiving element 13 is made of a semiconductor material such as silicon.
The in-photodiode is composed of ap layer 16 (anode) made of p + provided in the upper portion, an n layer 18 made of n + provided in the lower portion (cathode), and an intrinsic semiconductor n− provided between them. and i layer 17. An anode electrode 13a made of aluminum or the like is provided on the p-layer 16 and a cathode electrode 13b is formed on the i-layer 1
It is provided in a conductive state with the n + layer provided on the upper part of 7.
【００１５】また、受光素子１３の裏面には、例えば酸
化シリコン（ＳｉＯ2 ）から成る絶縁層１４が形成され
ており、この絶縁層１４により、受光素子１３の裏面と
接地パターン１５との絶縁を得ている。このため、配線
パターン１２および接地パターン１５との電気的な接続
は、受光素子１３の上部に設けられたアノード電極１３
ａおよびカソード電極１３ｂからボンディングワイヤー
１２ａを用いて行われる。An insulating layer 14 made of, for example, silicon oxide (SiO 2 ) is formed on the back surface of the light receiving element 13, and the insulating layer 14 insulates the back surface of the light receiving element 13 from the ground pattern 15. It has gained. Therefore, the electrical connection between the wiring pattern 12 and the ground pattern 15 is performed by the anode electrode 13 provided on the light receiving element 13.
a and the cathode electrode 13b to the bonding wire 12a.
【００１６】このように、接地パターン１５を基板１１
の表面に形成し、この接地パターン１５上に絶縁層１４
を介して受光素子１３を接続することにより、接地パタ
ーン１５と受光素子１３の裏面との間隔を絶縁層１４の
厚さだけにすることができる。これにより、受光素子１
３の裏面と絶縁層１４との間に構成される容量結合は極
微小となる。In this way, the ground pattern 15 is connected to the substrate 11
Formed on the surface of the insulating layer 14 on the ground pattern 15
By connecting the light receiving element 13 via the light receiving element 13, the distance between the ground pattern 15 and the back surface of the light receiving element 13 can be set only to the thickness of the insulating layer 14. Thereby, the light receiving element 1
The capacitive coupling formed between the back surface of 3 and the insulating layer 14 is extremely small.
【００１７】次に、本発明の半導体受光装置１による配
線パターン１２のレイアウトを図に基づいて説明する。
図３は本発明の半導体受光装置１の配線パターン１２の
レイアウト図で、（ａ）は表面側、（ｂ）は裏面側であ
る。すなわち、図３（ａ）に示すように、基板１１の表
面側には所定形状の配線パターン１２が設けられている
とともに、受光素子１３を搭載する位置に接地パターン
１５（図中斜線領域ｄ）が設けられている。また、基板
１１の裏面側にはチップ部品２２を接続するための配線
パターン１２が設けられている。Next, the layout of the wiring pattern 12 by the semiconductor light receiving device 1 of the present invention will be described with reference to the drawings.
3A and 3B are layout diagrams of the wiring pattern 12 of the semiconductor light receiving device 1 of the present invention, where FIG. 3A is the front side and FIG. 3B is the back side. That is, as shown in FIG. 3A, the wiring pattern 12 having a predetermined shape is provided on the front surface side of the substrate 11, and the ground pattern 15 (hatched area d in the figure) is provided at a position where the light receiving element 13 is mounted. Is provided. Further, a wiring pattern 12 for connecting the chip component 22 is provided on the back surface side of the substrate 11.
【００１８】このように、従来、基板１１の裏面側に設
けられていた接地パターン１５（図６（ｂ）の領域Ｄ）
が、基板１１の表面側に設けられており、しかも、この
接地パターン１５上に受光素子１３が搭載されるため、
基板の面積を縮小することができる。しかも、基板１１
の裏面側には配線パターン１２しか設けられていないた
め、配線パターン１２のレイアウト設計を自由に行うこ
とができる。As described above, the ground pattern 15 (region D in FIG. 6B) conventionally provided on the back surface side of the substrate 11 is used.
Is provided on the front surface side of the substrate 11, and since the light receiving element 13 is mounted on the ground pattern 15,
The area of the substrate can be reduced. Moreover, the substrate 11
Since only the wiring pattern 12 is provided on the back side of the wiring pattern 12, the layout design of the wiring pattern 12 can be freely performed.
【００１９】なお、本発明の半導体受光装置１で用いた
受光素子１３の構造として、受光素子１３の裏面に絶縁
層１４が設けられたものを用いて説明したが、本発明は
これに限定されず、受光素子１３と接地パターン１５と
の間に絶縁層１４が設けられている構造であればよい。
すなわち、接地パターン１５の上面にＳｉＯ2 等の絶縁
層１４を形成し、この絶縁層１４上に受光素子１３を搭
載したものでもよい。The structure of the light receiving element 13 used in the semiconductor light receiving device 1 of the present invention has been described by using the light receiving element 13 provided with the insulating layer 14 on the back surface thereof, but the present invention is not limited to this. Instead, the insulating layer 14 may be provided between the light receiving element 13 and the ground pattern 15.
That is, the insulating layer 14 made of SiO 2 or the like may be formed on the upper surface of the ground pattern 15, and the light receiving element 13 may be mounted on the insulating layer 14.
【００２０】[0020]
【発明の効果】以上説明したように、本発明の半導体受
光装置によれば次のような効果がある。すなわち、受光
素子の裏面のカソードとシールド用の接地パターンとの
間隔は、絶縁層の厚さだけとなるため、この間で容量結
合がほとんど構成されない。したがって、シールド効果
の向上を図ることができる。また、基板の表面側に接地
パターンが設けられ、この接地パターン上に絶縁層を介
して受光素子を搭載しているため、部品の実装密度を向
上することができる。また、基板の面積を縮小できるの
で、半導体受光装置全体の大きさを小型化することが可
能となる。さらに、基板の裏面側に接地パターンを設け
る必要がないため、配線パターンのレイアウト設計にお
いて、制約を受けることがなく、設計自由度を増加させ
ることが可能となる。As described above, the semiconductor light receiving device of the present invention has the following effects. That is, since the distance between the cathode on the back surface of the light receiving element and the ground pattern for shielding is only the thickness of the insulating layer, capacitive coupling is hardly formed between them. Therefore, the shield effect can be improved. Further, since the ground pattern is provided on the front surface side of the substrate and the light receiving element is mounted on the ground pattern via the insulating layer, the mounting density of components can be improved. Further, since the area of the substrate can be reduced, the size of the entire semiconductor light receiving device can be reduced. Furthermore, since it is not necessary to provide a ground pattern on the back surface side of the substrate, there is no restriction in the layout design of the wiring pattern, and it is possible to increase the degree of freedom in design.
【図１】本発明の半導体受光装置を説明する断面図であ
る。FIG. 1 is a sectional view illustrating a semiconductor light receiving device of the present invention.
【図２】本発明の半導体受光装置で使用する受光素子を
説明する断面図である。FIG. 2 is a sectional view illustrating a light receiving element used in the semiconductor light receiving device of the present invention.
【図３】本発明の配線パターンのレイアウト図で、
（ａ）は表面側、（ｂ）は裏面側である。FIG. 3 is a layout diagram of a wiring pattern of the present invention,
(A) is the front side and (b) is the back side.
【図４】従来の半導体受光装置を説明する断面図であ
る。FIG. 4 is a cross-sectional view illustrating a conventional semiconductor light receiving device.
【図５】信号処理回路を説明するブロック図である。FIG. 5 is a block diagram illustrating a signal processing circuit.
【図６】従来の配線パターンのレイアウト図で、（ａ）
は表面側、（ｂ）は裏面側である。FIG. 6 is a layout diagram of a conventional wiring pattern, (a)
Is the front surface side, and (b) is the back surface side.
１ 半導体受光装置 １１ 基板 １２ 配線パターン １２ａ ボンデ
ィングワイヤー １３ 受光素子 １４ 絶縁層 １５ 接地パターン ２１ 集積回路 ２２ チップ部品 ３０ 樹脂DESCRIPTION OF SYMBOLS 1 Semiconductor light receiving device 11 Substrate 12 Wiring pattern 12a Bonding wire 13 Light receiving element 14 Insulating layer 15 Ground pattern 21 Integrated circuit 22 Chip component 30 Resin
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 8422−4Ｍ Ｈ０１Ｌ 31/10 Ａ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location 8422-4M H01L 31/10 A
Claims (2)
と、 前記基板上に設けられた接地パターンと、 前記接地パターン上に絶縁層を介して搭載された受光素
子とから成ることを特徴とする半導体受光装置。1. A substrate comprising a predetermined wiring pattern, a ground pattern provided on the substrate, and a light-receiving element mounted on the ground pattern via an insulating layer. Semiconductor light receiving device.
記接地パターンとの両方にそれぞれボンディングワイヤ
ーを介して電気的に接続されていることを特徴とする請
求項１記載の半導体受光装置。2. The semiconductor light receiving device according to claim 1, wherein the light receiving element is electrically connected to both the wiring pattern and the ground pattern through bonding wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4112220A JPH05283721A (en) | 1992-04-03 | 1992-04-03 | Semiconductor light-receiving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4112220A JPH05283721A (en) | 1992-04-03 | 1992-04-03 | Semiconductor light-receiving device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05283721A true JPH05283721A (en) | 1993-10-29 |
Family
ID=14581264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4112220A Pending JPH05283721A (en) | 1992-04-03 | 1992-04-03 | Semiconductor light-receiving device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05283721A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008147383A (en) * | 2006-12-08 | 2008-06-26 | Matsushita Electric Works Ltd | Photoelectric conversion module |
-
1992
- 1992-04-03 JP JP4112220A patent/JPH05283721A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008147383A (en) * | 2006-12-08 | 2008-06-26 | Matsushita Electric Works Ltd | Photoelectric conversion module |
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