JPH05282471A - Microcomputer and emulator - Google Patents

Abstract

PURPOSE:To utilize plural external memories having addresses which are mutually duplicate with addresses of an internal memory by changing access conditions. CONSTITUTION:An emulation memory 331 substitutes for the internal ROM of a processor 1 for emulation and holds a user program. An emulation memory 332 holds an emulation program. An emulation control circuit 40 performs chip selection control over the memories 331 and 332 according to a processor 1 executes the user program or emulation program. The bus control circuit in the processor 1 employs two 16-bit data bus states as the access conditions of the memory 331 corresponding to the execution of the user program by the processor 1 or three 8-bit data bus states as the access conditions of the memory 332 corresponding to the execution of the emulation program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation processor for a microcomputer, for example, a single-chip microcomputer, and an emulator using the emulation processor.

[0002]

2. Description of the Related Art In order to develop a system using a single-chip microcomputer, a microcomputer developing device called a so-called emulator or in-circuit emulator is used. The microcomputer development device is a single-chip microcomputer (target microcomputer) which is connected between a system development device such as a so-called personal computer for software development and an application system under development and which is to be installed in the application system. While substituting for functions, it has the function of a debugger and supports the development of software (or programs) or application systems. An emulation processor for evaluation called an evaluation chip, which corresponds to the above single-chip microcomputer, is used for this microcomputer development device. Such an emulation processor has a function of including a single-chip microcomputer as a corresponding target microcomputer, and also has a dedicated function of outputting the internal state of the microcomputer and controlling the operation of the microcomputer. The development of the microcomputer development device is facilitated. Regarding the in-circuit emulator, for example, "H8 / 3" issued by Hitachi, Ltd. in November 1989
30 ASE model I ”and the like, and the single chip microcomputer is described in“ H8 / 330 HD647 ”issued by Hitachi, Ltd. in August 1989.
3308 HD64333308 Hardware Manual ”, and the emulation processor is known in Japanese Patent Laid-Open No. 63-106840.

Although not particularly limited, the single-chip microcomputer is for improving the processing speed and facilitating the interface with the external memory.
External memory uses 8-bit data bus to read / write in 3 states, and internal memory such as internal ROM is 1
It can be read in two states using a 6-bit data bus. The state is a basic operation cycle of the single-chip microcomputer or the emulation processor, and one state is a time of about 100 nanoseconds. At this time, a wait can be requested at the time of 3-state read / write, but a wait cannot be requested at the time of 2-state read / write. As a result, the efficiency of instruction reading on the built-in ROM by the CPU is improved, and the processing speed is improved.
Further, any memory can be used by being connected to the outside of the microcomputer regardless of access time.

Such a single-chip microcomputer includes a central processing unit (CPU), a ROM (read only memory) mainly for storing operation programs (user programs), and a RAM (random access) mainly for data storage or a work area of the CPU. Memory) and various peripheral functions. However, as the emulation processor, the program is frequently changed due to its nature of being used for program development.
For this reason, the ROM built in the single-chip microcomputer cannot be used because it cannot be written at any time, and an emulation memory such as a RAM which substitutes for the built-in ROM is provided inside the in-circuit emulator. The first emulation memory is used as an emulation memory that replaces the built-in ROM. First
The emulation memory replaces the built-in ROM,
It must operate with the same functions and specifications as the built-in ROM. That is, the first emulation memory is also 1
6-bit data bus, 2-state read / write must be performed. However, since the emulation memory has a larger output delay time of the address and the read signal output from the emulation processor at the time of reading, or the data delay time of the emulation memory, it is faster than the built-in ROM. Needed. Also, the memory capacity is built-in RO
The same as or more than M is required. Built-in R
The same applies to AM as in the case of the built-in ROM.

On the other hand, the in-circuit emulator is CP
It has a function of operating U to output the internal state of the single-chip microcomputer to the outside of the emulation processor. An emulation program for realizing such a debug support function is stored in the second emulation memory. Such a second
Since the emulation memory does not replace the built-in ROM, high speed memory is not required. It is sufficient to be able to read / write in the same 8-bit data bus and 3 states as the external memory.

[0006]

DISCLOSURE OF THE INVENTION The present inventors have proposed a CPU
Has an address space of 64 kbytes (1 kbyte = 1024 bytes), built-in ROM 60 kbytes, built-in RAM
We examined an emulation processor that replaces a single-chip microcomputer with a large-capacity memory of 2 kbytes. First, in the address space of the CPU, the space excluding the built-in ROM, RAM, and peripheral functions is 2 kbytes. With this 2 kbyte space alone,
It is not enough to store the emulation program. Although this is not a known technique in this respect, a display signal indicating whether the emulation processor is executing the user program or the emulation program is provided, and the first emulation memory is used or the second emulation memory is used. You can choose whether to use the emulation memory. As a result, the area for storing the emulation program can be secured up to 60 kbytes. However, in such a case, the second emulation memory, which originally does not need a high-speed memory, must be the same high-speed memory as the first emulation memory unless the access conditions are changed.

In addition, the built-in ROM that has already been developed is 32
Even if there is an in-circuit emulator that is compatible with microcomputers with 1 kbyte of built-in RAM and 1 kbyte of k-byte, if you do not change the emulation memory, you can modify this emulator to create a microcomputer with 60 kbytes of built-in ROM and 2 kbytes of built-in RAM It cannot be used as a computer-compatible emulator. At this time, in order to share the hardware of the emulator that does not depend on the specifications of the single-chip microcomputer other than the first emulation memory with other single-chip microcomputers, even if the built-in ROM has a small capacity, The emulation memory must be fast, which is not economical. That is, if a high-speed access memory is required for the second emulation memory as well as the first emulation memory, the second emulation memory for storing the emulation program must be arranged together with the first emulation memory in the immediate vicinity of the emulation processor. I won't. The emulation processor is mounted on an emulation pod that is extended from the emulator body by a cable and is close to the target system. Therefore, if the microcomputer to be supported by the emulator is changed, the emulation pod including the second emulation memory must be changed or replaced.

An object of the present invention is to provide a microcomputer capable of selectively using a high speed access memory and a low speed access memory in which allocation addresses are partially overlapped, as an external memory replacing the built-in memory. is there. Another object of the present invention is to use a high-speed access emulation memory for storing a user program and a low-speed access for storing an emulation program as an emulation memory that replaces a built-in memory for storing an operation program of a central processing unit. It is an object of the present invention to provide a microcomputer that can use an emulation memory with overlapping allocation addresses. Still another object of the present invention is to provide an emulator capable of facilitating product type expansion or coping with a change in a microcomputer built-in memory such as a ROM.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a one-chip microcomputer including a central processing unit and a memory, access to a predetermined address assigned to the built-in memory is performed.
A bus control means is provided for selectively controlling access to an external memory and changing the access condition by the central processing unit according to the switching.

The bus control means decodes an address signal to generate a selection signal corresponding to a predetermined address assigned to the built-in memory, and a logic of a predetermined acknowledge signal when the selection signal is activated. And a logic circuit for instructing the central processing unit to the predetermined access condition according to the value.

The access condition can be a single condition or a plurality of conditions selected from the number of parallel bits of data when accessing and the access time.

In the emulator in which the microcomputer is mounted as an emulation microcomputer, the emulator is arranged so as to have an address which entirely or partially overlaps with a predetermined address assigned to the built-in memory of the microcomputer. Is a memory for replacing the built-in memory,
And a second emulation memory, which further receives the selection signal generated by the decoder and the acknowledge signal, and outputs the acknowledge signal to the address where the first emulation memory and the second emulation memory overlap each other. Emulation memory control means for activating and controlling a chip select signal for the first emulation memory or the second emulation memory is arranged according to the logical value.

The first emulation memory has a shorter access time than the second emulation memory, the first emulation memory is an object for storing a target program, and the second emulation memory is an emulation program for controlling an emulator. To be stored. At this time, the acknowledge signal is a break acknowledge signal of the microcomputer that responds to the break instruction for the target program execution state.

The hardware that does not depend on the specifications of the microcomputer that the emulator should support,
In order to make it common to various microcomputers relatively easily or efficiently, the first emulation memory is mounted on the same circuit board as the microcomputer for emulation, for example, an emulation pod, and the second emulation memory is It is mounted on another circuit board such as an emulator body, which is connected from the circuit board by a cable.

[0017]

According to the above-mentioned means, the function of switching the external memory access by the bus control means and the access condition change accompanying it is used as a high-speed access memory in which allocation addresses are partially overlapped as an external memory replacing the built-in memory. And slow access memory are selectively made available to the microcomputer. When this microcomputer is an emulation microcomputer,
As an emulation memory that replaces the built-in memory for storing the operation program of the central processing unit, the high-speed access emulation memory for storing the user program and the low-speed access emulation memory for storing the emulation program have overlapping allocation addresses. And make it available to the microcomputer. Applying such an emulation microcomputer to the emulator makes it possible to position an emulation memory with sufficient low-speed access for storing the emulation program as hardware that does not depend on the specifications of the microcomputer that the emulator should support. This realizes easy product development or easy response to changes in the microcomputer built-in memory such as ROM.

[0018]

1 is a block diagram showing an emulation processor which is an embodiment of a microcomputer according to the present invention. The emulation processor 1 of the present embodiment has a single-chip microcomputer portion 10 corresponding to the function of the microcomputer to be supported by the emulation processor 1 and a portion dedicated to the emulation processor which is the other portion, and these are well known. It is formed on one semiconductor substrate such as silicon by a semiconductor integrated circuit manufacturing technique.

The single-chip microcomputer portion 10 is not particularly limited, but the CPU 11, 60k
Byte ROM (Read Only Memory) 12, 2 kbyte RAM (Random Access Memory) 13, Timer 1
4. Serial communication interface (SC
I) 15, an external bus interface 16, an input / output port circuit 17 including nine input / output ports, and a bus control circuit 18. The dedicated portion for the emulation processor has an emulation interface 20 and the like. The circuit blocks include an internal bus 1 including a data bus, an address bus, a control bus, etc.
9 are commonly connected. The emulation interface 20 transmits / receives signals to / from a microcomputer development device such as an emulator. The external bus interface 16 and the input / output port circuit 17 serve as a target system interface that transmits / receives signals to / from an application system (target system) targeted for system debugging or software debugging. This target system interface exchanges, for example, input / output data of ports, input / output signals of timers, and the like with the outside. The emulation interface exchanges, for example, a signal indicating a read operation or a write operation of the CPU 11, a signal indicating an instruction read operation, or a break interrupt signal with the outside. The emulation processor 1 has the same functional blocks as a single-chip microcomputer as a target microcomputer and is not particularly limited, but the operating frequency and the like are also the same. By using the emulation processor 1, it is not necessary to individually configure a logic gate circuit acting on behalf of the operation of the single chip microcomputer by a TTL or the like inside the microcomputer developing device.

FIG. 2 shows a schematic block diagram of an emulator as a microcomputer developing apparatus using the emulation processor 1. In the figure, 4 is a target system as a microcomputer application system, 3 is a microcomputer development device (hereinafter also simply referred to as an emulator), and 5 is a system development device such as a host computer. Reference numeral 40 denotes a target microcomputer mounting area in the target system 4, and the connector section 30 of the emulator 3 is mounted in the target system 4 instead of the target microcomputer. The emulation processor 1 includes the connector section 30 and the interface cable 31.
Via the target system interface 1 via
6 and 17 are used to input and output signals to and from the target system 4. The emulation processor 1 is connected to the emulation bus 32 using the emulation interface 20. Using the emulation bus 32, the emulation processor 1 outputs various signals transmitted / received between the target system 4 and the emulation processor 1 and information according to the internal state of the emulation processor 1, and also for emulation. For processor 1,
Various control signals for emulation are input.

Further, the emulation bus 32 has a first emulation memory 3 which substitutes for the ROM 12 built in the emulation processor 1.
31, a second emulation memory 332 that stores an emulation program, a break control circuit 34, a real-time trace circuit 35, and the like, which are not particularly limited, are connected. The emulation memory control circuit 40 generates selection signals for the first emulation memory 331 and the second emulation memory 332. The break control circuit 34 monitors the control state of the emulation processor 1 and the state of the emulation bus 32. When the state reaches a preset state, the break control circuit 34 inputs the emulator-dedicated interrupt for emulation. The execution of the user program by the processor 1 is stopped, and the emulation program is executed (break). The real-time trace circuit 35 sequentially stores addresses and data, and further control information given to the emulation bus 32, based on a signal indicating a read operation or a write operation of the CPU 11, a signal indicating an instruction read operation, and the like. The emulation memories 331 and 332, the break control circuit 3
4. The real-time trace circuit 35 is controlled by the control processor 37 via the control bus 36. The control bus 36 is connected to the system development device 5 such as a personal computer through a host interface circuit 39, although not particularly limited thereto.

The first emulation memory 331
Is a memory that can be accessed at high speed at the same or similar speed as the property of substituting the internal memory of the microcomputer. The second emulation memory 332 is not required to have such high speed. still,
In this embodiment, the emulation memory substituting the built-in RAM 13 is not shown, but it can be constituted by a memory having the same access specifications as the first emulation memory 331.

Although the emulator 3 can be constructed on a single circuit board, in the present embodiment, the emulator body 3A and the emulation pod 3B extendedly connected to the emulator body 3A by a cable (not shown) are provided. It is divided into two parts. As shown in FIG. 2, the emulation pod 3B includes the emulation processor 1 and the first emulation memory 331.
In order to minimize the undesired signal delay, the emulation can be performed with high reliability in a state close to the actual operation of the target system 4.

The emulation processor 1 is
Whether a user program (target program to be evaluated or under development) is being executed, or an emulation program (initialization program of emulator or microprocessor for emulation or control program of emulator) is being executed Break acknowledge signal BACK for indicating
Is output. The break acknowledge signal BACK indicates the execution of the emulation program by its 1 level, and indicates the execution of the user program by 0 level. For example, the break acknowledge signal BACK is 1
At the level, the real-time trace circuit 35 does not store the address, data and control information. The first emulation memory 331 is readable / writable when the break acknowledge signal BACK is at 0 level, that is, when the CPU 11 is executing the user program, and the second emulation memory 332 is the break acknowledge signal. When BACK is at 1 level, that is, CPU 11
Can be read / written while the emulation program is running.

FIG. 3 shows an address map of the CPU 11 incorporated in the emulation processor 1. The first emulation memory 331 has a storage capacity of 60 kbytes, and the second emulation memory 332
Has a storage capacity of 16 kbytes. These are CPU1
1 address H'8000 to H'BFFF (H 'is 16
Meaning a radix number). When an address in this range is selected, the emulation memory control circuit 40 determines which of the emulation memories 331 and 332 is selected based on the Breno acknowledge signal BACK. In FIG. 3, the memory access in the address range indicated by the bold arrow has a data bus width (the number of parallel bits of data accessed in one access cycle) of 8 bits and the number of access cycles is 3 states. To be done. In the memory access in the address range indicated by the dashed arrow, the data bus width is 16 bits and the number of access cycles is 2 states. Therefore, the bus width and the number of memory cycle states are controlled to be switched depending on whether the access target is the first emulation memory 331 or the second emulation memory 332 at the addresses H'8000 to H'BFFF. This control is performed by the bus control circuit 18.

The data bus of the emulation bus 32 is 16 bits which is the maximum bus width of the CPU 11,
Although a 16-bit data bus is connected to the first emulation memory 331, the second emulation memory 3
An 8-bit data bus is connected to 32. Although this 8-bit data bus is not particularly limited,
These are the upper 8 bits of the bit data bus.

FIG. 4 shows an example of the bus control circuit 18 of the emulation processor 1. The bus control circuit 18 has a decoder 180 that decodes the address signal output from the CPU 1 and generates a functional block selection signal indicating which functional block is selected. The decoding logic of the decoder 180 is determined according to the memory map described in FIG. The functional block selection signals include I / O selection signal 181, RAM selection signal 182, ROM selection signal 183, and emulator I / O.
O selection signal 184, emulator RAM selection signal 18
5, the emulator ROM selection signal 186. The I / O selection signal 181, the RAM selection signal 182, and the ROM selection signal 183 are stored in the timer 14 as an I / O (input / output circuit) built in the emulation processor 1 and the serial communication interface 15, the RAM 13, and the ROM 12, respectively. It is used as a selection signal, and one level thereof is set as a selection level. I for the emulator
/ O selection signal 184, emulator RAM selection signal 1
85, the emulator ROM selection signal 186 is input to the real-time trace circuit 35, and is also used as a selection signal of a function block on the emulator side that substitutes for the built-in function block of the emulation processor 1, and via the driver DRV, the emulation processor 1 To the outside, and the one level thereof is set as the selection level. The emulator RAM selection signal 185 is the RAM selection signal 18
2 and the emulator ROM selection signal 186 corresponds to the ROM selection signal 183. Although not particularly limited, each of the RAM selection signal 182 and the ROM selection signal 183 is output via a 2-input AND gate AND1 which receives the inverted level of the emulation operation signal 187 at one input. The emulation operation signal 187 is set to 1 level when the emulation processor 1 is mounted on the emulator 3 and performs the emulation operation. Thus, when the emulation operation is performed, the ROM selection signal 183 for the internal ROM 12 and The RAM selection signal 182 for the built-in RAM is fixed at 0 level as the non-selection level, and instead, the ROM selection signal for emulator 186 and RA for emulator are set.
The M selection signal 185 comes to be used.

Whether the functional blocks selected by the various functional block selection signals are connected by an 8-bit data bus or a 16-bit data bus,
Further, a 16-bit bus / 2-state instruction signal 190 and a wait instruction signal 191 are output to instruct the CPU 11 whether to access in two states or in three states. Although not particularly limited, in order to simplify the control logic and reduce the physical scale, the CPU 11 has two types of bus access operations: 16-bit bus / 2 states and 8-bit bus / 3 states. Therefore, when the 16-bit bus / 2-state instruction signal 190 is set to 0 level as the disable level, the CPU 11 performs 8-bit bus / 3-state bus access. According to the circuit of FIG. 4, 16 is output via the OR gate OR1 and the AND gate AND2.
The bit bus / two-state instruction signal 190 responds to the emulator RAM selection signal 185 or the emulator ROM selection signal 186 being set to 1 level when the bus acknowledge signal BACK is at 0 level (during execution of the user program). 16-bit bus
Instructs 2-state bus access. On the other hand, when the bus acknowledge signal BACK is at 1 level (during execution of the emulation program), even if the emulator ROM selection signal 186 is set to 1 level, the 16-bit bus
The 2-state instruction signal 190 maintains 0 level as a disable level, and 16-bit bus / 2-state bus access is not instructed. As for the emulation memory (not shown) which substitutes for the built-in RAM, the emulation memory is
The 6-bit bus / 2-state instruction signal 190 instructs the CPU 11 to access the 16-bit bus / 2-state bus during both the execution of the emulation program and the execution of the user program.

Therefore, during the emulation operation,
When the address assigned to the internal ROM 12 is accessed, the emulator ROM selection signal 18
6 is set to 1 level. At this time, when the break acknowledge signal BACK is at 0 level (during execution of the user program), 16-bit bus / 2-state bus access is instructed to the CPU 11, and the break acknowledge signal is set to 1 level. In the case of (execution of emulation program), 8-bit bus / 3-state bus access is instructed. As a result, the second emulation memory 332, which is made accessible by one level of the break acknowledge signal, can be read / written in three states or in a time of three states or more by the wait instruction signal 191 based on the wait request signal 192.

FIG. 5 shows an example block diagram of the emulation memory control circuit 40. The chip select CS1 of the first emulation memory 331 is outputted from the AND gate AND3 as a logical product signal of the emulator ROM selection signal 186 and the inverted signal of the break acknowledge signal BACK. Therefore, the built-in ROM
12 areas are selected, break acknowledge signal BAC
When K is at 0 level, the first emulation memory 3
31 is readable / writable. The access at this time is a 16-bit bus / 2-state bus access as is apparent from the description of FIG. The chip select signal CS2 of the second emulation memory 332 is an AND gate as a logical product signal for the emulator ROM select signal 186, the break acknowledge signal BACK, the address bit 15 and the address bit 14 inversion signal. It is output from AND4.
Therefore, in the internal ROM 12 area, H'8000 to
H'BFFF is selected, break acknowledge signal B
When the ACK is at the 1 level, the second emulation memory 332 is readable / writable. The access at this time is as shown in the explanation of FIG.
Bus access for more than 3 states.

FIG. 6 shows an emulation processor 1
An example timing diagram of the break processing of FIG. In FIG. 6, although not particularly limited, the user program exists at an address corresponding to the built-in ROM 12, and a so-called stack area exists at an address corresponding to the built-in RAM 13. When 1 level is given to the break interrupt input terminal (not shown) of the emulation processor 1, the CPU 11 interrupts the processing of the user program and saves the internal control register, for example, the program counter or the condition code register in the stack area. , Fetches the address of the first instruction of the emulation program to be executed from the memory and branches to that address. At this time, since the operation after the stack operation is for emulation control and not the operation to be debugged, the break acknowledge signal BACK is set to 1 level before the stack operation. Also,
Although the emulation program exists at the address corresponding to the built-in ROM 12, it is read in three states by the bus control circuit 18 described in FIG. Although not particularly limited, one-state wait is inserted by a wait request signal dedicated to emulation.

In the case of branching from the emulation program to the user program, a predetermined return instruction may be executed to perform an operation roughly opposite to the above break processing.

According to the above embodiment, the following effects are obtained.

(1) Using the break acknowledge signal BACK indicating whether the emulation processor 1 is executing the user program or the emulation program, the first emulation memory 3 is used.
31 or the second emulation memory 33
It is possible to choose whether to use 2. At this time, the bus control circuit 18 for changing the read / write specifications (bus width, number of memory cycle states) of the CPU 11 based on the break acknowledge signal BACK, and the first emulation memory 33 according to the change.
An emulation memory control circuit 40 for chip-selecting control of the first or second emulation memory 332 is adopted. Bus control circuit 18 and emulation control circuit 4
If the CPU 11 of the emulation processor 1 is executing the user program at the address corresponding to the built-in ROM 12 based on the break acknowledge signal BACK by 0, the first emulation memory 331 is read in 16-bit data bus / 2 states / If the write operation is performed and the emulation program corresponding to the address corresponding to the built-in ROM is being executed, the second emulation memory 332 can be read / written by the 8-bit data bus / 3-state and further wait can be requested. As described above, the emulation processor 1 uses the function of the external memory access switching by the bus control circuit 18 and the accompanying access condition change as the external memory replacing the built-in ROM 12, and the high-speed access in which the allocation addresses are partially overlapped. The memory (first emulation memory 331) and the low-speed access memory (second emulation memory 332) can be selectively used. Therefore, in the microcomputer (emulation processor) 1 having a large-capacity memory in which most of the address space of the CPU 11 is allocated to the internal memory, together with the external memory (first emulation memory 331) that replaces the internal memory, Another external memory (second
The emulation memory 332) can be used by the microcomputer 1 with an access specification different from the access specification of the alternative external memory (first emulation memory 331). (2) Due to the above, the second emulation memory 3 sufficient for low-speed access for storing the emulation program
32 can be positioned as the hardware of the part that does not depend on the specifications of the microcomputer that the emulator 3 should support. As a result, it is possible to facilitate the development of products or the adaptation to changes in the microcomputer built-in memory such as ROM. (3) Further, the first emulation memory 331
Is mounted on the same circuit board as the emulation processor 1, for example, the emulation pod 3B, and the second emulation memory 332 is connected to another circuit board from the circuit board by a cable, for example, the emulator main body 3
By being mounted on A, the hardware of the part that does not depend on the specifications of the microcomputer to be supported by the emulator 3 can be commonly used for various microcomputers relatively easily or efficiently. For example, when the built-in peripheral functions of the microcomputer having the same CPU 11 are changed or added, it becomes easy to share at least the emulator main body 3A.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example,
The read / write specifications or the read / write control method are not limited to those in the above embodiment. The read / write specifications can include, in addition to the bus width and the number of states, whether to enable or disable waits.

In the above description, the case where the invention made by the present inventor is mainly applied to the emulation processor which is the field of application which is the background of the invention has been described, but the invention is not limited thereto and other semiconductor integrated circuits. The present invention can be widely applied to those in which the operation specifications of the bus access need to be changed according to the instruction or command execution state of the microcomputer.

[0037]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) A high-speed access memory and a low-speed access memory in which allocation addresses are partially overlapped as an external memory replacing the internal memory by the function of switching the external memory access by the bus control circuit and the accompanying access condition changing function. The microcomputer can be selectively used. Therefore, in a microcomputer having a large-capacity memory in which most of the CPU address space is allocated to the internal memory,
The microcomputer can be used with an external memory that replaces the built-in memory, and another external memory with an access specification different from the access specification of the alternative external memory by overlapping the address of the external memory. (2) From the above, it is possible to position the second emulation memory for storing the emulation program, which is sufficient for low-speed access, as the hardware of the portion that does not depend on the specifications of the microcomputer that the emulator should support. As a result, it is possible to facilitate the development of products or the adaptation to changes in the microcomputer built-in memory such as ROM. (3) Further, the first emulation memory is mounted on the same circuit board as the emulation microcomputer, for example, an emulation pod, and the second emulation memory is connected to the circuit board by a cable from another circuit board, for example, an emulator body. The hardware of the part that does not depend on the specifications of the microcomputer to be supported by the emulator can be commonly used for various microcomputers relatively easily or efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing an emulation processor which is an embodiment of a microcomputer according to the present invention.

FIG. 2 is a block diagram showing an example of an emulator using an emulation processor.

FIG. 3 is an address map of an emulation processor.

FIG. 4 is a block diagram showing an example of a bus control circuit included in the emulation processor.

FIG. 5 is a block diagram showing an example of an emulation memory control circuit.

FIG. 6 is a timing chart showing an example of a break operation of the emulation processor.

[Explanation of symbols]

1 Emulation Processor 3 Emulator 3A Emulator Main Body 3B Emulation Pod 4 Target System 5 System Development Device 10 Single Chip Microcomputer Section 11 CPU 12 ROM 13 RAM 18 Bus Control Circuit 180 Decoder 185 Emulator RAM Selection Signal 186 Emulator ROM Selection Signal 190 16-bit bus / two-state instruction signal 191 wait instruction signal 40 emulation memory control circuit CS1 first emulation memory chip select signal CS2 second emulation memory chip select signal 331 first emulation memory 332 second emulation memory

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical display location G06F 13/16 510 8841-5B (72) Inventor Yoshikazu Aoto 5-20, Kamimizumoto-cho, Kodaira-shi, Tokyo No. 1 stock company Hitachi Ltd. Musashi factory

Claims (7)

[Claims] 1. In a one-chip type microcomputer having a central processing unit and a memory built-in, access to a predetermined address assigned to the built-in memory is selectively controlled to be switched to access to an external memory, and the switching is performed. A microcomputer provided with bus control means for instructing to change the access condition by the central processing unit. 2. The bus control means decodes an address signal to generate a selection signal corresponding to a predetermined address assigned to the internal memory, and a predetermined acknowledge signal when the selection signal is activated. 2. The microcomputer according to claim 1, further comprising a logic circuit for instructing a predetermined access condition to a central processing unit according to the logical value of. 3. The microcomputer according to claim 2, wherein the access condition is a single condition or a plurality of conditions selected from the number of parallel bits of data when accessing and the access time. 4. An emulator in which the microcomputer according to claim 3 is mounted as an emulation microcomputer, and has an address which partially or wholly overlaps a predetermined address assigned to a built-in memory of the microcomputer. The first and second emulation memories, which are arranged as described above, one of which is a memory for substituting the built-in memory, the selection signal and the acknowledge signal generated by the decoder, and the first emulation memory And a second emulation memory, the emulation memory control means for activating and controlling a chip select signal for the first emulation memory or the second emulation memory according to the logical value of the acknowledge signal. Emulator made with a,. 5. The first emulation memory has a shorter time required for access than the second emulation memory, the first emulation memory is an object for storing a target program, and the second emulation memory is for emulator control. The emulator according to claim 4, which is a storage target of an emulation program. 6. The emulator according to claim 5, wherein the acknowledge signal is a break acknowledge signal of a microcomputer in response to a break instruction for the execution state of the target program. 7. The first emulation memory is mounted on the same circuit board as the microcomputer for emulation, and the second emulation memory is mounted on another circuit board connected to the circuit board by a cable. The emulator according to Item 6.