JPH05276153A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To manage the realization of plural synchronizations with the minimum increase of hardware, and to deal with the alteration of a parameter, that is, the increase or the decrease of the frame synchronizing bits of a data signal, and the alteration of the stability condition of a frame synchronizing signal and the synchronization by only altering the condition of an initial value or a count value, etc. CONSTITUTION:An input means 10 to select a synchronizing signal, the storage means 12 of the frame synchronizing bit, a synchronization protection deciding count value and synchronizing operation, the counting means 13 of the number of times of coincidence non-coincidence of the synchronizing bit, a comparing means 11 to decide the coincidence between an extracted frame word and a stored frame word, a designated value setting means 15 to input the initial value of the counting means 13, a shifting means 16 to execute addition and subtraction, a digit selecting means 17 to re-write a part of data, a selecting means 14 to select the data from each means 12,15 to 17 and send it to the counting means 13, a control means 19 to realize continuous frame synchronizing operation procedure, and an address selecting means 20 to determine the storage place of the storage means 12 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to one type of circuit having a basic structure even if the type of frame synchronization signal for digital data transmission, synchronization determination conditions, the number of frames to be processed, etc. are different. The present invention relates to a frame synchronization circuit that can be processed in.

[0002]

2. Description of the Related Art Generally, in signal transmission between digital data transmission devices, a frame is defined as a repeating processing unit for performing time-series signal processing. The data string of is stored and sent. On the receiving side, in order to select the data sequence in these frames, the frame synchronization signal superimposed and transmitted in a fixed time slot with a frame period (for example, the beginning of the frame) is extracted, and synchronization of this timing is established. After that, I performed necessary signal processing. In recent years, in this kind of digital signal processing, a method of simultaneously establishing several kinds of frame synchronization as a multi-frame in addition to a basic frame and a frame synchronization method suitable for an LSI have been desired, and a large number of LSIs are required for a large-scale LSI. The method of mounting the frame synchronization circuit has been adopted.

Conventionally, as shown in the block diagram of FIG. 5, this type of frame synchronization circuit has a time-sequential input signal 500 containing a frame synchronization word, a word detection circuit 50 for detecting the synchronization word from the input signal, A word generation circuit 52 that outputs a predetermined designated synchronization word, a comparison circuit 51 that compares the designated synchronization word with the synchronization word extracted from the input, and determines pass / fail.
A so-called backward protection match counting circuit 54 that counts whether or not a predetermined number of frame sync word matches are reached when the sync words continue to match, and a predetermined number of frame sync word mismatches is counted. A so-called forward protection disagreement counting circuit 55, and a synchronization determination circuit 57 that finally inputs the counting results of the coincidence and disagreement counting circuits 54 and 55 and determines whether or not the conditions are predetermined coincidence or non-coincidence determination conditions. It is composed of a hunting control circuit 58 for preventing hunting that repeats the synchronization recovery operation due to a code error in the case of out of synchronization, and a timing counting circuit 53 for controlling the basic timing of the frame synchronization word generation circuit 52.

Next, the operation of the conventional example will be described.

A frame word is extracted from the input signal 500 by the word detection section 50 and input to the comparison circuit 51. To the other input of the comparison circuit 51, the frame word generated by the word generation circuit 52 driven by the timing counting circuit 53 that generates the basic timing of the frame synchronization circuit is input. The determination signal of the comparison circuit 51 is input to the coincidence counting circuit 54 and the non-coincidence counting circuit 55 which count the coincidence / non-coincidence of the frames. A synchronization determination signal is output from the synchronization determination circuit 57 based on these counting results, and the hunting circuit 58 outputs the synchronization determination signal.
Therefore, the counting of the timing counting circuit 53 is stopped, and the continuation control, that is, the hunting control is performed. Such a frame synchronization circuit requires this circuit configuration for one basic frame synchronization word, one predetermined match / mismatch determination condition, and a predetermined number of frames. Therefore, if the above-mentioned conditions change or there are other multi-frame synchronizations, this number of circuit configurations is required in a number corresponding to each case.

[0006]

This conventional frame synchronization circuit requires a frame synchronization basic counting circuit and a frame word match / mismatch counting circuit, and a frame word comparison and determination circuit and a synchronization determination circuit, which are independent of each other. However, in order to realize a large number of frame synchronizations at the same time, there is a drawback that the hardware scale increases. In order to avoid this, it has been realized by a large-scale LSI or the like, but since the types, conditions, number, etc. of frame synchronization signals are different depending on the time in accordance with the diversified signal processing in recent years, it is difficult to develop an LSI each time. It's getting very difficult.

The object of the present invention is to identify the type of frame sync signal,
It is an object of the present invention to provide a frame synchronization circuit that establishes synchronization in a time-sequential manner with one numerical value counting circuit, one comparison / determination circuit, and a memory element even if the conditions and the number change.

[0008]

A frame synchronization circuit of the present invention comprises an input means for selecting a synchronization signal from digital signal data on which a frame synchronization signal is superimposed, a frame synchronization bit, and a synchronization protection for determining a stable synchronization operation. A storage means for temporarily storing a judgment count value and a temporary operation state necessary for the synchronization operation; a counting means for counting the number of times the synchronization bit is taken in from the input means and the number of times of coincidence / mismatch of the frame words are input. Comparing means for judging the coincidence between the frame word extracted from the data and the known frame word input from the outside or the frame word stored in the storage means, and designation for inputting the initial value of the counting means according to the external data Value setting means, data shifting means for performing addition or subtraction processing of the counting means, and writing only part of the stored data. A digit selecting means for changing, a selecting means for selecting data from the designated value setting means, the shifting means, the digit selecting means, and the storing means, and transmitting the data to the counting means, and a frame synchronization operation procedure are realized continuously in time. Control means, and address selection means for deciding a storage location of the storage means in response to the procedure.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flow chart of a sequence flow showing logical processing controlled by a control circuit of the present embodiment, and FIG. 3 is a time chart showing a processing time relationship of the present embodiment. FIG. 4 is an explanatory diagram for explaining the contents stored in the RAM 12 of this embodiment. First, in the embodiment shown in FIG. 1, an input circuit 10 for sequentially sampling and fetching frame bits (hereinafter referred to as F bits), a comparison circuit 11 for comparing the known reference data 101 with the input F bits if there is a predetermined reference frame word in advance, RA to be described later
If there is a newly stored frame word in M12, it is read and compared with the input F bit. Next, the reference frame word and the storage of each status information in the process of the frame synchronization operation procedure described later, the count value (C) of the number of times of frame capture, the count value (Cy) of the match judgment of the frame word, the mismatch judgment of the frame word RAM 12 that stores determination conditions such as the count value (Cn) of the counter, and a counting circuit 1 that performs the counting operation in the operating procedure of each process
3, the initial value of the counting circuit 13 is an externally set value 1
Designated value setting circuit 15 and counting circuit 13 set by 02
Shift circuit 16 for performing addition and subtraction processing of 1), digit selection circuit 17 for rewriting only a part of data, these designated setting circuit 15, shift circuit 16, digit selection circuit 1
7, a selection circuit 14 for selecting the data of the RAM 12 and sending it to the counting circuit 13, a control circuit 19 for controlling the operation of each process so as to perform the time sequential operation, and R by this control signal.
An address selection circuit 20 for selecting the address of the AM 12,
The finally determined frame synchronization output signal 103 and R
It is composed of an output circuit 18 for extracting the information of the AM 12 and the like to the outside.

Next, the sequence flow controlled by the control circuit 19 will be described with reference to the contents stored in the RAM 12 shown in FIGS. Here, an example will be described in which the synchronization state, which is the flow on the left side of step S1 in FIG. The input circuit 10 samples and fetches F bits of the input data (step S2). At this time, the counting circuit 1
RA storing the F bit string up to the previous frame in 3
Stored data of F bits (8 bits configuration of F1 to F8 in FIG. 2) of a predetermined address (aaaH) from M12 is called by shifting the F bit string by 1 bit via the shift circuit 16. The sampled new F bit is added to the end of the F bit string and stored as a new F bit string at a predetermined address (aaaH) of the RAM 12. Next, the count value (C) of the number of fetches of F bits
Is taken into the counting circuit 13 from a predetermined address (ccccH) of the RAM 12 and incremented by 1 and stored again at the same address (step S3). At this time, the count value of the number of times of acquisition that is known in advance and the number of times of actual acquisition (C)
If the number of acquisitions is not completed, the process proceeds to the next frame synchronization sequence, and if completed, the process proceeds to the word detection sequence (step S4). That is, the F-bit string is addressed (aaaa) in the same manner as described above.
H) is taken into the counting circuit 13. The expected value of frame synchronization is the reference data 101 which is a known standard frame word.
Is input to the comparison circuit 11 from the outside as the counting circuit 13
Compare with the value of. If the comparison values match, the next frame sequence starts, and if they do not match, 1 is added to the mismatch determination count value (Cn) stored in the predetermined address (eeeeH) of the RAM 12 (steps S6 and S7).
When this (Cn) does not exceed the count value N determined by the stable condition of synchronization, the (Cn) value is set to the address (eeeeH).
It is stored again in and is moved to the next frame synchronization sequence. (C
If n) exceeds (N), it is determined that synchronization is lost, and R
"0" is written in the designated bit (S1) of the predetermined address (bbbbH) of the AM 12 (1: synchronous, 0: asynchronous). Further, "0" is written in the (Cy) value of the address (ddddH) to reset the coincidence determination count value (steps S8 and S9).

Now, the internal status monitoring bit of the address bbbbH of the RAM 12 in FIG. 4 will be described. S
1 is a synchronization determination bit, S2 is an F bit capture completion determination bit, S3 is a determination bit whether the word detection coincidence count value (Cy) exceeds the count value (Y: backward protection value) determined by the synchronization stability condition, and S4 is word detection. A determination bit whether the disagreement count value (Cn) exceeds the count value (N: forward protection value), S
Reference numeral 5 is a match determination bit of the word detection result, and S6 to S8 are other bits that are not directly related to frame synchronization. These S1 to S5 operate so that the digit selection circuit 17 selects the corresponding 1 bit of the designated address of the memory at each division, and the selection circuit 14 rewrites only the corresponding bit of the memory content. Therefore, the frame synchronization state monitoring can be easily determined by reading these monitoring bits. For example, the synchronization determination can be immediately known by periodically checking S1, and the synchronization timing required for signal processing can be specified by simultaneously checking S1 and S5 for each frame cycle.

As described above, the designated value setting circuit 15 sets the initial value of the counting circuit 14 and the designated value for counting to the initial setting input 1
This is for input from the RAM 02, so that the synchronization signal of any frame length and the stability condition can be freely changed to
Can be stored in 2. The control circuit 19 controls the whole of the counting circuit 13 and the selection circuit 14 according to the above-mentioned flow, and also controls the address selection circuit 20 so as to operate in a time sequential manner.
Configured to specify the memory address to.
The output circuit 18 outputs the output signal of the synchronization result and the status monitoring bit described above to the outside. Frame synchronization can be realized by sequentially repeating the above processing as shown in the time chart of FIG. Further, the processing sequence of the process of returning from the out-of-synchronization state to the synchronization is represented by the flow on the right side of the sequence flow of FIG. 2, but it can be realized by the same sequence as described above.

[0013]

As described above, according to the present invention,
One counting means for frame synchronization processing, a storage means for temporarily storing a count value, a frame word, etc., a comparison and determination means for the count value and frame words, and a control circuit for repeating frame synchronization continuously in a time-sequential manner. By including the above, even when a plurality of frame synchronizations are realized, it can be realized with a minimum increase in hardware. Moreover, it is possible to flexibly cope with the change of the parameter, that is, the increase / decrease of the frame sync bit of the data signal, the change of the frame sync signal, and the change of the synchronization stability condition, only by changing the conditions such as the initial value and the count value.

[Brief description of drawings]

FIG. 1 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a sequence flow diagram of the frame synchronization circuit of the present embodiment.

FIG. 3 is a time chart showing a relationship between processing times according to this embodiment.

FIG. 4 is an explanatory diagram showing stored contents of a RAM of this embodiment.

FIG. 5 is a block diagram of a conventional frame synchronization circuit.

[Explanation of symbols]

 10 Input Circuit 11 Comparison Circuit 12 RAM 13 Counting Circuit 14 Selection Circuit 15 Designated Value Setting Circuit 16 Shift Circuit 17 Digit Selection Circuit 18 Output Circuit 19 Control Circuit 20 Address Selection Circuit 50 Word Detection Circuit 51 Comparison Circuit 52 Word Generation Circuit 53 Timing Count Circuit 54 Match Count Circuit 55 Mismatch Count Circuit 56 Hunting Control Circuit 57 Synchronization Judgment Circuit

Claims (2)

[Claims] 1. An input means for selecting a sync signal from digital signal data on which a frame sync signal is superimposed, a frame sync bit, a judgment count value of sync protection for judging stable operation of sync, and a temporary necessary for sync operation. Storage means for temporarily storing a specific operation state, counting means for counting the number of times the synchronization bit is taken in from the input means and the number of times of coincidence / disagreement of frame words, and a frame word extracted from input data and externally input Comparing means for determining a match with the known frame word or the frame word stored in the storage means, designated value setting means for inputting an initial value of the counting means according to external data, addition of the counting means or Data shift means for performing subtraction processing, digit selection means for rewriting only a part of the stored data, and the designated value setting means Stage, the shift means, the digit selection means, the selection means for selecting the data from the storage means and sending the data to the counting means, the control means for realizing the frame synchronization operation procedure continuously in time, and the control means for responding to the procedure. And a address selecting means for determining a memory location of the memory means. 2. The storage means comprises a RAM, and includes a frame synchronization bit, an internal status monitoring bit, a synchronization determination bit, a frame capture completion determination bit, a backward protection value determination bit, a forward protection value determination bit, and a word detection result. 2. The frame synchronization circuit according to claim 1, wherein the coincidence determination bit and the coincidence determination value of the frame are temporarily stored.