KR100299339B1 - Synchronizing device - Google Patents

Abstract

The miniaturization and cost reduction of the device are realized by eliminating the FIFO, which is essential in the conventional device. The original packet unit data signal is reconstructed from the input data signal Data_In, in which an MPEG standard data signal in which a packet composed of 204 8-bit long unit data columns is allocated to a 6-bit long unit data column. 8-bit long data is sequentially extracted from two 6-bit long unit data sequentially held in buffers BS1 and BS2. The validity of the position of the head word is verified based on whether or not the sync code Cd indicating the head word of the packet appears repeatedly in the period of the packet. Since it is determined whether the packet cycle has elapsed based on the count value counted in synchronization with the extraction signal Dout, the FIFO required by the conventional apparatus becomes unnecessary.

Description

Synchronizer {SYNCHRONIZING DEVICE}

The present invention relates to a synchronization device, and more particularly, to an improved synchronization device for realizing miniaturization of a device by eliminating the first-in-first-out (FIFO) required in the conventional device.

40 is a block diagram showing the configuration of a conventional synchronization device that is the background of the present invention. The synchronization device 150 converts an input data signal Data_In consisting of a column of unit data of 1 bit length into an output data signal Data_0ut consisting of a column of unit data of L bit length. The synchronization device 150 includes a synchronization control unit 151, L bit shift registers 152 and 154, a FIFO 153 and a comparators 155 and 156.

The unit data of one bit length constituting the input data signal Data_In is input to the L bit shift register 152 in synchronization with the pulse of the clock signal Clk (that is, every one clock cycle). The L bit shift register 152 always keeps the L unit data input in the L clock cycle period going back from the present to the past. That is, the L bit shift register 152 corresponds to a serial-parallel conversion device that converts serial data into parallel data.

Every one clock cycle, the oldest unit data among the L unit data held in the L bit shift register 152 is transmitted to the FIFO 153. An example is a case where the output data signal Data_Out is an MPEG standard data signal, that is, a data signal composed of 204 consecutive packets of unit data of 8 bits in length.

In this case, the FIFO 153 has a storage capacity of 8 x 204 bits. Therefore, the unit data input to the FIFO 153 is output after 8 x 204 clock cycles. Every one clock cycle, one bit long unit data that has passed through the FIFO 153 is input to the L bit shift register 154. L bit shift register 154 is configured in the same manner as L bit shift register 152.

The synchronization controller l51 is a device portion that functions to control the operations of the comparators 155 and 156 and the like. The synchronization control unit 151 is input with a synchronization code Cd of L bit length indicating the head of the packet. The comparator 155 compares the value of the sync code Cd transmitted from the sync control unit 151 with the L bit data held in the L bit shift register 152. Similarly, the comparator 156 compares the value of the sync code Cd transmitted from the sync control unit 151 with the L bit data held in the L bit shift register 154.

When the comparators 155 and 156 detect that the L bit data of the L bit shift register 152 and the L bit data of the L bit shift register 154 coincide with the synchronization code Cd, the synchronization controller At 151, this sync code Cd is recognized as a head word of a packet. Then, the column of unit data of one bit length is divided into L bit units so as to follow the head word of the L bit length. As a result, unit data of L bit length is output as the output data signal Data_Out. This is realized by the synchronization control unit 151 by outputting the L bit data held in the L bit shift register 154 as the output data signal Data_Out every L clock cycles.

Since the conventional synchronization device is configured as described above, a large storage capacity is required in the FIFO 153. This has been an obstacle in reducing the size and manufacturing cost of the device by reducing the number of elements constituting the device.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems in the conventional apparatus, and to provide a synchronization apparatus capable of realizing miniaturization of the apparatus and reduction in manufacturing cost by eliminating the need for a FIFO.

1 is a block diagram showing an example of usage of the apparatus according to each embodiment;

2 is an explanatory diagram showing a schematic operation of the apparatus according to each embodiment;

3 is an overall block diagram of the apparatus of Example 1;

4 is a block diagram of a data extraction unit of FIG. 3;

5 is a flowchart of an operation of the shift register of FIG. 4;

6 is a schematic diagram showing an allocation pattern of unit data;

7 is an operation explanatory diagram of the pattern data extraction unit of FIG. 4;

8 is an explanatory diagram of the operation of the pattern data extraction unit of FIG. 4;

9 is an explanatory diagram of the operation of the pattern data extraction unit of FIG. 4;

10 is a flowchart of an operation of the state transition controller of FIG. 4, and the like;

11 is an explanatory view of the operation of the comparator of FIG. 4;

12 is an operation explanatory diagram of a comparison unit of FIG. 4;

13 is an explanatory diagram of the operation of the comparator of FIG. 4;

14 is an operation explanatory diagram of the state transition controller of FIG. 4;

15 is an operation explanatory diagram of the state transition controller of FIG. 4;

16 is an operation explanatory diagram of the state transition controller of FIG. 4;

17 is an explanatory diagram of the operation of the state transition controller of FIG. 4;

18 is a block diagram of a synchronization controller of FIG. 3;

19 is a block diagram of a synchronization detector of FIG. 18;

20 is a flowchart of an operation of a synchronization detector of FIG. 19;

21 is an explanatory diagram of the operation of the synchronization detector of FIG. 19;

22 is an explanatory diagram of the operation of the synchronization detector of FIG. 19;

23 is a flowchart of an operation of a head signal generator of FIG. 18;

24 is a flowchart of an operation of a final signal generator of FIG. 18;

25 is a flowchart of an operation of a synchronization signal generator of FIG. 18;

26 is a flowchart of an operation of a data output unit of FIG. 18;

27 is a block diagram of a clock modulator of FIG. 4;

28 is an explanatory diagram of the operation of the clock modulator of FIG. 27;

29 is a block diagram of a synchronization detector according to the second embodiment;

30 is a block diagram of a lock level changing unit of FIG. 29;

FIG. 31 is a schematic diagram showing a storage space of the tag memory of FIG. 30;

32 is a schematic diagram showing a storage space of the tag memory of FIG. 30;

33 is a flowchart of an operation of the lock level changing unit of FIG. 30;

34 is a flowchart of an operation of a synchronization detector of FIG. 29;

35 is a flowchart of step S150 of FIG. 34;

36 is an operation explanatory diagram of a synchronization detector of FIG. 29;

37 is a block diagram of a synchronization controller according to the third embodiment;

38 is a flowchart of an operation of a data output unit of FIG. 37;

39 is an operation explanatory diagram of a synchronization detector of FIG. 37;

40 is a block diagram of a conventional synchronization device.

Explanation of symbols for the main parts of the drawings

3: clock modulator 11: shift register

12: pattern data extraction unit 16: comparison unit (first comparison unit)

18: state transition control unit 19: mode change unit

22: mode shifter 23: pattern selector

32: leading signal generator 33: final signal generator

35: data output section 41: comparison section

42: lock level generator 43: process number generator

62: tag memory (tag storage)

63: Np counter (process number generation unit)

BS1, BS2: Buffer Data_In: Input Data Signal

Dout: Extraction signal H: Leading word

LL: Lock level MClk: Modulated clock signal (clock signal)

Np, Pd: Processing Number

According to an embodiment of the present invention, a first data signal configured on the basis of a packet having a column of first unit data having P (≧ 2) L (≥1) bits in length is a second unit data of m (≧ 1) bit length. A synchronization device for inputting a second data signal, which is allocated in the column of, as an input data signal, and reconstructing and outputting the first data signal from the input data signal.

The apparatus of the first aspect of the invention also has a shift register having a plurality of buffers each having an m-bit storage capacity and sequentially holding the second unit data constituting the input data signal, and the first unit data. Corresponds to the first through K (≥1) patterns sequentially assigned to the second data signal, and extracts data of L bit length from the data held in the shift register, thereby extracting the first through Kth. A pattern data extraction unit for acquiring data, a first comparison unit for comparing each of the first to Kth extracted data with a synchronization code as an indication of a head word of the packet, and the first to Kth extracted data A pattern selection unit for selecting and outputting any one of the extracted signals as an extraction signal, and controlling the selection operation of the pattern selection unit according to the synchronous state and the asynchronous state. And a state transition and the controller, the synchronization determination section for determining whether the synchronous state and any state of the asynchronous state.

The state transition control unit may further include: a mode shift unit configured to sequentially select the first to K th extraction data sequentially into the pattern selection unit so as to sequentially extract data in units of L bits from the input data signal; In the asynchronous state only, in the comparison by the first comparison unit, extraction data instructed by the mode shift unit to the pattern selector whenever only the k (1 ≦ k ≦ K) extracted data matches the synchronization code. And a mode changer for setting the sequential selection of k as the candidate for the leading word by setting the kth extracted signal corresponding to the kth pattern, and changing this to sequential selection starting from the start.

Further, the synchronization determination unit is a process number generation unit capable of cyclically counting P integers as process numbers in synchronization with the extraction signal when outputted, and a second comparison unit for comparing the extraction signal with the synchronization code. And a state determination unit that determines a transition between the synchronous state and the asynchronous state based on the processing number and the result of the comparison in the second comparison unit.

In the asynchronous state, if the correspondence between the extracted signal corresponding to the candidate and the synchronization code is repeatedly obtained at a first frequency or more in the comparison in the second comparison unit, The candidate for which the coincidence and concurrency is determined is determined as a determinant leader word, and in the synchronous state, the extraction corresponding to the definite leader word is compared in the second comparison unit. If a discrepancy between the signal and the sync code is repeatedly obtained at a second predetermined frequency or more, the transition to the asynchronous state is determined, and the determination is made as to whether or not the extracted signal corresponds to the candidate or the definitive headword. Is executed based on the process number.

In the apparatus of the second invention, in the synchronization apparatus of the first invention, in the asynchronous state, the process number generation unit can obtain a match between the extracted signal and the synchronization code in the comparison in the second comparison unit. Each time the processing number is returned to a predetermined value, and the state determining unit returns to the predetermined value after the processing number has passed one previous value of the predetermined value, the extraction signal is the candidate or the determined head. We judge that it is equivalent to language.

In the apparatus of the third aspect of the invention, in the synchronization apparatus of the first aspect of the invention, the state determination unit further includes a tag storage unit, and the state determination unit is an asynchronous state, wherein the processing number when the extraction signal to which the candidate is set is output. Is stored as the tag in the tag storage section, and then the processing number is compared with the tag stored in the tag storage section to determine whether the extracted signal corresponds to the candidate.

Embodiment of the Invention

<1. Introduction>

FIG. 1 is a block diagram showing an example of usage of the synchronization device of each embodiment described below. In this example, the synchronization device 101 is provided between the 64 QAM type demodulator 121 and the RS (Reed Solomon) type decoder 122. These apparatuses, for example, target data signals encoded on the basis of the MPEG standard, which is a representative standard in moving picture compression processing.

2 is an operation explanatory diagram showing an outline of the operation of the apparatus of FIG. The data signal D1 obtained by encoding image data based on the MPEG standard is configured in units of a certain number of data strings called "packets". The packet Pkt is configured as a column of unit data of 8 bits (= 1 byte) in length, and one packet Pkt contains 204 unit data. In addition, the synchronization code Cd as an identification mark is assigned to the head word H, which is the unit data located at the head of one packet Pkt (that is, immediately after the break of the packet Pkt). The sync code Cd is set to, for example, the value "47" in hexadecimal ("01000111" in the case of = binary, and is also expressed as "8'h47").

The data signal D1 is modulated by a 64 QAM type modulator (not shown) and then transmitted to the transmission path. The signal received through the transmission path is demodulated by demodulator 121 (FIG. 1). Unlike the original data signal D1, the data signal D2 output from the demodulator 121 is configured as a six-bit unit data string.

The data signal D2 is equivalent to that in which the data string constituting the data signal D1 is reconstructed by six bits. That is, the data signal D2 is allocated such that the 8-bit length unit data, which is a structural unit of the packet Pkt of the data signal D1, spans a plurality of 6-bit length unit data. Data signal D1 Taking sync code Cd (= 47) assigned to head H of one packet Pkt as an example, this sync code Cd is divided into two adjacent units of data signal D2, for example, as shown in FIG. Extends to data.

The role of the synchronization device 101 lies in synchronization, that is, reconstruction of the data signal D1 into the data signal D2. The synchronization device 101 searches for the head word H of the packet Pkt included in the data signal D2 on the basis of the synchronization code Cd, and reconstructs the data signal D1 composed of the columns of the packet Pkt. The reconstructed data signal D1 is a data signal D3, which is transmitted from the synchronization device 101 to the decoder 122. The decoder 122 decodes the data signal D3 and restores the image data before encoding.

The synchronization device of the present invention generally converts a data signal configured as a column of unit data of m (≥1) bit length into a data signal configured as a column of unit data of L (> m) bit length, A device having a function of reconstructing a data signal in a packet form. In each of the following embodiments, an example of handling the data signal D1 of the MPEG standard illustrated in FIG. 2, that is, a data signal D2 composed of a column of 6-bit long unit data and a data composed of 8-bit long unit data An example of conversion to the signal D3 is described (example of m = 6 and L = 8). However, the synchronization device corresponding to the general combination of m and L (> m) can be configured similarly.

<2. Example 1

3 is a block diagram showing the overall configuration of the synchronization device 101 according to the first embodiment. This synchronization device 101 is provided with a data extraction unit 1, a synchronization control unit 2, and a clock modulator 3. An input data signal Data_In, a clock signal Clk, a synchronization code Cd, and a reset signal RST are input to the synchronization device 101 as an input signal.

The input data signal Data_In is a data signal corresponding to the data signal D2 shown in FIG. 2, that is, a data signal composed of a column of unit data having a length of 6 bits. The clock signal Clk is a clock signal input in synchronization with the 6-bit unit data included in the input data signal Data_In. That is, whenever a 6-bit unit data is input as the input data signal Data_In, one pulse is input as the clock signal Clk.

The synchronization code Cd is a constant value set in the synchronization device 101 from the demodulator 121, for example, at the start of processing in accordance with the type of data to be processed. When the encoded data based on MPEG illustrated in FIG. 2 is the processing target, a value of "47" is given, for example, as the sync code Cd. The reset signal RST is a signal input by, for example, a reset operation of an operator (operator), and functions as a signal for instructing initialization of the state of each part of the synchronization device 101.

The synchronizing device 101 performs an operation based on these input signals and outputs an output data signal Data_Out, a standby state display signal Wt, a modulated clock signal MClk, a synchronization signal Sync, a leading signal Sync_Head, and a final signal Sync_Tai1 as output signals. The output data signal Data_Out is a data signal corresponding to the data signal D3 shown in Fig. 2, that is, a data signal that is configured as a column of unit data of 8 bits in length and has a format of a packet Pkt.

The data extraction unit 1 sequentially extracts 8-bit unit data constituting the packet Pkt from the input data signal Data_In in synchronization with the pulse of the clock signal Clk, and transmits the extraction signal Dout to the synchronization control unit 2. do. In addition, the data extraction unit 1 outputs a standby state display signal Wt indicating a pause state of extraction, that is, a "standby state" in a non-extractable clock cycle (one cycle of the clock signal Clk) that occurs periodically. .

The synchronization control unit 2 is a device portion whose main task is to control the data extraction unit 1, and in particular, displays the intervals of the lock level LL and the packet Pkt which are variables representing the degree of possibility of the synchronization state. The sync signal Sync is calculated and transmitted to the data extraction unit 1. The data extraction section 1 performs the extraction operation based on these lock level LL and synchronization signal Sync. The synchronization control unit 2 also outputs the leading signal Sync_Head for indicating the beginning of the packet Pkt and the final signal Sync_Tail for indicating the end of the packet Pkt, and outputs the extraction signal Dout in accordance with the value of the standby state display signal Wt. Output as data signal Data_Out.

The clock modulator 3 generates a modulated clock signal MClk based on the clock signal Clk and the standby state display signal Wt. The modulated clock signal MClk is a clock signal that is missing a pulse in a period in which the clock cycle is in the "standby state", that is, the period in which the standby state display signal Wt is active. That is, the pulse of the modulated clock signal MClk is output data signal Data_Out, which is output whenever valid data constituting the packet Pkt is output. The output signals Wt, Sync_Head, Sync_Tail, and MClk are supplied to the decoder 122 together with the output data signal Data_Out.

<2-1. Data Extractor>

4 is a block diagram showing the configuration of the data extraction unit 1. The data extraction section 1 includes a shift register 11, a pattern data extraction section 12, a comparison section 16, a lock level check section 17, a state transition control section 18 and a pattern selection section 23. It is. In addition, the state transition control unit 18 is provided with a mode change unit 19 and a mode shift unit 22.

The shift register 11 has buffers BS1 and BS2 connected in two stages. These buffers BS1 and BS2 each have a storage capacity of 6 bits. The data signal stored in each of the buffers BS1 and BS2 is output to the pattern data extraction section 12. In addition, input data signal Data_In, clock signal Clk, and reset signal RST are input to the shift register 11 as an input signal, and the shift register 11 operates based on these input signals.

5 is a flowchart showing the flow of operation of the shift register 11. When the shift register 11 starts to operate, first, in step S1, it is determined whether the pulse of the clock signal Clk rises. The process of step S1 is repeated until a rise is obtained, and if a rise is obtained, the process proceeds to step S2. That is, step S1 is a step of timing adjustment so that the process of step S2 or less starts in synchronization with the rising edge of the clock signal Clk.

Step S2 determines whether the reset signal RST is active (in the following example, the value "0"). If the reset signal RST is active, the reset process of step S3 is executed. That is, the stored value of each bit in the pair of buffers BS1, BS2 is set to " 0 ". On the other hand, if the reset signal RST is in the normal state (ie, the value " 1 "), the process of step S4, which is a normal process, is executed. In other words, six bits of unit data stored in the buffer BS1 are recorded in the buffer BS2, and six bits of unit data of the input data signal Data_In are recorded in the buffer BS1. In other words, the buffers BS1 and BS2 perform a shift operation.

When the process of step S3 or S4 ends, in step S5, it is determined whether or not the process is to be terminated. For example, when it is determined that the process should be terminated, for example, when communication is terminated or when the power supply must be turned off, the process is terminated. In contrast, if it is determined that the process should not be terminated, the process returns to step S1. As described above, the process loop of steps S1 to S5 is repeatedly executed until the determination that the process should be terminated is obtained.

<2-2. Pattern Data Extraction Unit>

Referring back to FIG. 4, the pattern data extractor 12 includes first to third pattern data extractors 13, 14, and 15. To each of these first to third pattern data extracting units 13, 14 and 15, data signals stored in both of the buffers BS1 and BS2 are input.

FIG. 6 is an explanatory diagram showing a pattern in which 8-bit length unit data constituting the packet Pkt is allocated among the input data signal Data_In configured as a string of 6-bit unit data. As shown in Fig. 6, the input data signal Data_In is composed of unit data consisting of six bits from the zeroth bit corresponding to the least significant bit (LSB) to the fifth bit corresponding to the most significant bit (MSB). have. There are three types of patterns PTl, PT2 and PT3 shown in Fig. 6 as a pattern to which unit data of 8 bits length is assigned to the input data signal Data_In.

These patterns PT1, PT2, PT3 all span two 6-bit long unit data adjacent to each other. The pattern PT1 consists of all of the zeroth to fifth bits of one unit data and the fourth and fifth bits of the next unit data. The pattern PT2 consists of the 0th to 3rd bits of one unit data and the 2nd to 5th bits of the next unit data. Further, the pattern PT3 is composed of both the zeroth and first bits of one unit data and the zeroth to fifth bits of the next unit data.

The 8-bit-long unit data constituting the packet Pkt are allocated to the input data signal Data_In tightly (to avoid empty bits) in the order of the patterns PTl, PT2, PT3, PTl, PT ... The first to third pattern data extracting units 13, 14, and 15 each have 8 bits corresponding to patterns PTl, PT2, PT3, respectively, from data of two units of input data signal Data_In stored in buffers BS1, BS2. Extract the data from.

That is, as shown in FIG. 7, the first pattern data extracting unit 13 extracts 8-bit data corresponding to the pattern PT1 from two adjacent 6-bit unit data stored in the buffers BS1 and BS2. Extract. In addition, as shown in Fig. 8, the second pattern data extracting unit 14 includes 8-bit data corresponding to the pattern PT2 from two adjacent 6-bit unit data stored in the buffers BS1 and BS2. Extract Similarly, the third pattern data extraction unit 15 extracts 8 bits of data corresponding to the pattern PT3 as shown in FIG. 9.

In this case, among the 8-bit data extracted by the first to third pattern data extracting units 13, 14 and 15, there is only one true 8-bit unit data worth extracting. Of course not. That is, the first to third pattern data extracting units 13, 14, and 15 may be 8-bit long unit data allocated to them among the two columns of 6-bit long unit data stored in the buffers BS1, BS2. This function extracts all candidates. The 8-bit data extracted by the first to third pattern data extractors 13, 14, and 15 are transmitted to the comparator 16 and the pattern selector 23, respectively.

<2-3. State Transition Control, etc.>

10 is a flowchart showing the flow of operations of the comparison unit 16, the lock level check unit 17, the state transition control unit 18, and the pattern selection unit 23. As shown in FIG. Also in this operation flow, steps S11 and S26 corresponding to steps S1 and S5 of Fig. 5 relating to the operation flow of the shift register 11 are provided, and the steps S11 to S26 are determined until it is determined that the process should be terminated. The process loop runs repeatedly. In addition, the process of step S12 and below is started in synchronization with the rising edge of the clock signal Clk.

The comparison process of steps S12 and S13 is performed by the lock level check unit l7. In these steps S12 and S13, the values of the synchronization signal Sync and the lock level LL transmitted from the synchronization control unit 2 are compared with predetermined values, respectively. In addition, the comparison process of steps S14 to S16 is performed by the comparison unit 16. In these steps S14 to S16, the data of the patterns PT1 to PT3 extracted by the first to third pattern data extraction units 13 to 15, respectively, are compared with the synchronization code Cd.

The state transition control unit 18 executes the mode decision by the process of step S17 or less in accordance with these comparison results. Here, the mode expresses the type of the selection operation in the pattern selection unit 23 (FIG. 4), as will be described later, and four types of modes of the first to fourth modes are defined.

When the synchronization signal Sync is active (value "1" in the following example), that is, when the clock cycle corresponds to the division of the packet Pkt, or when the value of the lock level LL is "0", that is, the device is When it is in the asynchronous state which has not reached the synchronous state, any of steps S17 to S20 is selectively executed according to those results with reference to the comparison result in steps S14 to S16. On the contrary, when the clock cycle is not a partition of the packet Pkt, and when the lock level LL is a value of "1" or more corresponding to the synchronous state, the process of step S20 is executed without referring to the comparison result in steps S14 to S16. .

In the comparison processing of steps S14 to S16, if it is determined that only one of the data of the three types of patterns PTl, PT2, PT3 matches the synchronization code Cd, in which of the modes is the current mode in steps S17 to S19? Regardless, the mode is set to the first to third modes, respectively. This process is executed by the mode change unit 19 provided in the state transition control unit 18.

On the other hand, in the comparison processing of steps S14 to S16, if all of the data of the three types of patterns PTl, PT2, PT3 do not match the synchronization code Cd or if two or more match, it is determined that the mode is in step S20. Is shifted from the current mode to the next mode. The same applies to the case where the comparison process of steps S14 to S16 is not referred to. The shift of the mode means that the modes are cyclically shifted one by one in the order of the first, the second, the third, the fourth, the first, the second, the ...

When the process of step S20 ends, the process proceeds to step S21 to determine whether the new mode is the fourth mode. If not in the fourth mode, in step S22, the standby state display signal Wt is set to a steady state (in the following example, the value "0"). On the contrary, if it is determined that it is the fourth mode, in step S23, the standby state display signal Wt is set to active (value "1"). When any process in steps S17 to S19 has passed, the process of step S22 is executed because the new mode is not the fourth mode. The processes of these steps S20 to S23 are performed by the mode shift unit 22 provided in the state transition control unit 18.

When step S22 has passed, the process of step S24 is executed. That is, the data of the patterns PTl, PT2, PT3 are selected in correspondence with the newly set first to third modes, respectively, and are output as the extraction signal Dout. When step S23 has passed, the process of step S25 is executed. In other words, the current extraction signal Dout is maintained without being updated. When either of the processes of steps S24 and S25 ends, the process proceeds to step S26.

The process of steps S24 and S25 is performed by the pattern selector 23. Therefore, as shown schematically in FIG. 4, the pattern selection unit 23 responds to the mode signal output from the mode shift unit 22, that is, the signal representing the mode, to form the first to third pattern data. It can be comprised as a switch circuit which selects and outputs the output signal of the extraction part 13, 14, 15, or the present value hold | maintained in a latch.

11 to 17 are diagrams illustrating the relationship between the extraction signal Dout selected based on the operation flow of FIG. 10 and the input data signal Data_In. First, in any clock cycle, it is stored in the shift register 11 when it is in an asynchronous state (lock level LL = 0) or when the clock cycle corresponds to the division of the packet Pkt (synchronization signal Sync = 1). Of the three types of extraction patterns PTl, PT2 and PT3 relating to the unit data of two columns, when only the pattern PT1 coincides with the synchronization code Cd, that is, the example shown in FIG. 11 and does not correspond to FIGS. 12 and 13. Assume the case as an example.

In this case, since the mode is set to the first mode in the clock cycle, the data of the pattern PT1 (which coincides with the sync code Cd) shown in Fig. 14 is output as the extraction signal Dout. This means that in this clock cycle, 8-bit-long unit data constituting the packet Pkt is assigned to the input data signal Data_In in the form of a pattern PT1, and its value is determined to match the sync code Cd.

If this judgment is justified, the 8-bit unit data is then allocated in the order of patterns PT2, PT3, PTl, PT2, ... Correspondingly, each time the clock cycle advances one by one (i.e. each time the clock signal Clk rises), the mode shifts sequentially to the second and third modes, and accordingly, the data output as the extraction signal Dout is shown in FIG. 15. The data is shifted to the data of the patterns PT2 and PT3 shown in Fig. 16, respectively.

In the next clock cycle, as shown in Fig. 17, there is no data to be duly extracted in the shift register 11. At this time, the mode is shifted to the fourth mode, and all of the data of the patterns PTl, PT2, PT3 extracted from the shift register 11 are not selected as the extraction signal Dout, and thus the value of the extraction signal Dout in the immediately preceding clock cycle. Is maintained. That is, in this clock cycle, the data extraction section 1 is placed in a pause state, that is, a "wait state". Only in this "standby state", the standby state display signal Wt becomes active. That is, the standby state display signal Wt functions as a signal for displaying the "standby state".

In the next clock cycle, the mode returns to the first mode, and the data of the pattern PT1 shown in Fig. 14 is output as the extraction signal Dout. In this case, it goes without saying that the data of the pattern PTl is generally not the sync code Cd. Hereinafter, four modes of the selection of the patterns PTl, PT2, PT3 and the "standby state" are sequentially developed as the mode cyclically and sequentially shifts (i.e., shifts) between the first to fourth modes every clock cycle. .

This shift operation is performed repeatedly until an asynchronous state occurs (lock level LL becomes "0"), or until the clock cycle corresponds to the segment of packet Pkt (synchronized signal Sync becomes "1"). . When the lock level LL becomes "0" or when the synchronization signal Sync becomes "1", it is determined which one of Figs. 11 to 13 corresponds to, for example, only in Fig. 12, regardless of the current mode. The mode is changed to the second mode, and the subsequent modes are cyclically shifted in the order of the third, fourth, one, two, and three modes.

In addition, if it determines with FIG. 13 only, a mode is changed to a 3rd mode, and subsequent modes are cyclically shifted in order of 4th, 1, 2, 3, 4 mode. In addition, when it does not correspond to any of FIGS. 11-13, or when it corresponds to several, cyclic shift operation is maintained as it is.

That is, normally, the operations of the first to fourth modes corresponding to the selection of the patterns PTl, PT2 and PT3 and the "standby state" are cyclically developed in this order. If only one of the data of the patterns PTl, PT2, PT3 coincides with the sync code Cd when the lock level LL becomes "0" or the sync signal Sync becomes "1", the mode is determined according to the result. Jumps to any one of the first to third modes.

The 8-bit long unit data constituting the packet Pkt is input to the input data signal Data_In in the order of patterns PTl, PT2, PT3, PTl, PT2, ... on the basis of the position of any 6-bit unit data. It is allocated tightly. In order for the data extracting unit 1 to extract the 8-bit long unit data string from the input data signal Data_In, not only the order of the patterns PTl, PT2, PT3, PTl, PT2, ... There can be a total of three types of extraction sequence with the order of two types of pattern PT2, PT3, PTl, PT2, PTl, ... and the pattern PT3, PTl, PT2, PTl, PT2, ... have.

According to the comparison result of the data of the patterns PT1, PT2, PT3 and the synchronization code Cd, the mode jumps to any one of the first to third modes, so that the synchronization code Cd read out of the input data signal Data_In is the three types of patterns PTl, PT2. On the basis of which PT3 is assigned, it is equivalent to selecting one of three types of order as a subsequent extraction order. At this time, the order including the pattern to which the sync code Cd is assigned is selected. In the normal period, continuous shifting of the mode without jumping means that extraction in the selected order is continued.

First, the selected order is not necessarily a valid order. In the input data signal Data_In, 8-bit data extracted in a pattern different from a legitimate pattern among three types of patterns PTl, PT2 and PT3 may sometimes have the same value as the sync code Cd. When the device is in an asynchronous state or when it is determined that the partition of the packet Pkt has been reached, jumping from one of the first to the third modes to the mode based on the sync code Cd was an error in the selected extraction order. This is to allow modifications in the proper order.

<2-4. Synchronization Control Unit and Synchronization Detector>

18 is a block diagram showing the configuration of the synchronization control unit 2. The synchronization controller 2 includes a synchronization detector 31, a head signal (head signal) generator 32, a final signal (tail signal) generator 33, a synchronization signal generator 34, and a data output unit. 35 is provided. The synchronization detection unit 31 and the lock level check unit 17 (FIG. 4) constitute a synchronization determination unit of the present invention.

As the input signal, the synchronization control unit 2 receives the synchronization code Cd, the clock signal Clk, the reset signal RST, the standby state display signal Wt and the extraction signal Dout. The standby state indication signal Wt and the extraction signal Dout are supplied from the data extraction section 1. The synchronization detection unit 31 calculates the lock level LL referred to by the data extraction unit 1 and also calculates the process number Pd referred to by the head signal generation unit 32. The head signal generator 32, the final signal generator 33, and the sync signal generator 34 generate and output the head signal Sync_Head, the last signal Sync_Tai1, and the sync signal Sync, respectively. In addition, the data output unit 35 outputs the output data signal Data_Out based on the extraction signal Dout.

19 is a block diagram showing the internal configuration of the synchronization detector 31. As shown in FIG. The synchronization detector 31 includes a comparison unit 41, a lock level generator 42, a process number generator 43, a reset determination unit 44, and a standby state determination unit 45. The lock level generator 42 and the lock level check unit 17 (FIG. 4) constitute a state determination unit of the present invention.

20 is a flowchart showing the flow of the operation of the synchronization detector 31. Also in this operation flow, steps S41 and S62 corresponding to steps S1 and S5 of Fig. 5 relating to the operation flow of the shift register 11 are provided, respectively, and from steps S41 to S until the determination is made that the process should be terminated. The process loop of S62 is repeatedly executed. In addition, the process of step S42 and below is started in synchronization with the rising edge of the clock signal Clk.

Step S42 determines whether the reset signal RST is active ("0"). If the reset signal RST is active, the reset processing of steps S43 and S44 is executed. That is, both the lock level LL and the process number Pd are set to the initial value "0". On the other hand, if the reset signal RST is in the normal state (" 1 "), processes below step S45, which are ordinary processes, are executed.

Step S45 determines whether the standby state display signal Wt is in the normal state ("0"). When the wait state display signal Wt is not in the normal state, that is, when the current clock cycle is the "standby state", the process goes directly to step S62. In other words, no process is executed in the "standby state."

On the other hand, if the standby state display signal Wt is in the normal state, the value of the extraction signal Dout is compared with the synchronization code Cd in step S46. If the extraction signal Dout coincides with the synchronization code Cd, the processes of steps S47 to S55 are performed, and if not, otherwise, the processes of steps S56 to S61 are performed.

In steps S47 to S55, the values of the process number Pd and the lock level LL are updated based on the current value of the process number Pd and the lock level LL. That is, when the process number Pd is "0", the process number Pd is incremented by the value "1". At this time, if the lock level LL does not reach the upper limit value (value "7" in the following example), the lock level LL is also increased by the value "1".

In contrast, when the process number Pd is not " 0 " (i.e., Pd = 1 to 203), the lock level LL and the process number Pd are set as follows. In other words, when the lock level LL is "0", the process number Pd is set to "1". When the lock level LL is not "0" (i.e., LL = 1 to 7) and the process number Pd is not "203" (ie, Pd = 1 to 202), the process number Pd is increased by "1". . When the lock level LL is not "0" (ie, LL = 1 to 7) and the process number Pd is "203", the process number Pd is returned to the initial value "0".

Also in steps S56 to S61, the values of the process number Pd and the lock level LL are updated based on the current value of the process number Pd and the lock level LL. That is, if the process number Pd is not "203", the process number Pd is increased by "1". In contrast, when the process number Pd is "203", the process number Pd is initialized to "0". The lock level LL is decremented by "1" only when the process number Pd is "0" and the lock level LL is not "0" (that is, LL = 1 to 7).

When the above process ends, the process proceeds to step S62. By repeatedly executing the process of steps S41 to S62, the process number Pd changes in the range of "0" to "203", and the lock level LL changes in the range of "0" to "7". In addition, determination of the reset signal RST of step S42 is performed by the reset determination part 44, and determination of the standby state display signal Wt of step S45 is performed by the standby state determination part 45. FIG.

In addition, the determination of the present value of the process number Pd in steps S47, S50, S56, and S58 and the determination of the present value of the lock level LL in steps S48, S53, and S59 are performed by the lock level generator 42 and the process number. It is executed by both of the generation parts 43. The process number generation unit 43 executes the process of setting the process number Pd in the steps S44, S49, S51, S52, S55, S57, and S61. The lock level generator 42 executes the setting process of the lock level LL in steps S43, S50, S54, and S60.

<2-5. Operation Example of Synchronization Detector>

21 and 22 are operation explanatory diagrams showing an operation example of the synchronization detection unit 31. In these figures, the period corresponding to one packet Pkt is indicated by the symbol "Pkt". In addition, the hatched rectangular frame represents the extraction signal Dout having the same value as the sync code Cd, and the white empty rectangle frame represents the extraction signal Dout having a value that does not match the sync code Cd. In the extraction signal Dout, if the extraction order is not wrong, and no error occurs in the data signal during the communication process, the synchronization code Cd appears at the position of the leading word for each section of the packet Pkt.

Since the reset signal RST is active at the time when the synchronization detector 31 starts to operate, both the process number Pd and the lock level LL are set to the initial value "0". After the reset is released (i.e., the reset signal RST is set to normal), the input of the extraction signal Dout is started. When the synchronization code Cd first appears in the synchronization detector 31, the process number Pd is set to "1" in step S55, and at the same time, the lock level LL is set to "1" in step S54.

Thereafter, the processing number Pd increases by " 1 " for each clock cycle via the steps S55, S56, and S61. Even if the same value as the sync code Cd appears in a position other than the head word of the packet Pkt, as long as the lock level LL is not "0", that is, "1" or more, the processes of steps S48, S50, and S52 are performed. The LL is not updated, and the process number Pd gradually increases to "203".

When the process number Pd reaches "203", the process number Pd returns to "0" by way of step S56, S57 or via steps S48, S50, S52. In the next clock cycle, as shown in Fig. 21, when the synchronization code Cd is found to be normal as the leading word of the packet Ptk, the process number Pd is increased to " 1 " by way of steps S47, S53, S54 and S55. At the same time, the lock level LL is also increased to "2".

Similarly, each time the sync code Cd appears as a leading word of the packet Pkt, the lock level LL rises sequentially as "3", "4", ... When the lock level LL reaches the upper limit value "7", only the process number Pd is increased to "1" by way of steps S47, S53 and S55 even though the synchronization code Cd appears in the head word of the packet Pkt, and the lock level LL is further increased. It remains unchanged and remains at the upper limit value "7". In other words, the lock level LL does not exceed the preset upper limit in any case.

On the other hand, as shown in Fig. 21, when the lock level LL is " 3 ", for example, when the synchronization code Cd does not appear in the head of the next packet Pkt, the process of the synchronization detection unit 31 performs steps S56, S58, Via S59, S60, S61. As a result, the process number Pd is increased to " 1 " and the lock level LL is decreased by " 1 ". That is, the lock level LL falls from "3" to "2".

If the sync code Cd appears at the head of the next packet Pkt, the lock level LL rises again by " 1 ", whereas, as illustrated in FIG. 21, if the sync code Cd does not appear, the lock level LL is further reduced to " 1 ". Also, even in the head of the next packet Pkt, if the sync code Cd does not appear, the lock level LL is reduced and returns to the initial value " 0 ".

When the lock level LL is " 0 ", the process number Pd is set to " 0 " through any of the processing paths of steps S56, S58, S61, or steps S56, S57, unless a match with the sync code Cd appears in the extraction signal Dout. The rise to "20" is repeated, and the lock level LL keeps the value "0".

FIG. 22 shows the operation subsequent to FIG. 21, and indicates the same point in time in which symbols A commonly displayed in FIGS. 21 and 22 are the same. When the lock level LL is "0", the first synchronization code Cd is tentatively treated as the leading word of the packet Pkt. As illustrated in Fig. 22, when the synchronization code Cd appears when the process number Pd is the value "k", the process number Pd is set to "l" by steps S48 and S49, but the lock level LL does not change. Keep 0 ". The process number Pd set to " 1 " corresponds to the fact that the input sync code Cd is tentatively regarded as the head of the packet Pkt, that is, the position of the partition of the packet Pkt is tentatively determined.

Before the next leading word of the tentative packet Pkt appears, i.e., before the process number Pd is initialized to "0" via "203" (when the process number Pd is the value "i" in FIG. 22), the synchronization code Cd When the same data as is shown, since the lock level LL is in a state of "0", the process number Pd is set again to "1" by steps S48 and S49. That is, the position of the head of the tentative packet Pkt is corrected to the position of the new sync code Cd.

Likewise below, when the synchronization code Cd appears before the process number Pd returns to "0" past "2O3" (in FIG. 22, when the process number Pd is the values "j", "p", "q"). Each time, the process number Pd is set to " 1 " so that the position of the head of the tentative packet Pkt is corrected. In that period, the lock level LL remains at " 0 ".

The sync code Cd does not appear until the process number Pd returns to the initial value to "0" via "2O3". Moreover, when the process number Pd becomes "0", that is, the next head of the tentative packet Pkt. When the synchronization code Cd appears at the position of the word, the processing number Pd is increased to " 1 " and the lock level LL is increased to " 1 " at step S47, S53, S54 and S55.

If the lock level LL is "1" or more, as described above, even if the synchronization code Cd appears at a position other than the head word of the packet Pkt, the process number Pd is not set to "1". That is, when the lock level LL rises from "0" to "1", the position of the partition of the tentative packet Pkt is treated definitely. As long as the lock level LL does not return to " 0 ", the position of the partition of the packet Pkt does not change. The operation state of the synchronization device 101 at this time is called "synchronization state". In contrast, if the lock level LL is &quot; 0 &quot;, the partition of the packet Pkt is tentatively handled so that a new partition is always searched for. The operation state of the synchronization device 101 at this time is called "asynchronous state".

When the lock level LL is "1" or more, whenever the sync code Cd appears in the leading word of the packet Pkt, the division of the packet Pkt is likely to be justified, and the lock level LL is "1" until the upper limit is reached. Raise and move away from "0" corresponding to the asynchronous state. On the contrary, each time a value other than the sync code Cd appears in the leading word of the packet Pkt, the lock level LL is lowered by "1" and "0" corresponding to the asynchronous state, reflecting that the partition of the packet Pkt is unlikely to be justified. Approach. When the lock level LL reaches "0", the operation state returns to the asynchronous state. As such, it can be said that the lock level LL is a variable representing the likelihood of the partitioning of the packet Pkt.

In this embodiment, the asynchronous state and the synchronous state are distinguished according to whether the lock level LL is "0" or "1" or more, but the reference value of the lock level LL separating the two states is from "0" to the upper limit. Can be set to any value. For example, it is possible to set the reference value to "2" so as to be asynchronous when the lock level LL is "2" or less and to be in a synchronous state when the lock level LL is "2" or less. In this case, in step S13 (FIG. 10), steps S42, S48, and S59 (FIG. 20), the reference value of the comparison may be changed from "0" to "2".

At this time, only after the synchronization code Cd appears three times in the head word of the tentatively determined packet Pkt, the partition of the tentative packet Pkt is finally determined, and the transition from the asynchronous state to the synchronous state is performed. That is, when the reference value for distinguishing the asynchronous state from the synchronous state is set higher, the transition from the asynchronous state to the synchronous state is performed when the partition of the packet Pkt is more likely to be legitimate. In other words, the higher the reference value, the more careful judgment is made regarding the validity of the division of the packet Pkt.

The purpose of the synchronization device is to legitimately extract, for example, 8-bit unit data assigned to the input data signal Data_In, and to reconstruct the data signal of the packet Pkt format by identifying the partition of the packet Pkt. By introducing a variable called lock level LL into the synchronization device 101, the probability of justification for the partition of the packet Pkt is quantified, and its validity is continuously tested, and the probability increases or decreases depending on the performance. . According to the degree of possibility, the operation state is divided into "asynchronous state" which treats the division of the packet Pkt as provisional, and "synchronous state" which treats as definite. This reduces waste time and allows for less error-prone synchronization.

<2-6. Lead signal generator, etc.>

23 is a flowchart showing the flow of the operation of the head signal generator 32. In this operation flow, the process loops of steps S71 to S78 are repeatedly executed until a determination is made that step S78 should terminate the process. In addition, since step S71 is provided, the process under step S72 is started in synchronization with the rising edge of the clock signal Clk.

Step S72 determines whether the reset signal RST is active ("0"). If the reset signal RST is active, the reset process in step S73 is executed, and the initial signal Sync_Head is set to an initial value " 1 " Thereafter, the process proceeds to step S78. On the other hand, if the reset signal RST is in the normal state ("1"), the process of step S74 or less, which is a normal process, is executed.

Step S74 determines whether the standby state display signal Wt is in the normal state ("0"). If the wait state display signal Wt is not in the normal state, that is, the current clock cycle is the "standby state", the process goes directly to step S78. In other words, no process is executed in the "standby state".

On the other hand, in step S75, if the wait state display signal Wt is in a normal state, it is determined whether or not the value of the process number Pd is "0". If the process number Pd is not an output "0" in step S76, the head signal Sync_Head is set to a steady state ("1"). On the contrary, if the process number Pd coincides with "0" in step S77, , The head signal Sync_head is set to active ("0"). When step S76 or S77 ends, the process proceeds to step S78.

24 is a flowchart showing the flow of operation of the final signal generator 33. The final signal generator 33 operates along the same processing path as the leading signal generator 32 shown in FIG. That is, in step S88, the process loops of steps S81 to S88 are repeatedly executed until a determination is made that the process should be terminated. In addition, the process of step S82 and below is started in synchronization with the rising edge of the clock signal Clk.

Step S82 determines whether the reset signal RST is active ("0"). If the reset signal RST is active, in step S83, the final signal Sync_Tai1 is set to an initial value "1" in a normal state. The process then proceeds to step S88. On the other hand, if the reset signal RST is in the normal state (" 1 "), the process of step S84 or lower which is a normal process is executed.

Step S84 determines whether the standby state display signal Wt is in the normal state ("0"). When the wait state display signal Wt is not in the normal state, that is, when the current clock cycle is the "standby state", the process goes directly to step S88. In other words, no process is executed in the "standby state".

On the other hand, in step S85, if the wait state display signal Wt is in a normal state, it is determined whether or not the value of the process number Pd is "203". If the process number Pd is not "203" in step S86, the final signal Sync_Tai1 is set to a steady state ("1"). On the contrary, if the process number Pd is matched to "203" in step S87. The final signal Sync_Tai1 is set to active ("0"). When step S86 or S87 ends, the process proceeds to step S88.

25 is a flowchart showing the flow of operation of the synchronization signal generator 34. The synchronization signal generator 34 also operates along the same processing path as the head signal generator 32 shown in FIG. That is, in step S98, the process loops of steps S91 to S98 are repeatedly executed until a determination is made that the process should be terminated. Also, the process of step S92 and below is started in synchronization with the rising edge of the clock signal Clk.

Step S92 determines whether the reset signal RST is active ("0"). In step S93, if the reset signal RST is active, the synchronization signal Sync is set to an initial value "0" in a normal state. Thereafter, the process proceeds to step S98. On the other hand, if the reset signal RST is in the normal state (" 1 "), a process of step S94 or lower which is a normal process is executed.

Step S94 determines whether the standby state display signal Wt is in the normal state ("0"). If the wait state display signal Wt is not in the normal state, that is, the current clock cycle is the "standby state", the process proceeds directly to step S98. In other words, no process is executed in the "standby state".

On the other hand, in step S95, if the wait state display signal Wt is in a normal state, it is determined whether or not the value of the process number Pd is "203". If the process number Pd is not "203" in step S96, then the synchronization signal Sync is set to a steady state ("0"). On the contrary, if the process number Pd coincides with "203" in step S97. The sync signal Sync is set to active ("1"). When step S96 or S97 ends, the process proceeds to step S98.

<2-7. Data Output and Clock Modulator>

26 is a flowchart showing the flow of operation of the data output unit 35. Similarly to the head signal generation unit 32 shown in FIG. 23, the data output unit 35 also repeatedly executes the process loops of steps S101 to S106 until a determination is made that the process should be terminated in step S106. . In addition, the process of step S102 and below is started in synchronization with the rising edge of the clock signal Clk.

Step S102 determines whether the reset signal RST is active ("0"). If the reset signal RST is active, in step S103, the output data signal Data_Out is set to an initial value "0". Thereafter, the process proceeds to step S106. On the other hand, if the reset signal RST is in the normal state (" 1 "), the process up to step S104, which is a normal process, is executed.

Step S104 determines whether the standby state indication signal Wt is in the normal state ("0"). If the wait state display signal Wt is not a normal state, that is, the current clock cycle is the "standby state", the process proceeds directly to step S106. In other words, no process is executed in the "standby state". On the other hand, in step S105, if the standby state display signal Wt is in a normal state, the extraction signal Dout is applied to the output data signal Data_Out. When step S105 ends, the process proceeds to step S106.

When the clock cycle is in the "standby state", the process of step S105 is not performed. Therefore, as the output data signal Data_Out, the value of the previous output data signal Data_Out, that is, the value one clock cycle ago, is maintained as it is. Therefore, in the clock cycle of the "waiting state", the output data signal Data_Out is not affected even if the extraction signal Dout is any value.

For this reason, in the "standby state", the pattern selector 23 (Fig. 4) does not necessarily have to hold the immediately preceding extraction signal Dout. In other words, step S25 of FIG. 10 is not essential, and any value may be output as the extraction signal Dout in the "standby state". Alternatively, in the flowchart of FIG. 26, if step S25 is provided, the comparison process of step S104 is deleted, and if the reset signal RST is released, the process of step S105 is always executed regardless of the value of the wait state display signal Wt. The data output part 35 may be comprised as much as possible.

FIG. 27 is a circuit diagram showing the configuration of the clock modulator 3. FIG. The clock modulator 3 includes a flip-flop 51 and a logic element 52. The standby state display signal Wt is input to the data input terminal of the flip-flop 51, and the clock signal Clk is input to the clock input terminal. The output data of the flip-flop 51 is input to the inverting input terminal of the logic element 52, and the clock signal Clk is input to the non-inverting input terminal. The output data of the logic element 52 is output externally as the modulation clock signal MClk.

The flip-flop 51 holds the standby state display signal Wt as an output signal in synchronization with the falling of the clock signal Clk. The logic element 52 is an AND circuit having a non-inverting input terminal and an inverting input terminal, and a logic switch for outputting the clock signal Clk as the modulated clock signal MClk only when the value of the output signal of the flip-flop 51 is "0". Function as.

<2-8. Output signal of synchronization device 101>

28 is a timing chart of various output signals output by the synchronization device 101. One packet Pkt, which is a unit constituting the output data signal Data_Out, contains a signal of 204 bytes, that is, 204 eight-bit unit data. These unit data are output in synchronization with the pulse of the clock signal Clk. Then, the "standby state" for one cycle (one clock cycle) appears every four cycles (four clock cycles) of the clock signal Clk. Thus, the output of one packet Pkt is terminated in 272 clock cycles.

In Fig. 28, " NOP " periodically appearing in the output data signal Data_Out is unit data in the "wait state" and is the same value as the previous unit data. The modulated clock signal MClk is obtained from the clock signal Clk as a clock signal which is missing a pulse only in the "waiting state". In other words, the modulated clock signal MClk is output as a pulse synchronized with only the unit data except for "N0P", that is, meaningful unit data.

The decoder 122 (FIG. 1) following the synchronization device 101 uses this modulated clock signal MClk as a clock signal, so that only meaningful unit data can be processed smoothly. For this purpose, as the modulated clock signal MClk, it is preferable to use the falling edge which is delayed half the period from the rise of the clock signal Clk. To meet this purpose, the modulated clock signal MClk is paused by a half cycle delay from the appearance of " NOP. &Quot;

When the clock cycle is in the "standby state", the standby state display signal Wt, which becomes active, is not only used inside the synchronization device 101 but also output to the outside, so that the "standby state" is transmitted to the external decoder 122 or the like. It also serves to inform. The leading signal Sync_Head is activated when the leading word H of the packet Pkt appears. Therefore, the head signal Sync_Head serves to inform the outside of the appearance of the head word H of the packet Pkt.

The last signal Sync_Tai1 becomes active when the last word T of the packet Pkt appears. In the example of FIG. 28, since "NOP" appears immediately after the final word T, the final signal Sync_Tai1 is active over two clock cycles. As can be seen from the various flow charts described above, all of the various output signals do not change in the "standby state". The final signal Sync_Tai1 serves to inform the outside of the appearance of the final word T of the packet Pkt. The synchronization signal Sync is a signal referred to inside the synchronization device 101 and merely has a logic value opposite to the final signal Sync_Tai1.

In addition, even if the operation state of the apparatus is in the asynchronous state and the division of the packet Pkt is tentative, there is no change in the point at which the various output signals are output at the timing shown in FIG.

As is apparent from the above description, the synchronization device 101 does not require the FIFO 153 provided in the conventional synchronization device 150. As already mentioned, the FIFO 153 needs a storage capacity for storing one packet Pkt data, that is, a storage capacity of 8 x 204 bits. Since the synchronization device 101 does not need to include the FIFO 153 having this excessive storage capacity, the synchronization device 101 can be made smaller and inexpensive.

<3. Example 2

Fig. 29 is a block diagram showing the configuration of the synchronization detector 31 of the synchronization device of the second embodiment. This embodiment is distinctly different from the synchronization detection unit 3l of the first embodiment in that the lock level changing unit 60 is provided in the synchronization detection unit 31. The lock level changing unit 60 instructs the lock level generating unit 42 to change the lock level LL based on the comparison result in the comparing unit 41.

30 is a block diagram showing an internal configuration of the lock level changing unit 60. As shown in FIG. The lock level changing unit 60 is provided with a controller 61, a tag memory 62, and an Np counter (another processing number generation unit) 63. The Np counter 63 counts the process number Np as the second process number different from the process number Pd. The process number Np has a value ranging from "0" to "203".

The tag memory 62 has a rewritable semiconductor memory and stores tags which will be described later. While the controller 61 exchanges data with respect to the tag memory 62 and the Np counter 63, the controller 61 changes the lock level LL to the lock level generator 42 by referring to the comparison result in the comparator 41. Outputs the signal indicated.

31 is a schematic diagram showing one form of the memory space of the tag memory 62. As shown in FIG. In this form, the tag memory 62 prepares a memory space capable of storing N (≧ 1) process number Np values. Since the process number Np is represented by one byte, the tag memory 62 of this type has a storage capacity of 8 x N bits. In the example of FIG. 31, five memory spaces are prepared, and four numerical values of "0", "tl", "t2", and "t3" are stored as tags.

32 is a schematic diagram illustrating another form of the memory space of the tag memory 62. The tag memory 62 of this type is configured to store data of 1 bit length in each of 204 addresses of "0" to "203". Thus, the storage capacity is 204 bits. The value of each data is normally in a steady state (" 0 " in this example), and is set to active (" 1 ") only for address data corresponding to the process number Np to be stored as a tag. As a result, the tag is substantially stored. That is, the tag memory 62 of this type is configured as a flag register.

If the number of unit data constituting the packet Pkt is increased, the form of Fig. 31 is more advantageous than Fig. 32 because less memory capacity is sufficient. On the contrary, when the number of unit data is small, it can be said that the form of FIG. 32 is more advantageous than FIG.

<3-1. Operation of Lock Level Changer>

33 is a flowchart showing the flow of operation of the lock level changing unit 60. Similarly to the head signal generation unit 32 shown in FIG. 23, the lock level changing unit 60 also repeatedly executes the process loops of steps S121 to S140 until it is determined in step S140 that the process should be terminated. . In addition, the process of step S122 and below is started in synchronization with the rising edge of the clock signal Clk.

Step S122 determines whether the reset signal RST is active ("0"). In step S123, if the reset signal RST is active, all tags are erased from the tag memory 62. That is, the stored data of the tag memory 62 is initialized. In addition, in step S124, the process number Np which is the count value in the Np counter 63 is initialized to "0". Thereafter, the process proceeds to step S140.

On the other hand, if the reset signal RST is in the normal state (" 1 "), the process of step S125 or lower which is a normal process is executed. Step S125 determines whether the standby state indication signal Wt is in the normal state ("0"). If the wait state display signal Wt is not in the normal state, that is, the current clock cycle is the "standby state", the process proceeds directly to step S140. In other words, no process is executed in the "standby state". On the other hand, in step S126, if the wait state display signal Wt is in the normal state, it is determined whether the tag is stored in the tag memory 62.

If no tag is stored in step S127, it is determined whether the extraction signal Dout matches the sync code Cd. If there is no match, the process proceeds to step S140. If there is a match, the process proceeds to step S137 described later.

In the determination of step S126, if a tag is stored in the tag memory 62, first, the process number Np is updated in steps S128 to S130. Namely, the process number Np is cyclically increased in the range of "0" to "203". After that, in step S131, it is determined whether or not there is a tag that matches the value of the current process number Np.

In this determination, if there is a matching tag, it is determined in step S132 whether the extraction signal Dout matches the synchronization code Cd. If the extraction signal Dout does not coincide with the synchronization code Cd, in step S133, the tag corresponding to the value of the current processing signal Np is erased from the tag memory 62. Thereafter, the process proceeds to step S140.

In contrast, in the determination of step S132, if the extraction signal Dout coincides with the synchronization code Cd, in step S134, all the tags are erased. In other words, the tag memory 62 is initialized. Subsequently, in step S135, the lock level generator 42 is instructed to change the lock level LL. Next, in step S136, the value of the process number Np is returned to the initial value "0". After that, in step S137, the tag with the value "0" of the process number Np is stored in the tag memory 62. Even when passing through step S127, since the value of the process number Np is "0", the tag of the value "0" is always stored in the tag memory 62 in step S137. Thereafter, the process proceeds to step S140.

In the determination of step S131, if no tag matching the process number Np exists, it is determined in step S138 whether the extraction signal Dout matches the synchronization code Cd. If there is a match, in step S139, after the tag matching the value of the process number Np is stored in the tag memory 62, the process proceeds to step S140. In contrast, if there is no match, the process proceeds directly to step S140.

In the above processes, steps S123, S133, S134, S137, and S139 related to storing and erasing of tags are executed by the tag memory 62 based on the instruction of the controller 61. Further, steps S124, S128, S129, S130, and S136 related to the setting of the process number Np are executed by the Np counter 63 based on the instruction of the controller 61.

<3-2. Operation of Lock Level Changer>

34 is a flowchart showing the flow of operation of the device portion excluding the lock level changing unit 60 in the synchronization detecting unit 31. As shown in FIG. The fact that step S150 is inserted immediately before step S62 is characteristically different from the flow of the operation of FIG. 20. The process of step S150 is performed by the lock level generating unit 42.

35 is a flowchart showing an internal processing path of step S150. When the process of step S150 starts, first in step S151, it is determined whether the lock level LL is "0". If the lock level LL is not "0", the process of step S150 ends, and the process proceeds to step S62. On the contrary, if the lock level LL coincides with "0", it is determined in step S152 whether there is an instruction indicating that the lock level LL from the lock level changing unit 60 should be changed.

If there is no indication of a change, the process of step S150 ends. In contrast, if a change instruction is given, the lock level LL is increased by " 1 " in step S153. In other words, the change instruction executed by step S135 (Fig. 33) means an instruction to raise the lock level LL by " 1 ". When step S153 ends, the entire step S150 ends.

36 is an operation explanatory diagram showing an operation example of the synchronization detection unit 31. This figure shows the operation after the time point A when the data as shown in Figs. 21 and 22 were input at the same timing as the extraction signal Dout. Therefore, the extraction signal Dout and the process number Pd are changed in the same timing as in FIG.

The period in which the value of the lock level LL is "0" and the sync code Cd does not appear lasts longer than the period corresponding to one packet Pkt at the time point A. FIG. For this reason, the tag stored in the tag memory 62 does not exist at the time point A. That is, the tag memory 62 is in the initial state.

When the synchronization code Cd first appears in this state, the tag corresponding to the process number Np ("0") is stored in the tag memory 62 by way of steps S126, S127, and S137. The fact that the tag is stored means that the sync code Cd that has appeared in the process number Np corresponding to the tag may be the leading word of the packet Pkt, and corresponds to the candidate position of the leading word. That is, a tag can be said to represent the candidate position of a head word, ie, the candidate of the division of the packet Pkt, by process number Pd. In Fig. 36, reference numeral "Tg" represents stored data in the tag memory 62. Figs.

In the next clock cycle, the process number Pd is increased to " 1 " by way of steps S126, S128, and S129. In addition, since the data passes through S131, S138, and S140, the stored data of the tag memory 62 is not changed. In the same manner below, the process number Pd continues to rise sequentially for each clock cycle until the next sync code Cd appears, but the stored data of the tag memory 62 is not changed. This operation reflects that no candidate of the partition of the packet Pkt appears in this period.

When the next sync code Cd appears, the process number Np continues to rise to the value "t1" by going through steps S126, S128, and S129. And the tag of the value "t1" is memorize | stored in the tag memory 62 via S131, S138, and S139. That is, at this point in time, there are two tags stored in the tag memory 62, "0" and "1". This means that a new candidate is additionally stored, corresponding to a new appearance of a candidate of the partition of the packet Pkt. Similarly, when the next sync code Cd appears, the value "t2" of the process number Np is added to the tag memory 62.

In the next clock cycle after the clock cycle in which the process number Np becomes "203", the process number Np returns to "0" by step S128 and S130. At this time, 204 clock cycles have elapsed since the synchronization code Cd first appeared. For this reason, a tag (= "0") corresponding to the process number Np (= "0") exists in the tag memory 62. Therefore, step S132 is executed after the determination of step S131.

In this clock cycle, the sync code Cd does not appear. Thus, by executing step S133, the tag with the value "0" is erased. The deletion of a tag reflects the loss of the possibility that the process number Pd corresponding to the tag is a partition of the packet Pkt, that is, the loss of qualification as a candidate for the partition. In Fig. 36, the arrow shown in the stored data Tg of the tag memory 62 indicates the period in which the tag remains, and the symbol " X " indicates that the tag has been erased.

After that, when the synchronization code Cd is newly displayed, the value "t3" of the process number Np is stored in the tag memory 62. That is, at this point in time, the tags stored in the tag memory 62, i.e., the candidates of the partitions, are three of "t1", "t2", and "t3".

In the clock cycle in which the process number Np becomes "t1", the process number Np coincides with the value "t1" of one of the tags stored in the tag memory 62. Therefore, step S132 is executed after the determination of step S131. Also in this clock cycle, the sync code Cd does not appear. Thus, by executing step S133, the tag " t1 " is also erased from the tag memory 62.

In the clock cycle in which the process number Np becomes "t2" (next cycle of the process number Np = "t2-1"), the process number Np coincides with the value "t2" of one of the tags stored in the tag memory 62. . For this reason, after determination of step S131, step S132 is executed. In this clock cycle, the sync code Cd appears. Therefore, by executing step S134, first, all tags are erased from the tag memory 62. FIG. In this manner, in step S135, the change of the lock level LL is instructed.

In addition, in step S136, the process number Np is changed from "t2" to the initial value "0". This corresponds to a change in the criteria of the tag. Thus, in step S137, the newly set value "0" of the process number Np is stored in the tag memory 62 as a tag. That is, at this time, the value of the tag stored in the tag memory 62 is only "0".

Since an instruction to change the lock level LL is given, the value of the lock level LL is increased from " 0 " to " 1 " by step S150 (Fig. 35). Thus, after that, the synchronization device 101 operates similarly to the synchronization state. That is, in this clock cycle, among the plurality of candidates stored in the tag memory 62, the candidates corresponding to the tag "t2" are decidedly treated as the division of the packet Pkt. Tags other than the tag promoted to be confirmed by the candidate are erased in the tag memory 62.

In this way, the validity of the tag as a candidate is tested at the time point when one packet Pkt has passed from tag generation, and if the validity is not satisfied, the tag is immediately deleted. On the contrary, when justification is satisfied, only the satisfied tags remain and also the criteria of the tags are changed. Except at this time, the process number Pd always continues to cyclically increase in the range of "0" to "203".

The lock level changing unit 60 continues the same operation regardless of whether the lock level LL becomes a value of "1" or more. For example, when the process number Pd passes "203" and becomes "0" again, as shown in Fig. 36, if the sync code Cd appears as expected, the process proceeds to steps S126, S131, S132, S134 to S137. For example, even if another tag exists, only a tag having a value of "0" is retained in the tag memory 62.

At this time, the instruction to change the lock level LL is issued in step S135, but since the lock level LL is not " 0 " in step S150 (Fig. 35), the increase of the lock level LL is not executed. In other words, the change instruction is ignored. It is by step S54 (Fig. 34) that the lock level LL is increased from " 1 " to " 2 " in this clock cycle, not from step S150.

As shown in Fig. 36, when the synchronization code Cd newly appears when the process number Pd is the value "t4" in the period in which the lock level LL is "2", the tag "t4" is stored in the tag memory 62. . In this way, the operation of the lock level changing unit 60 itself is not changed even if the lock level LL is " 0 " or more than " 1 ".

As described above, in the synchronization device of the second embodiment, if the synchronization code Cd appears before the process number Pd reaches " 203 ", the position of the appeared synchronization code Cd is assumed as a candidate for the division of the packet Pkt, and one packet is received. The validity is tested when the period corresponding to Pkt has passed. If it is judged that the validity is high, the partition as a candidate is determined and the operation state is shifted from the asynchronous state to the synchronous state. For this reason, as apparent from the comparison between Fig. 22 and Fig. 33, the advantage that the transition time from the asynchronous state to the synchronous state is not unnecessarily delayed is obtained.

Although the synchronization device of the second embodiment requires the tag memory 62, for example, in the example of FIG. 32, a much smaller 204 bit storage capacity is sufficient than the FIFO 153 requiring 8x204 bits. Also in the example of Fig. 31, for example, if N is set to 10, 8x10 = 80 bits is sufficient. In this manner, a device which is much smaller and cheaper than that of the conventional device is realized as in the synchronization device of the first embodiment.

<4. Example 3

37 is a block diagram showing the configuration of the synchronization control unit 2 of the synchronization device of the third embodiment. In the present embodiment, the data output unit 35 differs from the synchronization control unit 2 of the first embodiment in that the data output unit 35 operates with reference to the synchronization code Cd, the lock level LL, and the synchronization signal Sync.

FIG. 38 is a flowchart showing the flow of operation of the data output unit 35 of FIG. The flow of this operation is characteristically different from the flow of the operation in Fig. 26 in that the process of steps S161 to S164 is executed when it is determined in step S104 that the wait state display signal Wt is " 0 ".

In the determination of step S104, when the current clock cycle is not " standby " (i.e., Wt = O), when the synchronization signal Sync does not match " 1 ", i.e., the current clock cycle is a division of the packet Pkt. When the lock level LL is equal to the value &quot; 0 &quot;, i.e., when the operation state of the apparatus is asynchronous, the extraction signal Dout is outputted as the output data signal Data_Out as in step S105 (Fig. 26). .

However, on the contrary, when the synchronization signal Sync coincides with " 1 ", that is, the current clock cycle corresponds to the division of the packet Pkt, and the lock level LL is not the value " 0 " In contrast to step S105 (FIG. 26), when the operation state of P is the synchronous state, the synchronization code Cd, which is the original expected value, is output as the output data signal Data_Out.

39 is an operation explanatory diagram showing an operation example of the synchronization control unit 2. This figure shows the operation when the data as shown in Fig. 21 is input at the same timing as the extraction signal Dout. Therefore, the extraction signal Dout, the process number Pd, and the lock level LL are changed in the same timing as in FIG. However, the output data signal Data_Out does not necessarily coincide with the extraction signal Dout when the lock level LL is "1" or more. That is, the synchronization code Cd always appears in the head word immediately after the division of the packet Pkt regardless of whether the value of the extraction signal Dout matches the synchronization code Cd.

If the division of the packet Pkt is justified, the sync code Cd must appear in the leading word. In the synchronous state, the division of the packet Pkt is determined as having a certain ratio or more reliability. Therefore, in the synchronous state, when the synchronous code Cd does not appear in the leading word, it is highly likely that an error has occurred in the data signal for some reason.

In the data output unit 35 of the present embodiment, even if the value of the extracted signal Dout corresponding to the head word is any value, if the division of the packet Pkt is determined, the synchronization code Cd is given to the output data signal Data_Out corresponding to the head word. This has the advantage that the error is corrected and a correct value is obtained as the output data signal Data_Out.

<5. Variation>

(1) As already mentioned, in general, the L (> m) bit length unit data allocated to the input data signal Data_In composed of a column of unit data of m (≥1) bit length is extracted, and the packet Pkt format is extracted. It is possible to similarly configure the apparatus for outputting the data signal as the output data signal Data_Out. At this time, the shift register 11 has a buffer capable of storing m bits, and the number thereof is uniquely determined by a combination of the values of m and K.

The number K of patterns in which L-bit length unit signals are allocated to a plurality of m-bit length unit data is also determined by a combination of m and L. The pattern data extractor 12 generally includes first to K-th pattern data extractors. When one of the K types of patterns is sequentially extracted in synchronization with the clock signal Clk and output as the extraction signal Dout, the number of "wait states" to be inserted is also determined by the combination of m and L.

(2) In particular, as in the conventional synchronization device 150 illustrated in FIG. 40, when m = 1, the shift register 11 may include only eight buffers capable of storing one bit of data. That is, the shift register 11 is sufficient to have the same structure as the L bit shift register 152 provided in the conventional synchronization device 150. Since there is one type of allocation pattern, the number K of the pattern data extraction units is sufficient to be "1".

The 8-bit unit data extracted by the pattern data extraction section 12 for each clock cycle is selected as the extraction signal Dout only in one clock cycle out of the eight clock cycles, and the remaining seven cycles are in the "wait state". That is, eight types of modes are defined, and only one of them is a mode for selecting the data extracted by the pattern data extraction unit 12 as the extraction signal Dout, and the other seven modes correspond to the "waiting state".

(3) It is also possible to configure a device in which the relationship between the number m and L of unit data is m≥L. At this time, the number of buffers that can store the m bits included in the shift register 11 is two. The "waiting state" is not necessary, and the period for outputting the L bit length unit data as the output data signal Data_Out is set to a length equal to or less than the period for inputting the m bit length unit data as the input data signal Data_In.

In the apparatus of the first aspect of the invention, the position of the head is determined based on the synchronization code Cd, that is, the position of the section of the packet, and the validity of the position of the partition is determined according to each frequency, such as whether the synchronization code appears repeatedly in the head. Verified. In the asynchronous state, the position of the new compartment is always searched. In the synchronous state, the position of the compartment is determined and does not change. Since it is determined based on the process number generated by the process number generation unit, whether or not the extracted signal corresponds to the head word does not require a FIFO for storing one packet of data required by the conventional apparatus. For this reason, the number of elements constituting the apparatus is reduced, so that the apparatus can be miniaturized and the manufacturing cost can be reduced.

In the apparatus of the second aspect of the invention, in an asynchronous state, the processing number returns to a predetermined value whenever the extraction signal and the synchronization code coincide. Then, when the process number returns to the predetermined value via one previous value of the predetermined value, it is determined that the extracted signal corresponds to the candidate or the determined leading word of the leading word. For this reason, a memory for storing the positions of the candidates or the determined leader words of the leading word is not required. In other words, it is possible to obtain the effect that the device is the simplest.

In the apparatus of the third aspect of the invention, in an asynchronous state, the process number added to the extracted signal to which the candidate of the leading word is set is stored as a tag, and then the stored tag and the process number are compared, whereby the extracted signal is the candidate of the leading word. It is determined whether or not Therefore, even when a plurality of sync codes appear between one packet length, a valid candidate can be searched for and shifted to the sync state.

Claims (3)

A first data signal configured on the basis of a packet having a column of first unit data of P (≥2) L (≥1) bit lengths is allocated to a column of second unit data of m (≥1) bit length A synchronization device for inputting a second data signal formed as an input data signal, and reconstructing and outputting the first data signal from the input data signal. A shift register each having a storage capacity of m bits and having a plurality of buffers sequentially holding the second unit data constituting the input data signal; Corresponding to the first through K (≥1) patterns in which the first unit data is sequentially assigned to the second data signal, the L bit length data is extracted from the data held in the shift register, respectively. A pattern data extraction unit for obtaining K-th extraction data; A first comparison section for comparing each of the first to K th extraction data with a synchronization code as a headword mark of the packet; A pattern selector configured to select and output one of the first to K th extracted data as an extracted signal; A state transition control unit controlling a selection operation of the pattern selection unit according to a synchronous state and an asynchronous state; And a synchronization determining unit for determining which of the synchronous state and the asynchronous state, The state transition control unit A mode shift unit configured to cyclically select the first to K th extraction data sequentially into the pattern selection unit so as to sequentially extract data in units of consecutive L bits from the input data signal; In the comparison by the first comparator only in the asynchronous state, whenever only the k (1 ≦ k ≦ K) extraction data matches the sync code, the mode shift unit instructs the pattern selection unit to extract the extracted data. A mode changer for setting the sequential selection to the k-th extraction signal corresponding to the k-th pattern as a candidate of the leading word, and changing the sequential selection to sequential selection based on the starting point; The synchronization determining unit A processing number generation unit capable of cyclically counting P integers as processing numbers in synchronization with the output of the extracted signals; A second comparator for comparing the extracted signal with the sync code; A state determination unit that determines a transition between the synchronous state and the asynchronous state based on the processing number and the result of the comparison in the second comparison unit, In the asynchronous state, the state determining unit is configured to synchronize the extracted signal corresponding to the candidate with the synchronization code if it is repeatedly obtained at a first predetermined frequency or more in the comparison in the second comparing unit. The candidate to be matched at the same time as the determination of the transition to the state is defined as a definite leader, and in the synchronous state, the extraction signal and the synchronization code corresponding to the definite leader are compared in the second comparison unit. If the inconsistency with is repeatedly obtained more than a second predetermined frequency, the transition to the asynchronous state is determined, and the determination of whether the extracted signal corresponds to the candidate or the definite headword is made based on the process number. Synchronization device running by. The method of claim 1, In the asynchronous state, the process number generation unit returns the process number to a predetermined value every time a match between the extraction signal and the synchronization code is obtained in the comparison in the second comparison unit, And the state determining unit judges that the extracted signal corresponds to the candidate or the determined headword when the process number returns to the predetermined value after passing the value before one of the predetermined values. The method of claim 1, The state determination unit further includes a tag storage unit, The state judging section stores the process number when the extraction signal to which the candidate is set is output in the tag storage unit as a tag in an asynchronous state, and then stores the process number with the tag stored in the tag storage unit. And a comparison device determines whether the extracted signal corresponds to the candidate.