JPH05276061A - Frequency conversion circuit - Google Patents

Abstract

PURPOSE:To obtain the frequency conversion circuit with small power consumption and a small circuit scale not requiring a low pass filter. CONSTITUTION:A frequency divider 503 outputs a signal resulting from 1/2 frequency-dividing a sampling clock signal to drive a D flip-flop 502 as a frequency conversion signal. An exclusive OR element 501 multiplies an input signal whose frequency is to be converted with a frequency conversion signal. An output signal of the exclusive OR element 501 is inputted to the D flip-flop 502 driven by the sampling clock signal. Thus, the D flip-flop 502 samples an output signal of the exclusive OR element 501 by a signal whose frequency is twice the frequency of the frequency conversion signal. A signal whose frequency is lower than the frequency of the input signal is obtained from the D flip-flop 502.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a frequency conversion circuit which is an elemental technology in the field of general communication, and more particularly to a frequency conversion circuit for converting a signal frequency to a lower level.

[0002]

2. Description of the Related Art Frequency conversion circuits for converting signal frequencies to lower frequencies are frequently used in receivers for wireless communication.
Hereinafter, a conventional frequency conversion circuit for converting a signal frequency to a lower level will be described with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a conventional frequency conversion circuit. In the figure, 201 is a multiplier and 202 is a low-pass filter.

Next, the operation will be described. In FIG. 2, the input signal whose frequency is to be converted is multiplied by the frequency conversion signal by the multiplier 201. Here, the frequency of the input signal is f1 (Hz) and the frequency of the frequency conversion signal is f2.
(Hz), and the relationship given by the following equation is established between f1 and f2. 0 <f2 <2f1

An input signal of frequency f1 (Hz) and f2 (H
z) which is the result of multiplying the signal for frequency conversion of 2)
01 output signal has f1 + f2 (Hz) and | f1
A frequency component of -f2 | (Hz) appears. Considering the above-mentioned relationship between f1 and f2, the relationship given by the following equation is established. │f1 -f2 │ <f1 <f1 + f2

The output signal of the multiplier 201 is input to the low pass filter 202. The low-pass filter 202 has a frequency f1 + f2 (Hz) that appears in the output signal of the multiplier 201.
Among the components of | f1 −f2 | (Hz) and | f1 −f2 | (Hz), only the component of low frequency component | f1 −f2 | (Hz) is passed, and the component of high frequency component f1 + f2 (Hz) is blocked.

Therefore, from the low-pass filter 202,
A frequency-converted signal having a frequency of f1 -f2 | (Hz) is output. As mentioned above | f1 -f2 |
The frequency (Hz) is lower than the frequency f1 (Hz) of the input signal. That is, the frequency-converted signal output from the low-pass filter 202 is the input signal converted to a lower frequency.

[0008]

As described above, the conventional frequency conversion circuit uses the low-pass filter to remove the high frequency component appearing in the output signal of the multiplier, that is, the component of f1 + f2 (Hz). However, since the low-pass filter is generally complicated in structure, there is a problem that the circuit scale and power consumption tend to be large.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a frequency conversion circuit which does not require a low-pass filter and therefore has a small circuit scale and low power consumption.

[0010]

A frequency conversion circuit according to the present invention comprises a multiplier for multiplying an input signal whose frequency is to be converted by a frequency conversion signal, and an output signal of the multiplier for the frequency conversion signal. And a sampling device for sampling at a frequency twice as high as the above.

[0011]

In the frequency conversion circuit according to the present invention, f1 + f2 (appears in the output signal of the multiplier due to the aliasing phenomenon of the sampler that samples the output signal of the multiplier at twice the frequency conversion signal. The frequency component of (Hz) appears as a frequency component of | f1 -f2 | (Hz) in the output signal of the sampler. Therefore, the sampler outputs a signal having only the desired converted frequency of | f1 -f2 | (Hz).

[0012]

EXAMPLES Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 501 is an exclusive OR element as a multiplier, 502 is a D type flip-flop as a sampler, and 503 is a component that divides a clock signal for driving the D type flip-flop 502 as a sampler into two. It is a circulator.

Next, the operation will be described. Frequency divider 50
3 is a D-type flip-flop 502 as a sampler
A clock signal (hereinafter, referred to as “sampling clock signal”) that drives the signal is divided into two and is output as a frequency conversion signal. That is, when the frequency of the sampling clock signal is fs (Hz), the frequency of the frequency conversion signal is fs / 2 (Hz).

On the other hand, it is assumed that the input signal whose frequency is to be converted is a digital signal which takes only two values of logic "0" and logic "1". The frequency of the input signal is f1
(Hz), and the relationship given by the following equation is established between f1 and fs / 2, which is the frequency of the frequency conversion signal, as in the conventional example. 0 <fs / 2 <2f1

The exclusive OR element 501 is similar to the input signal whose frequency is to be converted, and is also a logic "0" and a logic "1".
The exclusive OR operation is performed with the frequency conversion signal that takes only two values. Considering that the logical "0" is converted into the numerical value "+1" and the logical "1" is converted into the numerical value "-1", the exclusive OR operation is converted into multiplication. That is, the exclusive OR element 501 acts as a multiplier that multiplies the input signal and the frequency conversion signal.

Therefore, the output signal of the exclusive OR element 501 is the input signal of frequency f1 (Hz) and the frequency fs / 2.
It is a product of the frequency conversion signal of (Hz). Therefore, the output signal of the exclusive OR element 501 has frequencies f1 + fs / 2 (Hz) and | f1 -fs / 2 | (H
The component of z) appears. Considering the above-mentioned relationship between f1 and fs / 2, the relationship given by the following equation is established. │f1 -fs / 2│ <f1 <f1 + fs / 2

The output signal of the exclusive OR element 501 is input to the D type flip-flop 502 as a sampler. The frequency of the D type flip-flop 502 is fs
Since it is driven by the sampling clock signal of (Hz),
The output signal of the exclusive OR element 501 will be sampled at fs (Hz). Here, it is assumed that the relationship expressed by the following equation holds. │f1 -fs / 2│ <fs / 2

This relationship is based on the frequency of the low frequency component appearing in the output signal of the exclusive OR element 501, that is, | f.
1-fs / 2 | (Hz) is the sampling Nyquist frequency fs
It means that it is lower than / 2 (Hz). Therefore, according to the sampling theorem, the component of the frequency | f1 −fs / 2 | (Hz) appearing in the output signal of the exclusive OR element 501 is also unchanged in the frequency | f1 −fs as the output signal of the D-type flip-flop 502. It is obvious that it appears as a component of / 2 | (Hz).

Considering this relationship and the fact that f1> 0, it is clear that the relationship expressed by the following equation holds between fs and f1. 0 <f1 <fs

From this, the relationship given by the following equation is established. fs / 2 <f1 + fs / 2 <3fs / 2

This inequality represents a high frequency component appearing in the output signal of the exclusive OR element 501, that is, f1 + fs
It represents the possible frequency range of the component of / 2 (Hz).

Like the component of frequency f1 + fs / 2 (Hz) appearing in the output signal of the exclusive OR element 501, f
Frequency F (Hz) that satisfies the condition of s / 2 <F <3fs / 2
When a signal with is input to the D-type flip-flop 502, this signal will be sampled at the frequency fs (Hz). In this case, the sampling Nyquist frequency fs
Since a signal having a frequency higher than / 2 (Hz) is sampled, a so-called aliasing phenomenon occurs, and | F-fs | is output to the D-type flip-flop 502.
A frequency component of (Hz) appears. This aliasing phenomenon is described in, for example, the document “Spectral Analysis” (Mikio Hino, Asakura Shoten, 1977, pp.175-pp.177).

Therefore, the high frequency component appearing in the output signal of the exclusive OR element 501, that is, f1 + fs / 2
The component of (Hz) is | f1 + fs in the output signal of the D type flip-flop 502 due to the aliasing phenomenon.
It appears as a frequency component of / 2-fs | = | f1-fs / 2 | (Hz).

As described above, the frequencies f1 + fs / 2 (Hz) and | f appearing in the output signal of the exclusive OR element 501.
Both of the components of 1-fs / 2 | (Hz) have a frequency of | f1−fs in the output signal of the D-type flip-flop 502.
Appears as a component of / 2 | (Hz). That is, | f1 -fs / 2 | (H
The frequency-converted signal having only the frequency z) is output. As mentioned above | f1 -fs / 2 |
The frequency (Hz) is lower than the frequency f1 (Hz) of the input signal. That is, the frequency-converted signal output from the D-type flip-flop 502 is the input signal converted to a lower frequency.

As described above, since the frequency signal of the difference is output to the output of the sampler by the sampling action of the D type flip-flop 502 as the sampler, the low-pass filter which is necessary in the conventional example is unnecessary. Becomes In general, the D-type flip-flop has a smaller circuit size and power consumption than a low-pass filter, and therefore has a smaller circuit size and power consumption than the conventional example.

[0026]

As described above, according to the frequency conversion circuit of the present invention, a multiplier that multiplies an input signal whose frequency is to be converted by a frequency conversion signal, and an output signal of the multiplier is used as the frequency converter. By providing a sampler that samples at a frequency twice that of the conversion signal, a low-pass filter is not required, and therefore a frequency conversion circuit with a small circuit scale and low power consumption can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a frequency conversion circuit according to the present invention.

FIG. 2 is a configuration diagram showing a configuration of a conventional frequency conversion circuit.

[Explanation of symbols]

 201 multiplier 501 exclusive OR element 502 D type flip-flop 503 frequency divider

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[Procedure amendment]

[Submission date] September 29, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008]

As described above, the conventional frequency conversion circuit uses the low-pass filter to remove the high frequency component appearing in the output signal of the multiplier, that is, the component of f1 + f2 (Hz). but generally a low pass filter for construction is complicated, there is a problem that the circuit scale and power consumption tends to increase.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

As described above, in this embodiment, the absolute value of the difference between the frequencies of the input signal and the frequency conversion signal is obtained by the sampling action of the D-type flip-flop 502 as the sampler.
Since only a signal having a frequency of is output, the low-pass filter, which was necessary in the conventional example, is not necessary. Generally D
Since the type flip-flop has a smaller circuit size and power consumption than the low-pass filter, the circuit size and power consumption of this embodiment are also smaller than those of the conventional example.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Reference Signs] 501 exclusive OR element 502 D type flip-flop 503 frequency divider

Claims (1)

[Claims] 1. A multiplier that multiplies an input signal whose frequency is to be converted by a frequency conversion signal, and a sampler that samples the output signal of the multiplier at a frequency twice that of the frequency conversion signal. A frequency conversion circuit comprising: