JPS58172250U - MSK modulation circuit - Google Patents

MSK modulation circuit

Info

Publication number
JPS58172250U
JPS58172250U JP6819582U JP6819582U JPS58172250U JP S58172250 U JPS58172250 U JP S58172250U JP 6819582 U JP6819582 U JP 6819582U JP 6819582 U JP6819582 U JP 6819582U JP S58172250 U JPS58172250 U JP S58172250U
Authority
JP
Japan
Prior art keywords
circuit
frequency
frequency divider
modulation circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6819582U
Other languages
Japanese (ja)
Inventor
千田 茂
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP6819582U priority Critical patent/JPS58172250U/en
Publication of JPS58172250U publication Critical patent/JPS58172250U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来から用いられている変調回路の一例を示す
回路図、第2図は第1図の回路のタイムチャート、第3
図はこの考案の一実施例を示す回路図、第4図は第3図
の回路のタイムチャート、第5図はこの考案の他の実施
例を示す回路図、第6図は第5図の回路のタイムチャー
トである。 −1・・・・・・可変分周回路、10.18・・・・・
・抵抗、11・・・・・・演算増幅器、15・・・・・
・サンプリング回路(フリップフロップ)、16・・・
・・・2N分周回路、17・・・・・・論理変換回路。 (0) (b) (C) (d) (e) (f) 第5図
Figure 1 is a circuit diagram showing an example of a conventionally used modulation circuit, Figure 2 is a time chart of the circuit in Figure 1, and Figure 3 is a circuit diagram showing an example of a conventional modulation circuit.
The figure is a circuit diagram showing one embodiment of this invention, Fig. 4 is a time chart of the circuit of Fig. 3, Fig. 5 is a circuit diagram showing another embodiment of this invention, and Fig. 6 is a circuit diagram of the circuit of Fig. 5. This is a time chart of the circuit. -1...Variable frequency divider circuit, 10.18...
・Resistor, 11... Operational amplifier, 15...
・Sampling circuit (flip-flop), 16...
...2N frequency divider circuit, 17...logic conversion circuit. (0) (b) (C) (d) (e) (f) Figure 5

Claims (1)

【実用新案登録請求の範囲】 搬送波周波数foとビットレート周波数f、との間に p fo=7(2に+、1) (但しkは1より大きい正の整数) の関係を有するMSK(ミニマムシフトキーイン、  
グ)変調回路において、外部から供給されるクロック信
号を所定の分周比で分周する可変分周回路と、その可変
分周回路の出力を2N(Nは正の整数)分周する2N分
周回路と、その2N分周回路の出力信号のうち(N−1
)段目の分周回路の出力信号によって外部から供給され
る入力データをサンプリングするサンプリング回路と、
前記2N分周回路の複数の出力信号をもとに階段波を作
成するための信号変換回路とから構成され、前記可変分
周器の分周比は前記サンプリング回路の出力信号に応じ
て制御されることを特徴とするMSK変調回路。
[Claims for Utility Model Registration] MSK (minimum) having the relationship p fo = 7 (2 +, 1) (k is a positive integer greater than 1) between the carrier wave frequency fo and the bit rate frequency f. shift key in,
(G) In a modulation circuit, there is a variable frequency divider circuit that divides the clock signal supplied from the outside at a predetermined frequency division ratio, and a 2N frequency divider that divides the output of the variable frequency divider circuit by 2N (N is a positive integer). Of the output signals of the frequency circuit and its 2N frequency dividing circuit, (N-1
) a sampling circuit that samples input data supplied from the outside based on the output signal of the frequency divider circuit in the second stage;
and a signal conversion circuit for creating a staircase wave based on the plurality of output signals of the 2N frequency divider, and the frequency division ratio of the variable frequency divider is controlled according to the output signal of the sampling circuit. An MSK modulation circuit characterized by:
JP6819582U 1982-05-11 1982-05-11 MSK modulation circuit Pending JPS58172250U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6819582U JPS58172250U (en) 1982-05-11 1982-05-11 MSK modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6819582U JPS58172250U (en) 1982-05-11 1982-05-11 MSK modulation circuit

Publications (1)

Publication Number Publication Date
JPS58172250U true JPS58172250U (en) 1983-11-17

Family

ID=30077982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6819582U Pending JPS58172250U (en) 1982-05-11 1982-05-11 MSK modulation circuit

Country Status (1)

Country Link
JP (1) JPS58172250U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5176955A (en) * 1974-09-18 1976-07-03 Ibm

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5176955A (en) * 1974-09-18 1976-07-03 Ibm

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