JPH05275538A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide the flattered and multilayered semiconductor integrated circuit device capable of forming a resist in stably overhang shape as well as being easily manufactured by lifting-off step. CONSTITUTION:The title manufacturing method of semiconductor integrated circuit device is composed of the four steps enumerated as follows i.e., the first step of forming a polyimide base resin layer 24 (27) on a Si substrate 21, the second step of forming positive type photoresist 25 on the polyimide base resin layer 24 to be processed so that the solubility of the polyimide base resin 24 to the same solvent solving the region sensitized by the resin 24 and the positive type photoresist 25 using the developing pattern of the photoresist 25 as a mask may exceed the solubility of the photoresist 25, the third step of etching away the photoresist 25 in overhang shape to form the first layer conductor metal 26 on the whole surface and the fourth step of removing the positive type photoresist 25 to form the second layer conductor metal 29.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a method of manufacturing an integrated circuit device having wiring conductors formed in multiple layers.

[0002]

2. Description of the Related Art Heretofore, as a device of this kind, Nikkei Electronics 1977.11.28 Atsushi Saiki, Kouki Mukai
Ichiro, Seiki Harada "Using Polyimide Resin for Multilayer Wiring and Surface Protection Film of Transistors and ICs", No. 102-
There is one described on page 123, which is generally constituted by Al as a conductor and a CVD, PSG or SiO ₂ film as an insulating film. In this structure, Al film and PSG
Due to the step difference caused by the film, a short circuit between the wiring layers and a disconnection of the wiring layers are likely to occur. Further, due to the step, there is a limit to miniaturization of wiring. Therefore, attempts are being made to improve such a step structure to provide a flattened structure. As one method for realizing the wiring of this flattening structure,
A known method is to form a predetermined insulating layer, then selectively metallize a portion corresponding to the wiring layer, and further form the wiring layer and the insulating layer so as to have the same thickness.

The prior art will be described below with reference to the sectional view of FIG. In the figure, 1 is a silicon substrate, 2 is a diffusion layer,
3 is a SiO ₂ film. In addition, 4 is a CVD Al ₂ O ₃ film formed as an insulating layer, 5 is a photoresist, 6 is a first layer Al as a wiring conductor, and 7 is a P formed as an insulating layer.
SG (phosphorus silicate glass), 8 is a contact hole, and 9 is a second layer Al as a wiring conductor.

The manufacturing method of the prior art will be described below step by step. First, as shown in FIG. 4A, the diffusion layer 2
CVD (Chemical Vapor De) using oxidation or thermal decomposition of a compound on the silicon substrate 1 on which
An Al ₃ O ₃ film as the insulating layer 4 is formed on the entire surface by a thin film technique such as position: deposition by vapor phase chemical reaction). After that, after applying photoresist to the entire surface,
A resist pattern 5 of a predetermined insulating layer is formed by photolithography technique.

Thereafter, using this resist pattern 5 as a mask, Al ₃ O ₃ is dissolved and removed, and then the wiring layer is formed. After that, the Al film 6 to be the first layer is formed on the entire surface of the photoresist formed in the pattern of the insulating layer by using a thin film technique such as vapor deposition. After that, FIG.
As shown in (b), by dissolving the photoresist using a solvent such as acetone, the Al film on the resist is also floated and removed, and the unnecessary Al film is selectively removed. This method is generally called a lift-off method. In the lift-off method, as shown in FIG. 5, the photoresist 10 generally needs to have an overhang shape. That is, in FIG. 5A, an overhang-shaped photoresist 10 is formed on the substrate, and a metal film 11 is formed thereon as shown in FIG. 5B. As shown, the photoresist 10 is removed and a pattern of the metal film 11 is formed. As a result, the step coverage of the metal film 11 between the photoresist and the underlying layer is deteriorated, so that a solvent such as acetone can easily enter, and the metal film 11 itself is cut off at the time of film formation. The metal film can be easily peeled off.

Next, as shown in FIG. 4C, a PSG film 7 which is a second insulating film is formed by using a thin film technique such as a CVD method using the oxidation of SiH ₄ + PH ₃ and thereafter. , A contact hole 8 with the first layer Al6 of the first layer is formed by using a photolithography technique, and a second layer A is formed thereon.
19 is formed by using a thin film technique, a second wiring layer is formed by using a photolithography technique, and the planarization structure is completed.

[0007]

However, since the lift-off method is used in the above-mentioned apparatus having the conventional structure, it is necessary to form the photoresist 5 which is the etching mask of the insulating layer 4 in an overhang shape. However, in general, it is difficult to form a positive resist, which is easy to develop and peel off, into an overhang shape because of its developing characteristics. Therefore, there is an attempt to obtain an overhang shape by using a negative resist which is difficult to develop and peel. Even if a resist having an overhang shape is formed, when Al ₂ O ₃ , Si ₃ N ₄ or the like is used as the insulating layer 4, if wet etching using hot phosphoric acid is carried out, the photoresist becomes the etchant. Intolerable. Therefore, an additional step of forming a mask pattern with SiO ₂ or the like on the insulating layer 4 is required, and lift-off itself cannot be performed with SiO ₂ , and a new photoresist pattern is again formed after etching the insulating layer 4. Need to be formed. Further, as the etching of the insulating layer 4, plasma etching (for example, Si ₃ N ₄ as the insulating layer 4 is performed).
It is also possible to carry out etching with CF ₄ plasma), but it was difficult to maintain the overhang shape of the resist because the resist was attacked by the plasma reaction.

As described above, it is difficult to form the photoresist in an overhang shape in the apparatus having the above structure, and therefore, it is difficult to form the Al pattern by the lift-off method with stable yield. .. In order to eliminate the above-mentioned problems, the present invention uses polyimide as an insulating layer, uses a normal positive resist as a photoresist, and makes the solubility of polyimide in a developing solution larger than the solubility of a positive resist in a developing section in a developing section. Thus, the present invention aims to provide a method for manufacturing a flattened and multilayered semiconductor integrated circuit device, in which a resist having an overhang shape can be stably formed, and which can be easily manufactured by a lift-off method. To do.

[0009]

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor integrated circuit device, which comprises a step of forming a polyimide resin layer as an insulating layer on a substrate, and the polyimide resin. The step of forming a positive photoresist on the layer, and the solubility of the polyimide resin in the same solvent that dissolves the exposed area of the polyimide resin layer and the positive photoresist using the development pattern of the positive photoresist as a mask. A step of etching the positive photoresist into an overhang shape by treating it so as to have a solubility higher than that of the positive photoresist; a step of forming a conductive metal on the entire surface; and a step of removing the positive photoresist by a lift-off method to remove the conductive metal And a step of forming a pattern.

[0010]

According to the present invention, as described above, in a semiconductor integrated circuit device, a polyimide resin is used as an insulating layer and a positive photoresist is used as a photoresist, and both of them have different solubility in a developing solution. (Polyimide> photoresist) to expose the circuit pattern, develop with photoresist developing solution, and etch polyimide resin at the same time. The conductor metal pattern is formed by using the lift-off method with the above solvent.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of a manufacturing process of a semiconductor integrated circuit device showing an embodiment of the present invention. First, Fig. 1
As shown in (a), a diffusion layer 22 and a SiO ₂ film 23 are formed on a base material on which a pattern is formed, for example, a Si substrate 21, and a polyimide resin 24 is spin-coated on the diffusion layer 22 and the SiO ₂ film 23. After curing the polyimide resin, the film thickness was made the same as the required conductor film thickness, and was 1 μm here. Examples of the polyimide-based resin include PSI-S-5 manufactured by Chisso Corporation.
001-A with a viscosity of 125 centipoise (cP
spin coating at a rotation speed of 2000 rpm for about 30 seconds. Then, a heat treatment at 130 ° C. for 30 minutes was performed as a cure for the polyimide resin. The temperature and time of this heat treatment determine the solubility of the polyimide resin in the photoresist developing solution [here, TMA (tetramethylammonium) 0.26 N aqueous solution]. The present invention is intended to form an overhang shape by making the solubility of the polyimide resin larger than the solubility of the photosensitive portion of the photoresist formed thereon.

FIG. 2 shows the curing temperature and the etching rate (dissolved thickness per unit time) for the developing solution. In this figure, the horizontal axis shows the curing temperature (° C.) of the polyimide resin, and the vertical axis shows the solubility (μm / min) of the polyimide in TMA (tetramethylammonium). Next, a positive photoresist 25 is applied on the polyimide resin layer 24. As the resist, for example, RC120 manufactured by Shipley Co., Ltd. was used, and it was applied to a thickness of 3 μm by a roll coater and baked at 90 ° C. for 10 minutes.

Next, as shown in FIG. 1B, the circuit pattern is exposed by a photolithography technique, the positive photoresist 25 is developed with a developing solution, and the polyimide resin is dissolved using this as a mask. Both are patterned. The development is carried out by using a dipping and stirring method in a TMA 0.26N aqueous solution at 25 ° C., followed by rinsing with deionized water and baking at 90 ° C. for 1 hour.

FIG. 3 shows the cross-sectional shape of the resist formed by this process. Then, in order to remove the residue such as polyimide remaining in the portion corresponding to the wiring layer, ashing was performed with O ₂ plasma. Then, as shown in FIG. 1C, an Al conductor is used as the conductor metal 26 of the first layer.
A film is formed by the μm vapor deposition method. The film formation was performed at a substrate temperature of about 100 ° C. to prevent the resist from being deformed.

Next, as shown in FIG. 1 (d), a lift-off solvent was immersed in butyl acetate, and ultrasonic waves were applied to perform lift-off to form a pattern.
Then, the polyimide resin is cured at 350 ° C. to complete the imidization. Next, as shown in FIG. 1 (e), a polyimide resin layer 27 is applied and cured again as a second insulating layer, and a contact hole 28 is formed by a photolithography technique. Two
An Al conductor is formed as the conductor metal 29 of the layer, a second wiring layer is formed by using the photolithography technique, and the flattening structure is completed.

The present invention is not limited to the two-layer wiring structure, and the contact hole 28 is formed, and the lift-off process is performed after the second-layer wiring layer. It is also possible to do so. In addition, in order to reduce the connection resistance of the conductor between each layer, the O ₂
After plasma ashing, it is better to remove the oxide film on the contact surface of the Al surface with an Al etching solution such as phosphoric acid.

In the first embodiment, the overhang shape is formed by increasing the etching rate of the polyimide resin, but it can also be achieved by reducing the etching rate of the positive photoresist. it can. This will be described below as a second embodiment. Second
In this example, the curing temperature after the application of the polyimide resin is set to 160 ° C. to reduce the solubility of the polyimide resin in TMA. Next, a positive photoresist is applied thereon, exposed to light, and developed to form a pattern of the positive photoresist. At this time, since the polyimide resin has reduced solubility in the developer (TMA), it is hardly dissolved until the photosensitive portion of the positive photoresist is completely dissolved. After that, UV cure treatment (after resist development, UV light irradiation (220 to 270 nm, 8 mW
/ Cm ² , 15 minutes) and then baked at 90 ° C. for 1 hour] to cure the positive photoresist and make it insoluble in a developing solution. After this, again soak in the developer,
When the stirring is performed, the etch rate of the positive photoresist is considerably smaller than the etch rate of the polyimide resin, so that the polyimide resin is dissolved earlier and becomes an overhang shape.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0019]

As described in detail above, according to the present invention, a polyimide resin is used as an insulating layer, and a positive photoresist is used as a photoresist for processing the same.
Since either of them is treated so as to have a difference in solubility with respect to the developing solution, the overhang-shaped resist can be stably formed.

Therefore, it is possible to easily selectively metallize the portion of the insulating layer portion corresponding to the subsequent wiring layer by the lift-off method. Further, if the wiring layer and the insulating layer are formed to have the same thickness, a flattened multi-layer integrated circuit device can be realized without causing a step between them.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor integrated circuit device showing an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a curing temperature of a polyimide resin and a solubility of the polyimide resin in TMA in a manufacturing process of a semiconductor integrated circuit device showing an embodiment of the present invention.

FIG. 3 is a perspective view showing a cross-sectional shape of a resist-polyimide resin film in a manufacturing process of a semiconductor integrated circuit device showing an embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process of a conventional semiconductor integrated circuit device.

FIG. 5 is an explanatory diagram of a conventional lift-off method.

[Explanation of symbols]

21 Si Substrate 22 Diffusion Layer 23 SiO ₂ Film 24, 27 Polyimide Resin Layer 25 Positive Photoresist 26 First-Layer Conductor Metal (Al) 28 Contact Hole 29 Second-Layer Conductor Metal (Al)

Claims (3)

[Claims] 1. A step of: (a) forming a polyimide resin layer as an insulating layer on a substrate; (b) forming a positive photoresist on the polyimide resin layer; and (c) a positive photoresist. With the development pattern as a mask, the polyimide-based resin layer and the positive-type photoresist are treated so that the solubility of the polyimide-based resin in the same solvent that dissolves the exposed region of the positive-type photoresist is larger than that of the positive-type photoresist. A step of etching the photoresist into an overhang shape; (d) a step of forming a conductive metal on the entire surface; and (e) a step of removing the positive photoresist by a lift-off method and forming a conductive metal pattern. A method for manufacturing a semiconductor integrated circuit device having a feature. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the curing temperature of the polyimide resin layer is set so that the solubility of the polyimide resin is higher than that of the positive photoresist. 120
A method of manufacturing a semiconductor integrated circuit device, characterized in that the temperature is ± 20 ° C. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the positive photoresist after development is treated with UV light so that the solubility of the polyimide resin is higher than that of the positive photoresist. A method for manufacturing a semiconductor integrated circuit device, which comprises irradiating.